1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 /*
3 * Atmel SMC (Static Memory Controller) regist
4 *
5 * Copyright (C) 2014 Atmel
6 * Copyright (C) 2014 Free Electrons
7 *
8 * Author: Boris Brezillon <boris.brezillon@fr
9 */
10
11 #ifndef _LINUX_MFD_SYSCON_ATMEL_SMC_H_
12 #define _LINUX_MFD_SYSCON_ATMEL_SMC_H_
13
14 #include <linux/kernel.h>
15 #include <linux/of.h>
16 #include <linux/regmap.h>
17
18 #define ATMEL_SMC_SETUP(cs)
19 #define ATMEL_HSMC_SETUP(layout, cs)
20 ((layout)->timing_regs_offset + ((cs)
21 #define ATMEL_SMC_PULSE(cs)
22 #define ATMEL_HSMC_PULSE(layout, cs)
23 ((layout)->timing_regs_offset + ((cs)
24 #define ATMEL_SMC_CYCLE(cs)
25 #define ATMEL_HSMC_CYCLE(layout, cs)
26 ((layout)->timing_regs_offset + ((cs)
27 #define ATMEL_SMC_NWE_SHIFT
28 #define ATMEL_SMC_NCS_WR_SHIFT
29 #define ATMEL_SMC_NRD_SHIFT
30 #define ATMEL_SMC_NCS_RD_SHIFT
31
32 #define ATMEL_SMC_MODE(cs)
33 #define ATMEL_HSMC_MODE(layout, cs)
34 ((layout)->timing_regs_offset + ((cs)
35 #define ATMEL_SMC_MODE_READMODE_MASK
36 #define ATMEL_SMC_MODE_READMODE_NCS
37 #define ATMEL_SMC_MODE_READMODE_NRD
38 #define ATMEL_SMC_MODE_WRITEMODE_MASK
39 #define ATMEL_SMC_MODE_WRITEMODE_NCS
40 #define ATMEL_SMC_MODE_WRITEMODE_NWE
41 #define ATMEL_SMC_MODE_EXNWMODE_MASK
42 #define ATMEL_SMC_MODE_EXNWMODE_DISABLE
43 #define ATMEL_SMC_MODE_EXNWMODE_FROZEN
44 #define ATMEL_SMC_MODE_EXNWMODE_READY
45 #define ATMEL_SMC_MODE_BAT_MASK
46 #define ATMEL_SMC_MODE_BAT_SELECT
47 #define ATMEL_SMC_MODE_BAT_WRITE
48 #define ATMEL_SMC_MODE_DBW_MASK
49 #define ATMEL_SMC_MODE_DBW_8
50 #define ATMEL_SMC_MODE_DBW_16
51 #define ATMEL_SMC_MODE_DBW_32
52 #define ATMEL_SMC_MODE_TDF_MASK
53 #define ATMEL_SMC_MODE_TDF(x)
54 #define ATMEL_SMC_MODE_TDF_MAX
55 #define ATMEL_SMC_MODE_TDF_MIN
56 #define ATMEL_SMC_MODE_TDFMODE_OPTIMIZED
57 #define ATMEL_SMC_MODE_PMEN
58 #define ATMEL_SMC_MODE_PS_MASK
59 #define ATMEL_SMC_MODE_PS_4
60 #define ATMEL_SMC_MODE_PS_8
61 #define ATMEL_SMC_MODE_PS_16
62 #define ATMEL_SMC_MODE_PS_32
63
64 #define ATMEL_HSMC_TIMINGS(layout, cs)
65 ((layout)->timing_regs_offset + ((cs)
66 #define ATMEL_HSMC_TIMINGS_OCMS
67 #define ATMEL_HSMC_TIMINGS_RBNSEL(x)
68 #define ATMEL_HSMC_TIMINGS_NFSEL
69 #define ATMEL_HSMC_TIMINGS_TCLR_SHIFT
70 #define ATMEL_HSMC_TIMINGS_TADL_SHIFT
71 #define ATMEL_HSMC_TIMINGS_TAR_SHIFT
72 #define ATMEL_HSMC_TIMINGS_TRR_SHIFT
73 #define ATMEL_HSMC_TIMINGS_TWB_SHIFT
74
75 struct atmel_hsmc_reg_layout {
76 unsigned int timing_regs_offset;
77 };
78
79 /**
80 * struct atmel_smc_cs_conf - SMC CS config as
81 * @setup: NCS/NWE/NRD setup timings (not appl
82 * @pulse: NCS/NWE/NRD pulse timings (not appl
83 * @cycle: NWE/NRD cycle timings (not applicab
84 * @timings: advanced NAND related timings (on
85 * @mode: all kind of config parameters (see t
86 * The mode fields are different on at9
87 */
88 struct atmel_smc_cs_conf {
89 u32 setup;
90 u32 pulse;
91 u32 cycle;
92 u32 timings;
93 u32 mode;
94 };
95
96 void atmel_smc_cs_conf_init(struct atmel_smc_c
97 int atmel_smc_cs_conf_set_timing(struct atmel_
98 unsigned int
99 unsigned int
100 int atmel_smc_cs_conf_set_setup(struct atmel_s
101 unsigned int s
102 int atmel_smc_cs_conf_set_pulse(struct atmel_s
103 unsigned int s
104 int atmel_smc_cs_conf_set_cycle(struct atmel_s
105 unsigned int s
106 void atmel_smc_cs_conf_apply(struct regmap *re
107 const struct atme
108 void atmel_hsmc_cs_conf_apply(struct regmap *r
109 const struct atm
110 int cs, const st
111 void atmel_smc_cs_conf_get(struct regmap *regm
112 struct atmel_smc_cs
113 void atmel_hsmc_cs_conf_get(struct regmap *reg
114 const struct atmel
115 int cs, struct atm
116 const struct atmel_hsmc_reg_layout *
117 atmel_hsmc_get_reg_layout(struct device_node *
118
119 #endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */
120
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