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Linux/sound/soc/pxa/pxa2xx-i2s.c

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Diff markup

Differences between /sound/soc/pxa/pxa2xx-i2s.c (Version linux-3.12.74) and /sound/soc/pxa/pxa2xx-i2s.c (Version linux-5.9.16)


                                                   >>   1 // SPDX-License-Identifier: GPL-2.0-or-later
  1 /*                                                  2 /*
  2  * pxa2xx-i2s.c  --  ALSA Soc Audio Layer           3  * pxa2xx-i2s.c  --  ALSA Soc Audio Layer
  3  *                                                  4  *
  4  * Copyright 2005 Wolfson Microelectronics PLC      5  * Copyright 2005 Wolfson Microelectronics PLC.
  5  * Author: Liam Girdwood                            6  * Author: Liam Girdwood
  6  *         lrg@slimlogic.co.uk                      7  *         lrg@slimlogic.co.uk
  7  *                                             << 
  8  *  This program is free software; you can red << 
  9  *  under  the terms of  the GNU General  Publ << 
 10  *  Free Software Foundation;  either version  << 
 11  *  option) any later version.                 << 
 12  */                                                 8  */
 13                                                     9 
 14 #include <linux/init.h>                            10 #include <linux/init.h>
 15 #include <linux/module.h>                          11 #include <linux/module.h>
 16 #include <linux/device.h>                          12 #include <linux/device.h>
 17 #include <linux/delay.h>                           13 #include <linux/delay.h>
 18 #include <linux/clk.h>                             14 #include <linux/clk.h>
 19 #include <linux/platform_device.h>                 15 #include <linux/platform_device.h>
 20 #include <linux/io.h>                              16 #include <linux/io.h>
 21 #include <sound/core.h>                            17 #include <sound/core.h>
 22 #include <sound/pcm.h>                             18 #include <sound/pcm.h>
 23 #include <sound/initval.h>                         19 #include <sound/initval.h>
 24 #include <sound/soc.h>                             20 #include <sound/soc.h>
 25 #include <sound/pxa2xx-lib.h>                      21 #include <sound/pxa2xx-lib.h>
 26 #include <sound/dmaengine_pcm.h>                   22 #include <sound/dmaengine_pcm.h>
 27                                                    23 
 28 #include <mach/hardware.h>                         24 #include <mach/hardware.h>
 29 #include <mach/audio.h>                            25 #include <mach/audio.h>
 30                                                    26 
 31 #include "pxa2xx-i2s.h"                            27 #include "pxa2xx-i2s.h"
 32                                                    28 
 33 /*                                                 29 /*
 34  * I2S Controller Register and Bit Definitions     30  * I2S Controller Register and Bit Definitions
 35  */                                                31  */
 36 #define SACR0           __REG(0x40400000)  /*      32 #define SACR0           __REG(0x40400000)  /* Global Control Register */
 37 #define SACR1           __REG(0x40400004)  /*      33 #define SACR1           __REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
 38 #define SASR0           __REG(0x4040000C)  /*      34 #define SASR0           __REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
 39 #define SAIMR           __REG(0x40400014)  /*      35 #define SAIMR           __REG(0x40400014)  /* Serial Audio Interrupt Mask Register */
 40 #define SAICR           __REG(0x40400018)  /*      36 #define SAICR           __REG(0x40400018)  /* Serial Audio Interrupt Clear Register */
 41 #define SADIV           __REG(0x40400060)  /*      37 #define SADIV           __REG(0x40400060)  /* Audio Clock Divider Register. */
 42 #define SADR            __REG(0x40400080)  /*      38 #define SADR            __REG(0x40400080)  /* Serial Audio Data Register (TX and RX FIFO access Register). */
 43                                                    39 
 44 #define SACR0_RFTH(x)   ((x) << 12)     /* Rx      40 #define SACR0_RFTH(x)   ((x) << 12)     /* Rx FIFO Interrupt or DMA Trigger Threshold */
 45 #define SACR0_TFTH(x)   ((x) << 8)      /* Tx      41 #define SACR0_TFTH(x)   ((x) << 8)      /* Tx FIFO Interrupt or DMA Trigger Threshold */
 46 #define SACR0_STRF      (1 << 5)        /* FIF     42 #define SACR0_STRF      (1 << 5)        /* FIFO Select for EFWR Special Function */
 47 #define SACR0_EFWR      (1 << 4)        /* Ena     43 #define SACR0_EFWR      (1 << 4)        /* Enable EFWR Function  */
 48 #define SACR0_RST       (1 << 3)        /* FIF     44 #define SACR0_RST       (1 << 3)        /* FIFO, i2s Register Reset */
 49 #define SACR0_BCKD      (1 << 2)        /* Bit !!  45 #define SACR0_BCKD      (1 << 2)        /* Bit Clock Direction */
 50 #define SACR0_ENB       (1 << 0)        /* Ena     46 #define SACR0_ENB       (1 << 0)        /* Enable I2S Link */
 51 #define SACR1_ENLBF     (1 << 5)        /* Ena     47 #define SACR1_ENLBF     (1 << 5)        /* Enable Loopback */
 52 #define SACR1_DRPL      (1 << 4)        /* Dis !!  48 #define SACR1_DRPL      (1 << 4)        /* Disable Replaying Function */
 53 #define SACR1_DREC      (1 << 3)        /* Dis     49 #define SACR1_DREC      (1 << 3)        /* Disable Recording Function */
 54 #define SACR1_AMSL      (1 << 0)        /* Spe     50 #define SACR1_AMSL      (1 << 0)        /* Specify Alternate Mode */
 55                                                    51 
 56 #define SASR0_I2SOFF    (1 << 7)        /* Con     52 #define SASR0_I2SOFF    (1 << 7)        /* Controller Status */
 57 #define SASR0_ROR       (1 << 6)        /* Rx      53 #define SASR0_ROR       (1 << 6)        /* Rx FIFO Overrun */
 58 #define SASR0_TUR       (1 << 5)        /* Tx      54 #define SASR0_TUR       (1 << 5)        /* Tx FIFO Underrun */
 59 #define SASR0_RFS       (1 << 4)        /* Rx      55 #define SASR0_RFS       (1 << 4)        /* Rx FIFO Service Request */
 60 #define SASR0_TFS       (1 << 3)        /* Tx      56 #define SASR0_TFS       (1 << 3)        /* Tx FIFO Service Request */
 61 #define SASR0_BSY       (1 << 2)        /* I2S     57 #define SASR0_BSY       (1 << 2)        /* I2S Busy */
 62 #define SASR0_RNE       (1 << 1)        /* Rx      58 #define SASR0_RNE       (1 << 1)        /* Rx FIFO Not Empty */
 63 #define SASR0_TNF       (1 << 0)        /* Tx  !!  59 #define SASR0_TNF       (1 << 0)        /* Tx FIFO Not Empty */
 64                                                    60 
 65 #define SAICR_ROR       (1 << 6)        /* Cle     61 #define SAICR_ROR       (1 << 6)        /* Clear Rx FIFO Overrun Interrupt */
 66 #define SAICR_TUR       (1 << 5)        /* Cle     62 #define SAICR_TUR       (1 << 5)        /* Clear Tx FIFO Underrun Interrupt */
 67                                                    63 
 68 #define SAIMR_ROR       (1 << 6)        /* Ena     64 #define SAIMR_ROR       (1 << 6)        /* Enable Rx FIFO Overrun Condition Interrupt */
 69 #define SAIMR_TUR       (1 << 5)        /* Ena     65 #define SAIMR_TUR       (1 << 5)        /* Enable Tx FIFO Underrun Condition Interrupt */
 70 #define SAIMR_RFS       (1 << 4)        /* Ena     66 #define SAIMR_RFS       (1 << 4)        /* Enable Rx FIFO Service Interrupt */
 71 #define SAIMR_TFS       (1 << 3)        /* Ena     67 #define SAIMR_TFS       (1 << 3)        /* Enable Tx FIFO Service Interrupt */
 72                                                    68 
 73 struct pxa_i2s_port {                              69 struct pxa_i2s_port {
 74         u32 sadiv;                                 70         u32 sadiv;
 75         u32 sacr0;                                 71         u32 sacr0;
 76         u32 sacr1;                                 72         u32 sacr1;
 77         u32 saimr;                                 73         u32 saimr;
 78         int master;                                74         int master;
 79         u32 fmt;                                   75         u32 fmt;
 80 };                                                 76 };
 81 static struct pxa_i2s_port pxa_i2s;                77 static struct pxa_i2s_port pxa_i2s;
 82 static struct clk *clk_i2s;                        78 static struct clk *clk_i2s;
 83 static int clk_ena = 0;                            79 static int clk_ena = 0;
 84                                                    80 
 85 static unsigned long pxa2xx_i2s_pcm_stereo_out << 
 86 static struct snd_dmaengine_dai_dma_data pxa2x     81 static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_out = {
 87         .addr           = __PREG(SADR),            82         .addr           = __PREG(SADR),
 88         .addr_width     = DMA_SLAVE_BUSWIDTH_4     83         .addr_width     = DMA_SLAVE_BUSWIDTH_4_BYTES,
                                                   >>  84         .chan_name      = "tx",
 89         .maxburst       = 32,                      85         .maxburst       = 32,
 90         .filter_data    = &pxa2xx_i2s_pcm_ster << 
 91 };                                                 86 };
 92                                                    87 
 93 static unsigned long pxa2xx_i2s_pcm_stereo_in_ << 
 94 static struct snd_dmaengine_dai_dma_data pxa2x     88 static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_in = {
 95         .addr           = __PREG(SADR),            89         .addr           = __PREG(SADR),
 96         .addr_width     = DMA_SLAVE_BUSWIDTH_4     90         .addr_width     = DMA_SLAVE_BUSWIDTH_4_BYTES,
                                                   >>  91         .chan_name      = "rx",
 97         .maxburst       = 32,                      92         .maxburst       = 32,
 98         .filter_data    = &pxa2xx_i2s_pcm_ster << 
 99 };                                                 93 };
100                                                    94 
101 static int pxa2xx_i2s_startup(struct snd_pcm_s     95 static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream,
102                               struct snd_soc_d     96                               struct snd_soc_dai *dai)
103 {                                                  97 {
104         struct snd_soc_pcm_runtime *rtd = subs !!  98         struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
105         struct snd_soc_dai *cpu_dai = rtd->cpu !!  99         struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
106                                                   100 
107         if (IS_ERR(clk_i2s))                      101         if (IS_ERR(clk_i2s))
108                 return PTR_ERR(clk_i2s);          102                 return PTR_ERR(clk_i2s);
109                                                   103 
110         if (!cpu_dai->active)                  !! 104         if (!snd_soc_dai_active(cpu_dai))
111                 SACR0 = 0;                        105                 SACR0 = 0;
112                                                   106 
113         return 0;                                 107         return 0;
114 }                                                 108 }
115                                                   109 
116 /* wait for I2S controller to be ready */         110 /* wait for I2S controller to be ready */
117 static int pxa_i2s_wait(void)                     111 static int pxa_i2s_wait(void)
118 {                                                 112 {
119         int i;                                    113         int i;
120                                                   114 
121         /* flush the Rx FIFO */                   115         /* flush the Rx FIFO */
122         for(i = 0; i < 16; i++)                !! 116         for (i = 0; i < 16; i++)
123                 SADR;                             117                 SADR;
124         return 0;                                 118         return 0;
125 }                                                 119 }
126                                                   120 
127 static int pxa2xx_i2s_set_dai_fmt(struct snd_s    121 static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
128                 unsigned int fmt)                 122                 unsigned int fmt)
129 {                                                 123 {
130         /* interface format */                    124         /* interface format */
131         switch (fmt & SND_SOC_DAIFMT_FORMAT_MA    125         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
132         case SND_SOC_DAIFMT_I2S:                  126         case SND_SOC_DAIFMT_I2S:
133                 pxa_i2s.fmt = 0;                  127                 pxa_i2s.fmt = 0;
134                 break;                            128                 break;
135         case SND_SOC_DAIFMT_LEFT_J:               129         case SND_SOC_DAIFMT_LEFT_J:
136                 pxa_i2s.fmt = SACR1_AMSL;         130                 pxa_i2s.fmt = SACR1_AMSL;
137                 break;                            131                 break;
138         }                                         132         }
139                                                   133 
140         switch (fmt & SND_SOC_DAIFMT_MASTER_MA    134         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
141         case SND_SOC_DAIFMT_CBS_CFS:              135         case SND_SOC_DAIFMT_CBS_CFS:
142                 pxa_i2s.master = 1;               136                 pxa_i2s.master = 1;
143                 break;                            137                 break;
144         case SND_SOC_DAIFMT_CBM_CFS:              138         case SND_SOC_DAIFMT_CBM_CFS:
145                 pxa_i2s.master = 0;               139                 pxa_i2s.master = 0;
146                 break;                            140                 break;
147         default:                                  141         default:
148                 break;                            142                 break;
149         }                                         143         }
150         return 0;                                 144         return 0;
151 }                                                 145 }
152                                                   146 
153 static int pxa2xx_i2s_set_dai_sysclk(struct sn    147 static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
154                 int clk_id, unsigned int freq,    148                 int clk_id, unsigned int freq, int dir)
155 {                                                 149 {
156         if (clk_id != PXA2XX_I2S_SYSCLK)          150         if (clk_id != PXA2XX_I2S_SYSCLK)
157                 return -ENODEV;                   151                 return -ENODEV;
158                                                   152 
159         return 0;                                 153         return 0;
160 }                                                 154 }
161                                                   155 
162 static int pxa2xx_i2s_hw_params(struct snd_pcm    156 static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
163                                 struct snd_pcm    157                                 struct snd_pcm_hw_params *params,
164                                 struct snd_soc    158                                 struct snd_soc_dai *dai)
165 {                                                 159 {
166         struct snd_dmaengine_dai_dma_data *dma    160         struct snd_dmaengine_dai_dma_data *dma_data;
167                                                   161 
168         BUG_ON(IS_ERR(clk_i2s));               !! 162         if (WARN_ON(IS_ERR(clk_i2s)))
                                                   >> 163                 return -EINVAL;
169         clk_prepare_enable(clk_i2s);              164         clk_prepare_enable(clk_i2s);
170         clk_ena = 1;                              165         clk_ena = 1;
171         pxa_i2s_wait();                           166         pxa_i2s_wait();
172                                                   167 
173         if (substream->stream == SNDRV_PCM_STR    168         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
174                 dma_data = &pxa2xx_i2s_pcm_ste    169                 dma_data = &pxa2xx_i2s_pcm_stereo_out;
175         else                                      170         else
176                 dma_data = &pxa2xx_i2s_pcm_ste    171                 dma_data = &pxa2xx_i2s_pcm_stereo_in;
177                                                   172 
178         snd_soc_dai_set_dma_data(dai, substrea    173         snd_soc_dai_set_dma_data(dai, substream, dma_data);
179                                                   174 
180         /* is port used by another stream */      175         /* is port used by another stream */
181         if (!(SACR0 & SACR0_ENB)) {               176         if (!(SACR0 & SACR0_ENB)) {
182                 SACR0 = 0;                        177                 SACR0 = 0;
183                 if (pxa_i2s.master)               178                 if (pxa_i2s.master)
184                         SACR0 |= SACR0_BCKD;      179                         SACR0 |= SACR0_BCKD;
185                                                   180 
186                 SACR0 |= SACR0_RFTH(14) | SACR    181                 SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
187                 SACR1 |= pxa_i2s.fmt;             182                 SACR1 |= pxa_i2s.fmt;
188         }                                         183         }
189         if (substream->stream == SNDRV_PCM_STR    184         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
190                 SAIMR |= SAIMR_TFS;               185                 SAIMR |= SAIMR_TFS;
191         else                                      186         else
192                 SAIMR |= SAIMR_RFS;               187                 SAIMR |= SAIMR_RFS;
193                                                   188 
194         switch (params_rate(params)) {            189         switch (params_rate(params)) {
195         case 8000:                                190         case 8000:
196                 SADIV = 0x48;                     191                 SADIV = 0x48;
197                 break;                            192                 break;
198         case 11025:                               193         case 11025:
199                 SADIV = 0x34;                     194                 SADIV = 0x34;
200                 break;                            195                 break;
201         case 16000:                               196         case 16000:
202                 SADIV = 0x24;                     197                 SADIV = 0x24;
203                 break;                            198                 break;
204         case 22050:                               199         case 22050:
205                 SADIV = 0x1a;                     200                 SADIV = 0x1a;
206                 break;                            201                 break;
207         case 44100:                               202         case 44100:
208                 SADIV = 0xd;                      203                 SADIV = 0xd;
209                 break;                            204                 break;
210         case 48000:                               205         case 48000:
211                 SADIV = 0xc;                      206                 SADIV = 0xc;
212                 break;                            207                 break;
213         case 96000: /* not in manual and possi    208         case 96000: /* not in manual and possibly slightly inaccurate */
214                 SADIV = 0x6;                      209                 SADIV = 0x6;
215                 break;                            210                 break;
216         }                                         211         }
217                                                   212 
218         return 0;                                 213         return 0;
219 }                                                 214 }
220                                                   215 
221 static int pxa2xx_i2s_trigger(struct snd_pcm_s    216 static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
222                               struct snd_soc_d    217                               struct snd_soc_dai *dai)
223 {                                                 218 {
224         int ret = 0;                              219         int ret = 0;
225                                                   220 
226         switch (cmd) {                            221         switch (cmd) {
227         case SNDRV_PCM_TRIGGER_START:             222         case SNDRV_PCM_TRIGGER_START:
228                 if (substream->stream == SNDRV    223                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
229                         SACR1 &= ~SACR1_DRPL;     224                         SACR1 &= ~SACR1_DRPL;
230                 else                              225                 else
231                         SACR1 &= ~SACR1_DREC;     226                         SACR1 &= ~SACR1_DREC;
232                 SACR0 |= SACR0_ENB;               227                 SACR0 |= SACR0_ENB;
233                 break;                            228                 break;
234         case SNDRV_PCM_TRIGGER_RESUME:            229         case SNDRV_PCM_TRIGGER_RESUME:
235         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:     230         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
236         case SNDRV_PCM_TRIGGER_STOP:              231         case SNDRV_PCM_TRIGGER_STOP:
237         case SNDRV_PCM_TRIGGER_SUSPEND:           232         case SNDRV_PCM_TRIGGER_SUSPEND:
238         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:        233         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
239                 break;                            234                 break;
240         default:                                  235         default:
241                 ret = -EINVAL;                    236                 ret = -EINVAL;
242         }                                         237         }
243                                                   238 
244         return ret;                               239         return ret;
245 }                                                 240 }
246                                                   241 
247 static void pxa2xx_i2s_shutdown(struct snd_pcm    242 static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream,
248                                 struct snd_soc    243                                 struct snd_soc_dai *dai)
249 {                                                 244 {
250         if (substream->stream == SNDRV_PCM_STR    245         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
251                 SACR1 |= SACR1_DRPL;              246                 SACR1 |= SACR1_DRPL;
252                 SAIMR &= ~SAIMR_TFS;              247                 SAIMR &= ~SAIMR_TFS;
253         } else {                                  248         } else {
254                 SACR1 |= SACR1_DREC;              249                 SACR1 |= SACR1_DREC;
255                 SAIMR &= ~SAIMR_RFS;              250                 SAIMR &= ~SAIMR_RFS;
256         }                                         251         }
257                                                   252 
258         if ((SACR1 & (SACR1_DREC | SACR1_DRPL)    253         if ((SACR1 & (SACR1_DREC | SACR1_DRPL)) == (SACR1_DREC | SACR1_DRPL)) {
259                 SACR0 &= ~SACR0_ENB;              254                 SACR0 &= ~SACR0_ENB;
260                 pxa_i2s_wait();                   255                 pxa_i2s_wait();
261                 if (clk_ena) {                    256                 if (clk_ena) {
262                         clk_disable_unprepare(    257                         clk_disable_unprepare(clk_i2s);
263                         clk_ena = 0;              258                         clk_ena = 0;
264                 }                                 259                 }
265         }                                         260         }
266 }                                                 261 }
267                                                   262 
268 #ifdef CONFIG_PM                                  263 #ifdef CONFIG_PM
269 static int pxa2xx_i2s_suspend(struct snd_soc_d !! 264 static int pxa2xx_soc_pcm_suspend(struct snd_soc_component *component)
270 {                                                 265 {
271         /* store registers */                     266         /* store registers */
272         pxa_i2s.sacr0 = SACR0;                    267         pxa_i2s.sacr0 = SACR0;
273         pxa_i2s.sacr1 = SACR1;                    268         pxa_i2s.sacr1 = SACR1;
274         pxa_i2s.saimr = SAIMR;                    269         pxa_i2s.saimr = SAIMR;
275         pxa_i2s.sadiv = SADIV;                    270         pxa_i2s.sadiv = SADIV;
276                                                   271 
277         /* deactivate link */                     272         /* deactivate link */
278         SACR0 &= ~SACR0_ENB;                      273         SACR0 &= ~SACR0_ENB;
279         pxa_i2s_wait();                           274         pxa_i2s_wait();
280         return 0;                                 275         return 0;
281 }                                                 276 }
282                                                   277 
283 static int pxa2xx_i2s_resume(struct snd_soc_da !! 278 static int pxa2xx_soc_pcm_resume(struct snd_soc_component *component)
284 {                                                 279 {
285         pxa_i2s_wait();                           280         pxa_i2s_wait();
286                                                   281 
287         SACR0 = pxa_i2s.sacr0 & ~SACR0_ENB;       282         SACR0 = pxa_i2s.sacr0 & ~SACR0_ENB;
288         SACR1 = pxa_i2s.sacr1;                    283         SACR1 = pxa_i2s.sacr1;
289         SAIMR = pxa_i2s.saimr;                    284         SAIMR = pxa_i2s.saimr;
290         SADIV = pxa_i2s.sadiv;                    285         SADIV = pxa_i2s.sadiv;
291                                                   286 
292         SACR0 = pxa_i2s.sacr0;                    287         SACR0 = pxa_i2s.sacr0;
293                                                   288 
294         return 0;                                 289         return 0;
295 }                                                 290 }
296                                                   291 
297 #else                                             292 #else
298 #define pxa2xx_i2s_suspend      NULL           !! 293 #define pxa2xx_soc_pcm_suspend  NULL
299 #define pxa2xx_i2s_resume       NULL           !! 294 #define pxa2xx_soc_pcm_resume   NULL
300 #endif                                            295 #endif
301                                                   296 
302 static int pxa2xx_i2s_probe(struct snd_soc_dai    297 static int pxa2xx_i2s_probe(struct snd_soc_dai *dai)
303 {                                                 298 {
304         clk_i2s = clk_get(dai->dev, "I2SCLK");    299         clk_i2s = clk_get(dai->dev, "I2SCLK");
305         if (IS_ERR(clk_i2s))                      300         if (IS_ERR(clk_i2s))
306                 return PTR_ERR(clk_i2s);          301                 return PTR_ERR(clk_i2s);
307                                                   302 
308         /*                                        303         /*
309          * PXA Developer's Manual:                304          * PXA Developer's Manual:
310          * If SACR0[ENB] is toggled in the mid    305          * If SACR0[ENB] is toggled in the middle of a normal operation,
311          * the SACR0[RST] bit must also be set    306          * the SACR0[RST] bit must also be set and cleared to reset all
312          * I2S controller registers.              307          * I2S controller registers.
313          */                                       308          */
314         SACR0 = SACR0_RST;                        309         SACR0 = SACR0_RST;
315         SACR0 = 0;                                310         SACR0 = 0;
316         /* Make sure RPL and REC are disabled     311         /* Make sure RPL and REC are disabled */
317         SACR1 = SACR1_DRPL | SACR1_DREC;          312         SACR1 = SACR1_DRPL | SACR1_DREC;
318         /* Along with FIFO servicing */           313         /* Along with FIFO servicing */
319         SAIMR &= ~(SAIMR_RFS | SAIMR_TFS);        314         SAIMR &= ~(SAIMR_RFS | SAIMR_TFS);
320                                                   315 
                                                   >> 316         snd_soc_dai_init_dma_data(dai, &pxa2xx_i2s_pcm_stereo_out,
                                                   >> 317                 &pxa2xx_i2s_pcm_stereo_in);
                                                   >> 318 
321         return 0;                                 319         return 0;
322 }                                                 320 }
323                                                   321 
324 static int  pxa2xx_i2s_remove(struct snd_soc_d    322 static int  pxa2xx_i2s_remove(struct snd_soc_dai *dai)
325 {                                                 323 {
326         clk_put(clk_i2s);                         324         clk_put(clk_i2s);
327         clk_i2s = ERR_PTR(-ENOENT);               325         clk_i2s = ERR_PTR(-ENOENT);
328         return 0;                                 326         return 0;
329 }                                                 327 }
330                                                   328 
331 #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000     329 #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
332                 SNDRV_PCM_RATE_16000 | SNDRV_P    330                 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
333                 SNDRV_PCM_RATE_48000 | SNDRV_P    331                 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
334                                                   332 
335 static const struct snd_soc_dai_ops pxa_i2s_da    333 static const struct snd_soc_dai_ops pxa_i2s_dai_ops = {
336         .startup        = pxa2xx_i2s_startup,     334         .startup        = pxa2xx_i2s_startup,
337         .shutdown       = pxa2xx_i2s_shutdown,    335         .shutdown       = pxa2xx_i2s_shutdown,
338         .trigger        = pxa2xx_i2s_trigger,     336         .trigger        = pxa2xx_i2s_trigger,
339         .hw_params      = pxa2xx_i2s_hw_params    337         .hw_params      = pxa2xx_i2s_hw_params,
340         .set_fmt        = pxa2xx_i2s_set_dai_f    338         .set_fmt        = pxa2xx_i2s_set_dai_fmt,
341         .set_sysclk     = pxa2xx_i2s_set_dai_s    339         .set_sysclk     = pxa2xx_i2s_set_dai_sysclk,
342 };                                                340 };
343                                                   341 
344 static struct snd_soc_dai_driver pxa_i2s_dai =    342 static struct snd_soc_dai_driver pxa_i2s_dai = {
345         .probe = pxa2xx_i2s_probe,                343         .probe = pxa2xx_i2s_probe,
346         .remove = pxa2xx_i2s_remove,              344         .remove = pxa2xx_i2s_remove,
347         .suspend = pxa2xx_i2s_suspend,         << 
348         .resume = pxa2xx_i2s_resume,           << 
349         .playback = {                             345         .playback = {
350                 .channels_min = 2,                346                 .channels_min = 2,
351                 .channels_max = 2,                347                 .channels_max = 2,
352                 .rates = PXA2XX_I2S_RATES,        348                 .rates = PXA2XX_I2S_RATES,
353                 .formats = SNDRV_PCM_FMTBIT_S1    349                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
354         .capture = {                              350         .capture = {
355                 .channels_min = 2,                351                 .channels_min = 2,
356                 .channels_max = 2,                352                 .channels_max = 2,
357                 .rates = PXA2XX_I2S_RATES,        353                 .rates = PXA2XX_I2S_RATES,
358                 .formats = SNDRV_PCM_FMTBIT_S1    354                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
359         .ops = &pxa_i2s_dai_ops,                  355         .ops = &pxa_i2s_dai_ops,
360         .symmetric_rates = 1,                     356         .symmetric_rates = 1,
361 };                                                357 };
362                                                   358 
363 static const struct snd_soc_component_driver p    359 static const struct snd_soc_component_driver pxa_i2s_component = {
364         .name           = "pxa-i2s",              360         .name           = "pxa-i2s",
                                                   >> 361         .pcm_construct  = pxa2xx_soc_pcm_new,
                                                   >> 362         .pcm_destruct   = pxa2xx_soc_pcm_free,
                                                   >> 363         .open           = pxa2xx_soc_pcm_open,
                                                   >> 364         .close          = pxa2xx_soc_pcm_close,
                                                   >> 365         .hw_params      = pxa2xx_soc_pcm_hw_params,
                                                   >> 366         .hw_free        = pxa2xx_soc_pcm_hw_free,
                                                   >> 367         .prepare        = pxa2xx_soc_pcm_prepare,
                                                   >> 368         .trigger        = pxa2xx_soc_pcm_trigger,
                                                   >> 369         .pointer        = pxa2xx_soc_pcm_pointer,
                                                   >> 370         .mmap           = pxa2xx_soc_pcm_mmap,
                                                   >> 371         .suspend        = pxa2xx_soc_pcm_suspend,
                                                   >> 372         .resume         = pxa2xx_soc_pcm_resume,
365 };                                                373 };
366                                                   374 
367 static int pxa2xx_i2s_drv_probe(struct platfor    375 static int pxa2xx_i2s_drv_probe(struct platform_device *pdev)
368 {                                                 376 {
369         return snd_soc_register_component(&pde !! 377         return devm_snd_soc_register_component(&pdev->dev, &pxa_i2s_component,
370                                           &pxa !! 378                                                &pxa_i2s_dai, 1);
371 }                                              << 
372                                                << 
373 static int pxa2xx_i2s_drv_remove(struct platfo << 
374 {                                              << 
375         snd_soc_unregister_component(&pdev->de << 
376         return 0;                              << 
377 }                                                 379 }
378                                                   380 
379 static struct platform_driver pxa2xx_i2s_drive    381 static struct platform_driver pxa2xx_i2s_driver = {
380         .probe = pxa2xx_i2s_drv_probe,            382         .probe = pxa2xx_i2s_drv_probe,
381         .remove = pxa2xx_i2s_drv_remove,       << 
382                                                   383 
383         .driver = {                               384         .driver = {
384                 .name = "pxa2xx-i2s",             385                 .name = "pxa2xx-i2s",
385                 .owner = THIS_MODULE,          << 
386         },                                        386         },
387 };                                                387 };
388                                                   388 
389 static int __init pxa2xx_i2s_init(void)           389 static int __init pxa2xx_i2s_init(void)
390 {                                                 390 {
391         clk_i2s = ERR_PTR(-ENOENT);               391         clk_i2s = ERR_PTR(-ENOENT);
392         return platform_driver_register(&pxa2x    392         return platform_driver_register(&pxa2xx_i2s_driver);
393 }                                                 393 }
394                                                   394 
395 static void __exit pxa2xx_i2s_exit(void)          395 static void __exit pxa2xx_i2s_exit(void)
396 {                                                 396 {
397         platform_driver_unregister(&pxa2xx_i2s    397         platform_driver_unregister(&pxa2xx_i2s_driver);
398 }                                                 398 }
399                                                   399 
400 module_init(pxa2xx_i2s_init);                     400 module_init(pxa2xx_i2s_init);
401 module_exit(pxa2xx_i2s_exit);                     401 module_exit(pxa2xx_i2s_exit);
402                                                   402 
403 /* Module information */                          403 /* Module information */
404 MODULE_AUTHOR("Liam Girdwood, lrg@slimlogic.co    404 MODULE_AUTHOR("Liam Girdwood, lrg@slimlogic.co.uk");
405 MODULE_DESCRIPTION("pxa2xx I2S SoC Interface")    405 MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
406 MODULE_LICENSE("GPL");                            406 MODULE_LICENSE("GPL");
407 MODULE_ALIAS("platform:pxa2xx-i2s");              407 MODULE_ALIAS("platform:pxa2xx-i2s");
408                                                   408 

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