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Linux/arch/alpha/kernel/core_tsunami.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 /*
  3  *      linux/arch/alpha/kernel/core_tsunami.c
  4  *
  5  * Based on code written by David A. Rusling (david.rusling@reo.mts.dec.com).
  6  *
  7  * Code common to all TSUNAMI core logic chips.
  8  */
  9 
 10 #define __EXTERN_INLINE inline
 11 #include <asm/io.h>
 12 #include <asm/core_tsunami.h>
 13 #undef __EXTERN_INLINE
 14 
 15 #include <linux/module.h>
 16 #include <linux/types.h>
 17 #include <linux/pci.h>
 18 #include <linux/sched.h>
 19 #include <linux/init.h>
 20 #include <linux/bootmem.h>
 21 
 22 #include <asm/ptrace.h>
 23 #include <asm/smp.h>
 24 #include <asm/vga.h>
 25 
 26 #include "proto.h"
 27 #include "pci_impl.h"
 28 
 29 /* Save Tsunami configuration data as the console had it set up.  */
 30 
 31 struct 
 32 {
 33         unsigned long wsba[4];
 34         unsigned long wsm[4];
 35         unsigned long tba[4];
 36 } saved_config[2] __attribute__((common));
 37 
 38 /*
 39  * NOTE: Herein lie back-to-back mb instructions.  They are magic. 
 40  * One plausible explanation is that the I/O controller does not properly
 41  * handle the system transaction.  Another involves timing.  Ho hum.
 42  */
 43 
 44 /*
 45  * BIOS32-style PCI interface:
 46  */
 47 
 48 #define DEBUG_CONFIG 0
 49 
 50 #if DEBUG_CONFIG
 51 # define DBG_CFG(args)  printk args
 52 #else
 53 # define DBG_CFG(args)
 54 #endif
 55 
 56 
 57 /*
 58  * Given a bus, device, and function number, compute resulting
 59  * configuration space address
 60  * accordingly.  It is therefore not safe to have concurrent
 61  * invocations to configuration space access routines, but there
 62  * really shouldn't be any need for this.
 63  *
 64  * Note that all config space accesses use Type 1 address format.
 65  *
 66  * Note also that type 1 is determined by non-zero bus number.
 67  *
 68  * Type 1:
 69  *
 70  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
 71  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
 72  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 73  * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
 74  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 75  *
 76  *      31:24   reserved
 77  *      23:16   bus number (8 bits = 128 possible buses)
 78  *      15:11   Device number (5 bits)
 79  *      10:8    function number
 80  *       7:2    register number
 81  *  
 82  * Notes:
 83  *      The function number selects which function of a multi-function device 
 84  *      (e.g., SCSI and Ethernet).
 85  * 
 86  *      The register selects a DWORD (32 bit) register offset.  Hence it
 87  *      doesn't get shifted by 2 bits as we want to "drop" the bottom two
 88  *      bits.
 89  */
 90 
 91 static int
 92 mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
 93              unsigned long *pci_addr, unsigned char *type1)
 94 {
 95         struct pci_controller *hose = pbus->sysdata;
 96         unsigned long addr;
 97         u8 bus = pbus->number;
 98 
 99         DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, "
100                  "pci_addr=0x%p, type1=0x%p)\n",
101                  bus, device_fn, where, pci_addr, type1));
102         
103         if (!pbus->parent) /* No parent means peer PCI bus. */
104                 bus = 0;
105         *type1 = (bus != 0);
106 
107         addr = (bus << 16) | (device_fn << 8) | where;
108         addr |= hose->config_space_base;
109                 
110         *pci_addr = addr;
111         DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
112         return 0;
113 }
114 
115 static int 
116 tsunami_read_config(struct pci_bus *bus, unsigned int devfn, int where,
117                     int size, u32 *value)
118 {
119         unsigned long addr;
120         unsigned char type1;
121 
122         if (mk_conf_addr(bus, devfn, where, &addr, &type1))
123                 return PCIBIOS_DEVICE_NOT_FOUND;
124 
125         switch (size) {
126         case 1:
127                 *value = __kernel_ldbu(*(vucp)addr);
128                 break;
129         case 2:
130                 *value = __kernel_ldwu(*(vusp)addr);
131                 break;
132         case 4:
133                 *value = *(vuip)addr;
134                 break;
135         }
136 
137         return PCIBIOS_SUCCESSFUL;
138 }
139 
140 static int 
141 tsunami_write_config(struct pci_bus *bus, unsigned int devfn, int where,
142                      int size, u32 value)
143 {
144         unsigned long addr;
145         unsigned char type1;
146 
147         if (mk_conf_addr(bus, devfn, where, &addr, &type1))
148                 return PCIBIOS_DEVICE_NOT_FOUND;
149 
150         switch (size) {
151         case 1:
152                 __kernel_stb(value, *(vucp)addr);
153                 mb();
154                 __kernel_ldbu(*(vucp)addr);
155                 break;
156         case 2:
157                 __kernel_stw(value, *(vusp)addr);
158                 mb();
159                 __kernel_ldwu(*(vusp)addr);
160                 break;
161         case 4:
162                 *(vuip)addr = value;
163                 mb();
164                 *(vuip)addr;
165                 break;
166         }
167 
168         return PCIBIOS_SUCCESSFUL;
169 }
170 
171 struct pci_ops tsunami_pci_ops = 
172 {
173         .read =         tsunami_read_config,
174         .write =        tsunami_write_config,
175 };
176 
177 void
178 tsunami_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
179 {
180         tsunami_pchip *pchip = hose->index ? TSUNAMI_pchip1 : TSUNAMI_pchip0;
181         volatile unsigned long *csr;
182         unsigned long value;
183 
184         /* We can invalidate up to 8 tlb entries in a go.  The flush
185            matches against <31:16> in the pci address.  */
186         csr = &pchip->tlbia.csr;
187         if (((start ^ end) & 0xffff0000) == 0)
188                 csr = &pchip->tlbiv.csr;
189 
190         /* For TBIA, it doesn't matter what value we write.  For TBI, 
191            it's the shifted tag bits.  */
192         value = (start & 0xffff0000) >> 12;
193 
194         *csr = value;
195         mb();
196         *csr;
197 }
198 
199 #ifdef NXM_MACHINE_CHECKS_ON_TSUNAMI
200 static long __init
201 tsunami_probe_read(volatile unsigned long *vaddr)
202 {
203         long dont_care, probe_result;
204         int cpu = smp_processor_id();
205         int s = swpipl(IPL_MCHECK - 1);
206 
207         mcheck_taken(cpu) = 0;
208         mcheck_expected(cpu) = 1;
209         mb();
210         dont_care = *vaddr;
211         draina();
212         mcheck_expected(cpu) = 0;
213         probe_result = !mcheck_taken(cpu);
214         mcheck_taken(cpu) = 0;
215         setipl(s);
216 
217         printk("dont_care == 0x%lx\n", dont_care);
218 
219         return probe_result;
220 }
221 
222 static long __init
223 tsunami_probe_write(volatile unsigned long *vaddr)
224 {
225         long true_contents, probe_result = 1;
226 
227         TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */
228         true_contents = *vaddr;
229         *vaddr = 0;
230         draina();
231         if (TSUNAMI_cchip->misc.csr & (1L << 28)) {
232                 int source = (TSUNAMI_cchip->misc.csr >> 29) & 7;
233                 TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */
234                 probe_result = 0;
235                 printk("tsunami_probe_write: unit %d at 0x%016lx\n", source,
236                        (unsigned long)vaddr);
237         }
238         if (probe_result)
239                 *vaddr = true_contents;
240         return probe_result;
241 }
242 #else
243 #define tsunami_probe_read(ADDR) 1
244 #endif /* NXM_MACHINE_CHECKS_ON_TSUNAMI */
245 
246 static void __init
247 tsunami_init_one_pchip(tsunami_pchip *pchip, int index)
248 {
249         struct pci_controller *hose;
250 
251         if (tsunami_probe_read(&pchip->pctl.csr) == 0)
252                 return;
253 
254         hose = alloc_pci_controller();
255         if (index == 0)
256                 pci_isa_hose = hose;
257         hose->io_space = alloc_resource();
258         hose->mem_space = alloc_resource();
259 
260         /* This is for userland consumption.  For some reason, the 40-bit
261            PIO bias that we use in the kernel through KSEG didn't work for
262            the page table based user mappings.  So make sure we get the
263            43-bit PIO bias.  */
264         hose->sparse_mem_base = 0;
265         hose->sparse_io_base = 0;
266         hose->dense_mem_base
267           = (TSUNAMI_MEM(index) & 0xffffffffffL) | 0x80000000000L;
268         hose->dense_io_base
269           = (TSUNAMI_IO(index) & 0xffffffffffL) | 0x80000000000L;
270 
271         hose->config_space_base = TSUNAMI_CONF(index);
272         hose->index = index;
273 
274         hose->io_space->start = TSUNAMI_IO(index) - TSUNAMI_IO_BIAS;
275         hose->io_space->end = hose->io_space->start + TSUNAMI_IO_SPACE - 1;
276         hose->io_space->name = pci_io_names[index];
277         hose->io_space->flags = IORESOURCE_IO;
278 
279         hose->mem_space->start = TSUNAMI_MEM(index) - TSUNAMI_MEM_BIAS;
280         hose->mem_space->end = hose->mem_space->start + 0xffffffff;
281         hose->mem_space->name = pci_mem_names[index];
282         hose->mem_space->flags = IORESOURCE_MEM;
283 
284         if (request_resource(&ioport_resource, hose->io_space) < 0)
285                 printk(KERN_ERR "Failed to request IO on hose %d\n", index);
286         if (request_resource(&iomem_resource, hose->mem_space) < 0)
287                 printk(KERN_ERR "Failed to request MEM on hose %d\n", index);
288 
289         /*
290          * Save the existing PCI window translations.  SRM will 
291          * need them when we go to reboot.
292          */
293 
294         saved_config[index].wsba[0] = pchip->wsba[0].csr;
295         saved_config[index].wsm[0] = pchip->wsm[0].csr;
296         saved_config[index].tba[0] = pchip->tba[0].csr;
297 
298         saved_config[index].wsba[1] = pchip->wsba[1].csr;
299         saved_config[index].wsm[1] = pchip->wsm[1].csr;
300         saved_config[index].tba[1] = pchip->tba[1].csr;
301 
302         saved_config[index].wsba[2] = pchip->wsba[2].csr;
303         saved_config[index].wsm[2] = pchip->wsm[2].csr;
304         saved_config[index].tba[2] = pchip->tba[2].csr;
305 
306         saved_config[index].wsba[3] = pchip->wsba[3].csr;
307         saved_config[index].wsm[3] = pchip->wsm[3].csr;
308         saved_config[index].tba[3] = pchip->tba[3].csr;
309 
310         /*
311          * Set up the PCI to main memory translation windows.
312          *
313          * Note: Window 3 is scatter-gather only
314          * 
315          * Window 0 is scatter-gather 8MB at 8MB (for isa)
316          * Window 1 is scatter-gather (up to) 1GB at 1GB
317          * Window 2 is direct access 2GB at 2GB
318          *
319          * NOTE: we need the align_entry settings for Acer devices on ES40,
320          * specifically floppy and IDE when memory is larger than 2GB.
321          */
322         hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0);
323         /* Initially set for 4 PTEs, but will be overridden to 64K for ISA. */
324         hose->sg_isa->align_entry = 4;
325 
326         hose->sg_pci = iommu_arena_new(hose, 0x40000000,
327                                        size_for_memory(0x40000000), 0);
328         hose->sg_pci->align_entry = 4; /* Tsunami caches 4 PTEs at a time */
329 
330         __direct_map_base = 0x80000000;
331         __direct_map_size = 0x80000000;
332 
333         pchip->wsba[0].csr = hose->sg_isa->dma_base | 3;
334         pchip->wsm[0].csr  = (hose->sg_isa->size - 1) & 0xfff00000;
335         pchip->tba[0].csr  = virt_to_phys(hose->sg_isa->ptes);
336 
337         pchip->wsba[1].csr = hose->sg_pci->dma_base | 3;
338         pchip->wsm[1].csr  = (hose->sg_pci->size - 1) & 0xfff00000;
339         pchip->tba[1].csr  = virt_to_phys(hose->sg_pci->ptes);
340 
341         pchip->wsba[2].csr = 0x80000000 | 1;
342         pchip->wsm[2].csr  = (0x80000000 - 1) & 0xfff00000;
343         pchip->tba[2].csr  = 0;
344 
345         pchip->wsba[3].csr = 0;
346 
347         /* Enable the Monster Window to make DAC pci64 possible. */
348         pchip->pctl.csr |= pctl_m_mwin;
349 
350         tsunami_pci_tbi(hose, 0, -1);
351 }
352 
353 
354 void __iomem *
355 tsunami_ioportmap(unsigned long addr)
356 {
357         FIXUP_IOADDR_VGA(addr);
358         return (void __iomem *)(addr + TSUNAMI_IO_BIAS);
359 }
360 
361 void __iomem *
362 tsunami_ioremap(unsigned long addr, unsigned long size)
363 {
364         FIXUP_MEMADDR_VGA(addr);
365         return (void __iomem *)(addr + TSUNAMI_MEM_BIAS);
366 }
367 
368 #ifndef CONFIG_ALPHA_GENERIC
369 EXPORT_SYMBOL(tsunami_ioportmap);
370 EXPORT_SYMBOL(tsunami_ioremap);
371 #endif
372 
373 void __init
374 tsunami_init_arch(void)
375 {
376 #ifdef NXM_MACHINE_CHECKS_ON_TSUNAMI
377         unsigned long tmp;
378         
379         /* Ho hum.. init_arch is called before init_IRQ, but we need to be
380            able to handle machine checks.  So install the handler now.  */
381         wrent(entInt, 0);
382 
383         /* NXMs just don't matter to Tsunami--unless they make it
384            choke completely. */
385         tmp = (unsigned long)(TSUNAMI_cchip - 1);
386         printk("%s: probing bogus address:  0x%016lx\n", __func__, bogus_addr);
387         printk("\tprobe %s\n",
388                tsunami_probe_write((unsigned long *)bogus_addr)
389                ? "succeeded" : "failed");
390 #endif /* NXM_MACHINE_CHECKS_ON_TSUNAMI */
391 
392 #if 0
393         printk("%s: CChip registers:\n", __func__);
394         printk("%s: CSR_CSC 0x%lx\n", __func__, TSUNAMI_cchip->csc.csr);
395         printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr);
396         printk("%s: CSR_MISC 0x%lx\n", __func__, TSUNAMI_cchip->misc.csr);
397         printk("%s: CSR_DIM0 0x%lx\n", __func__, TSUNAMI_cchip->dim0.csr);
398         printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr);
399         printk("%s: CSR_DIR0 0x%lx\n", __func__, TSUNAMI_cchip->dir0.csr);
400         printk("%s: CSR_DIR1 0x%lx\n", __func__, TSUNAMI_cchip->dir1.csr);
401         printk("%s: CSR_DRIR 0x%lx\n", __func__, TSUNAMI_cchip->drir.csr);
402 
403         printk("%s: DChip registers:\n");
404         printk("%s: CSR_DSC 0x%lx\n", __func__, TSUNAMI_dchip->dsc.csr);
405         printk("%s: CSR_STR 0x%lx\n", __func__, TSUNAMI_dchip->str.csr);
406         printk("%s: CSR_DREV 0x%lx\n", __func__, TSUNAMI_dchip->drev.csr);
407 #endif
408         /* With multiple PCI busses, we play with I/O as physical addrs.  */
409         ioport_resource.end = ~0UL;
410 
411         /* Find how many hoses we have, and initialize them.  TSUNAMI
412            and TYPHOON can have 2, but might only have 1 (DS10).  */
413 
414         tsunami_init_one_pchip(TSUNAMI_pchip0, 0);
415         if (TSUNAMI_cchip->csc.csr & 1L<<14)
416                 tsunami_init_one_pchip(TSUNAMI_pchip1, 1);
417 
418         /* Check for graphic console location (if any).  */
419         find_console_vga_hose();
420 }
421 
422 static void
423 tsunami_kill_one_pchip(tsunami_pchip *pchip, int index)
424 {
425         pchip->wsba[0].csr = saved_config[index].wsba[0];
426         pchip->wsm[0].csr = saved_config[index].wsm[0];
427         pchip->tba[0].csr = saved_config[index].tba[0];
428 
429         pchip->wsba[1].csr = saved_config[index].wsba[1];
430         pchip->wsm[1].csr = saved_config[index].wsm[1];
431         pchip->tba[1].csr = saved_config[index].tba[1];
432 
433         pchip->wsba[2].csr = saved_config[index].wsba[2];
434         pchip->wsm[2].csr = saved_config[index].wsm[2];
435         pchip->tba[2].csr = saved_config[index].tba[2];
436 
437         pchip->wsba[3].csr = saved_config[index].wsba[3];
438         pchip->wsm[3].csr = saved_config[index].wsm[3];
439         pchip->tba[3].csr = saved_config[index].tba[3];
440 }
441 
442 void
443 tsunami_kill_arch(int mode)
444 {
445         tsunami_kill_one_pchip(TSUNAMI_pchip0, 0);
446         if (TSUNAMI_cchip->csc.csr & 1L<<14)
447                 tsunami_kill_one_pchip(TSUNAMI_pchip1, 1);
448 }
449 
450 static inline void
451 tsunami_pci_clr_err_1(tsunami_pchip *pchip)
452 {
453         pchip->perror.csr;
454         pchip->perror.csr = 0x040;
455         mb();
456         pchip->perror.csr;
457 }
458 
459 static inline void
460 tsunami_pci_clr_err(void)
461 {
462         tsunami_pci_clr_err_1(TSUNAMI_pchip0);
463 
464         /* TSUNAMI and TYPHOON can have 2, but might only have 1 (DS10) */
465         if (TSUNAMI_cchip->csc.csr & 1L<<14)
466                 tsunami_pci_clr_err_1(TSUNAMI_pchip1);
467 }
468 
469 void
470 tsunami_machine_check(unsigned long vector, unsigned long la_ptr)
471 {
472         /* Clear error before any reporting.  */
473         mb();
474         mb();  /* magic */
475         draina();
476         tsunami_pci_clr_err();
477         wrmces(0x7);
478         mb();
479 
480         process_mcheck_info(vector, la_ptr, "TSUNAMI",
481                             mcheck_expected(smp_processor_id()));
482 }
483 

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