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Linux/arch/alpha/kernel/sys_eiger.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 /*
  3  *      linux/arch/alpha/kernel/sys_eiger.c
  4  *
  5  *      Copyright (C) 1995 David A Rusling
  6  *      Copyright (C) 1996, 1999 Jay A Estabrook
  7  *      Copyright (C) 1998, 1999 Richard Henderson
  8  *      Copyright (C) 1999 Iain Grant
  9  *
 10  * Code supporting the EIGER (EV6+TSUNAMI).
 11  */
 12 
 13 #include <linux/kernel.h>
 14 #include <linux/types.h>
 15 #include <linux/mm.h>
 16 #include <linux/sched.h>
 17 #include <linux/pci.h>
 18 #include <linux/init.h>
 19 #include <linux/bitops.h>
 20 
 21 #include <asm/ptrace.h>
 22 #include <asm/dma.h>
 23 #include <asm/irq.h>
 24 #include <asm/mmu_context.h>
 25 #include <asm/io.h>
 26 #include <asm/pgtable.h>
 27 #include <asm/core_tsunami.h>
 28 #include <asm/hwrpb.h>
 29 #include <asm/tlbflush.h>
 30 
 31 #include "proto.h"
 32 #include "irq_impl.h"
 33 #include "pci_impl.h"
 34 #include "machvec_impl.h"
 35 
 36 
 37 /* Note that this interrupt code is identical to TAKARA.  */
 38 
 39 /* Note mask bit is true for DISABLED irqs.  */
 40 static unsigned long cached_irq_mask[2] = { -1, -1 };
 41 
 42 static inline void
 43 eiger_update_irq_hw(unsigned long irq, unsigned long mask)
 44 {
 45         int regaddr;
 46 
 47         mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30));
 48         regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c);
 49         outl(mask & 0xffff0000UL, regaddr);
 50 }
 51 
 52 static inline void
 53 eiger_enable_irq(struct irq_data *d)
 54 {
 55         unsigned int irq = d->irq;
 56         unsigned long mask;
 57         mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
 58         eiger_update_irq_hw(irq, mask);
 59 }
 60 
 61 static void
 62 eiger_disable_irq(struct irq_data *d)
 63 {
 64         unsigned int irq = d->irq;
 65         unsigned long mask;
 66         mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
 67         eiger_update_irq_hw(irq, mask);
 68 }
 69 
 70 static struct irq_chip eiger_irq_type = {
 71         .name           = "EIGER",
 72         .irq_unmask     = eiger_enable_irq,
 73         .irq_mask       = eiger_disable_irq,
 74         .irq_mask_ack   = eiger_disable_irq,
 75 };
 76 
 77 static void
 78 eiger_device_interrupt(unsigned long vector)
 79 {
 80         unsigned intstatus;
 81 
 82         /*
 83          * The PALcode will have passed us vectors 0x800 or 0x810,
 84          * which are fairly arbitrary values and serve only to tell
 85          * us whether an interrupt has come in on IRQ0 or IRQ1. If
 86          * it's IRQ1 it's a PCI interrupt; if it's IRQ0, it's
 87          * probably ISA, but PCI interrupts can come through IRQ0
 88          * as well if the interrupt controller isn't in accelerated
 89          * mode.
 90          *
 91          * OTOH, the accelerator thing doesn't seem to be working
 92          * overly well, so what we'll do instead is try directly
 93          * examining the Master Interrupt Register to see if it's a
 94          * PCI interrupt, and if _not_ then we'll pass it on to the
 95          * ISA handler.
 96          */
 97 
 98         intstatus = inw(0x500) & 15;
 99         if (intstatus) {
100                 /*
101                  * This is a PCI interrupt. Check each bit and
102                  * despatch an interrupt if it's set.
103                  */
104 
105                 if (intstatus & 8) handle_irq(16+3);
106                 if (intstatus & 4) handle_irq(16+2);
107                 if (intstatus & 2) handle_irq(16+1);
108                 if (intstatus & 1) handle_irq(16+0);
109         } else {
110                 isa_device_interrupt(vector);
111         }
112 }
113 
114 static void
115 eiger_srm_device_interrupt(unsigned long vector)
116 {
117         int irq = (vector - 0x800) >> 4;
118         handle_irq(irq);
119 }
120 
121 static void __init
122 eiger_init_irq(void)
123 {
124         long i;
125 
126         outb(0, DMA1_RESET_REG);
127         outb(0, DMA2_RESET_REG);
128         outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
129         outb(0, DMA2_MASK_REG);
130 
131         if (alpha_using_srm)
132                 alpha_mv.device_interrupt = eiger_srm_device_interrupt;
133 
134         for (i = 16; i < 128; i += 16)
135                 eiger_update_irq_hw(i, -1);
136 
137         init_i8259a_irqs();
138 
139         for (i = 16; i < 128; ++i) {
140                 irq_set_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
141                 irq_set_status_flags(i, IRQ_LEVEL);
142         }
143 }
144 
145 static int
146 eiger_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
147 {
148         u8 irq_orig;
149 
150         /* The SRM console has already calculated out the IRQ value's for
151            option cards. As this works lets just read in the value already
152            set and change it to a useable value by Linux.
153 
154            All the IRQ values generated by the console are greater than 90,
155            so we subtract 80 because it is (90 - allocated ISA IRQ's).  */
156 
157         pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq_orig);
158 
159         return irq_orig - 0x80;
160 }
161 
162 static u8
163 eiger_swizzle(struct pci_dev *dev, u8 *pinp)
164 {
165         struct pci_controller *hose = dev->sysdata;
166         int slot, pin = *pinp;
167         int bridge_count = 0;
168 
169         /* Find the number of backplane bridges.  */
170         int backplane = inw(0x502) & 0x0f;
171 
172         switch (backplane)
173         {
174            case 0x00: bridge_count = 0; break; /* No bridges */
175            case 0x01: bridge_count = 1; break; /* 1 */
176            case 0x03: bridge_count = 2; break; /* 2 */
177            case 0x07: bridge_count = 3; break; /* 3 */
178            case 0x0f: bridge_count = 4; break; /* 4 */
179         };
180 
181         slot = PCI_SLOT(dev->devfn);
182         while (dev->bus->self) {
183                 /* Check for built-in bridges on hose 0. */
184                 if (hose->index == 0
185                     && (PCI_SLOT(dev->bus->self->devfn)
186                         > 20 - bridge_count)) {
187                         slot = PCI_SLOT(dev->devfn);
188                         break;
189                 }
190                 /* Must be a card-based bridge.  */
191                 pin = pci_swizzle_interrupt_pin(dev, pin);
192 
193                 /* Move up the chain of bridges.  */
194                 dev = dev->bus->self;
195         }
196         *pinp = pin;
197         return slot;
198 }
199 
200 /*
201  * The System Vectors
202  */
203 
204 struct alpha_machine_vector eiger_mv __initmv = {
205         .vector_name            = "Eiger",
206         DO_EV6_MMU,
207         DO_DEFAULT_RTC,
208         DO_TSUNAMI_IO,
209         .machine_check          = tsunami_machine_check,
210         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
211         .min_io_address         = DEFAULT_IO_BASE,
212         .min_mem_address        = DEFAULT_MEM_BASE,
213         .pci_dac_offset         = TSUNAMI_DAC_OFFSET,
214 
215         .nr_irqs                = 128,
216         .device_interrupt       = eiger_device_interrupt,
217 
218         .init_arch              = tsunami_init_arch,
219         .init_irq               = eiger_init_irq,
220         .init_rtc               = common_init_rtc,
221         .init_pci               = common_init_pci,
222         .kill_arch              = tsunami_kill_arch,
223         .pci_map_irq            = eiger_map_irq,
224         .pci_swizzle            = eiger_swizzle,
225 };
226 ALIAS_MV(eiger)
227 

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