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TOMOYO Linux Cross Reference
Linux/arch/alpha/kernel/time.c

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  1 /*
  2  *  linux/arch/alpha/kernel/time.c
  3  *
  4  *  Copyright (C) 1991, 1992, 1995, 1999, 2000  Linus Torvalds
  5  *
  6  * This file contains the PC-specific time handling details:
  7  * reading the RTC at bootup, etc..
  8  * 1994-07-02    Alan Modra
  9  *      fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
 10  * 1995-03-26    Markus Kuhn
 11  *      fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
 12  *      precision CMOS clock update
 13  * 1997-09-10   Updated NTP code according to technical memorandum Jan '96
 14  *              "A Kernel Model for Precision Timekeeping" by Dave Mills
 15  * 1997-01-09    Adrian Sun
 16  *      use interval timer if CONFIG_RTC=y
 17  * 1997-10-29    John Bowman (bowman@math.ualberta.ca)
 18  *      fixed tick loss calculation in timer_interrupt
 19  *      (round system clock to nearest tick instead of truncating)
 20  *      fixed algorithm in time_init for getting time from CMOS clock
 21  * 1999-04-16   Thorsten Kranzkowski (dl8bcu@gmx.net)
 22  *      fixed algorithm in do_gettimeofday() for calculating the precise time
 23  *      from processor cycle counter (now taking lost_ticks into account)
 24  * 2000-08-13   Jan-Benedict Glaw <jbglaw@lug-owl.de>
 25  *      Fixed time_init to be aware of epoches != 1900. This prevents
 26  *      booting up in 2048 for me;) Code is stolen from rtc.c.
 27  */
 28 #include <linux/config.h>
 29 #include <linux/errno.h>
 30 #include <linux/module.h>
 31 #include <linux/sched.h>
 32 #include <linux/kernel.h>
 33 #include <linux/param.h>
 34 #include <linux/string.h>
 35 #include <linux/mm.h>
 36 #include <linux/delay.h>
 37 #include <linux/ioport.h>
 38 #include <linux/irq.h>
 39 #include <linux/interrupt.h>
 40 #include <linux/init.h>
 41 #include <linux/bcd.h>
 42 
 43 #include <asm/uaccess.h>
 44 #include <asm/io.h>
 45 #include <asm/hwrpb.h>
 46 
 47 #include <linux/mc146818rtc.h>
 48 #include <linux/time.h>
 49 #include <linux/timex.h>
 50 
 51 #include "proto.h"
 52 #include "irq_impl.h"
 53 
 54 u64 jiffies_64 = INITIAL_JIFFIES;
 55 
 56 EXPORT_SYMBOL(jiffies_64);
 57 
 58 extern unsigned long wall_jiffies;      /* kernel/timer.c */
 59 
 60 static int set_rtc_mmss(unsigned long);
 61 
 62 spinlock_t rtc_lock = SPIN_LOCK_UNLOCKED;
 63 
 64 #define TICK_SIZE (tick_nsec / 1000)
 65 
 66 /*
 67  * Shift amount by which scaled_ticks_per_cycle is scaled.  Shifting
 68  * by 48 gives us 16 bits for HZ while keeping the accuracy good even
 69  * for large CPU clock rates.
 70  */
 71 #define FIX_SHIFT       48
 72 
 73 /* lump static variables together for more efficient access: */
 74 static struct {
 75         /* cycle counter last time it got invoked */
 76         __u32 last_time;
 77         /* ticks/cycle * 2^48 */
 78         unsigned long scaled_ticks_per_cycle;
 79         /* last time the CMOS clock got updated */
 80         time_t last_rtc_update;
 81         /* partial unused tick */
 82         unsigned long partial_tick;
 83 } state;
 84 
 85 unsigned long est_cycle_freq;
 86 
 87 
 88 static inline __u32 rpcc(void)
 89 {
 90     __u32 result;
 91     asm volatile ("rpcc %0" : "=r"(result));
 92     return result;
 93 }
 94 
 95 /*
 96  * Scheduler clock - returns current time in nanosec units.
 97  *
 98  * Copied from ARM code for expediency... ;-}
 99  */
100 unsigned long long sched_clock(void)
101 {
102         return (unsigned long long)jiffies * (1000000000 / HZ);
103 }
104 
105 
106 /*
107  * timer_interrupt() needs to keep up the real-time clock,
108  * as well as call the "do_timer()" routine every clocktick
109  */
110 irqreturn_t timer_interrupt(int irq, void *dev, struct pt_regs * regs)
111 {
112         unsigned long delta;
113         __u32 now;
114         long nticks;
115 
116 #ifndef CONFIG_SMP
117         /* Not SMP, do kernel PC profiling here.  */
118         if (!user_mode(regs))
119                 alpha_do_profile(regs->pc);
120 #endif
121 
122         write_seqlock(&xtime_lock);
123 
124         /*
125          * Calculate how many ticks have passed since the last update,
126          * including any previous partial leftover.  Save any resulting
127          * fraction for the next pass.
128          */
129         now = rpcc();
130         delta = now - state.last_time;
131         state.last_time = now;
132         delta = delta * state.scaled_ticks_per_cycle + state.partial_tick;
133         state.partial_tick = delta & ((1UL << FIX_SHIFT) - 1); 
134         nticks = delta >> FIX_SHIFT;
135 
136         while (nticks > 0) {
137                 do_timer(regs);
138                 nticks--;
139         }
140 
141         /*
142          * If we have an externally synchronized Linux clock, then update
143          * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
144          * called as close as possible to 500 ms before the new second starts.
145          */
146         if ((time_status & STA_UNSYNC) == 0
147             && xtime.tv_sec > state.last_rtc_update + 660
148             && xtime.tv_nsec >= 500000 - ((unsigned) TICK_SIZE) / 2
149             && xtime.tv_nsec <= 500000 + ((unsigned) TICK_SIZE) / 2) {
150                 int tmp = set_rtc_mmss(xtime.tv_sec);
151                 state.last_rtc_update = xtime.tv_sec - (tmp ? 600 : 0);
152         }
153 
154         write_sequnlock(&xtime_lock);
155         return IRQ_HANDLED;
156 }
157 
158 void
159 common_init_rtc(void)
160 {
161         unsigned char x;
162 
163         /* Reset periodic interrupt frequency.  */
164         x = CMOS_READ(RTC_FREQ_SELECT) & 0x3f;
165         /* Test includes known working values on various platforms
166            where 0x26 is wrong; we refuse to change those. */
167         if (x != 0x26 && x != 0x25 && x != 0x19 && x != 0x06) {
168                 printk("Setting RTC_FREQ to 1024 Hz (%x)\n", x);
169                 CMOS_WRITE(0x26, RTC_FREQ_SELECT);
170         }
171 
172         /* Turn on periodic interrupts.  */
173         x = CMOS_READ(RTC_CONTROL);
174         if (!(x & RTC_PIE)) {
175                 printk("Turning on RTC interrupts.\n");
176                 x |= RTC_PIE;
177                 x &= ~(RTC_AIE | RTC_UIE);
178                 CMOS_WRITE(x, RTC_CONTROL);
179         }
180         (void) CMOS_READ(RTC_INTR_FLAGS);
181 
182         outb(0x36, 0x43);       /* pit counter 0: system timer */
183         outb(0x00, 0x40);
184         outb(0x00, 0x40);
185 
186         outb(0xb6, 0x43);       /* pit counter 2: speaker */
187         outb(0x31, 0x42);
188         outb(0x13, 0x42);
189 
190         init_rtc_irq();
191 }
192 
193 
194 /* Validate a computed cycle counter result against the known bounds for
195    the given processor core.  There's too much brokenness in the way of
196    timing hardware for any one method to work everywhere.  :-(
197 
198    Return 0 if the result cannot be trusted, otherwise return the argument.  */
199 
200 static unsigned long __init
201 validate_cc_value(unsigned long cc)
202 {
203         static struct bounds {
204                 unsigned int min, max;
205         } cpu_hz[] __initdata = {
206                 [EV3_CPU]    = {   50000000,  200000000 },      /* guess */
207                 [EV4_CPU]    = {  100000000,  300000000 },
208                 [LCA4_CPU]   = {  100000000,  300000000 },      /* guess */
209                 [EV45_CPU]   = {  200000000,  300000000 },
210                 [EV5_CPU]    = {  250000000,  433000000 },
211                 [EV56_CPU]   = {  333000000,  667000000 },
212                 [PCA56_CPU]  = {  400000000,  600000000 },      /* guess */
213                 [PCA57_CPU]  = {  500000000,  600000000 },      /* guess */
214                 [EV6_CPU]    = {  466000000,  600000000 },
215                 [EV67_CPU]   = {  600000000,  750000000 },
216                 [EV68AL_CPU] = {  750000000,  940000000 },
217                 [EV68CB_CPU] = { 1000000000, 1333333333 },
218                 /* None of the following are shipping as of 2001-11-01.  */
219                 [EV68CX_CPU] = { 1000000000, 1700000000 },      /* guess */
220                 [EV69_CPU]   = { 1000000000, 1700000000 },      /* guess */
221                 [EV7_CPU]    = {  800000000, 1400000000 },      /* guess */
222                 [EV79_CPU]   = { 1000000000, 2000000000 },      /* guess */
223         };
224 
225         /* Allow for some drift in the crystal.  10MHz is more than enough.  */
226         const unsigned int deviation = 10000000;
227 
228         struct percpu_struct *cpu;
229         unsigned int index;
230 
231         cpu = (struct percpu_struct *)((char*)hwrpb + hwrpb->processor_offset);
232         index = cpu->type & 0xffffffff;
233 
234         /* If index out of bounds, no way to validate.  */
235         if (index >= sizeof(cpu_hz)/sizeof(cpu_hz[0]))
236                 return cc;
237 
238         /* If index contains no data, no way to validate.  */
239         if (cpu_hz[index].max == 0)
240                 return cc;
241 
242         if (cc < cpu_hz[index].min - deviation
243             || cc > cpu_hz[index].max + deviation)
244                 return 0;
245 
246         return cc;
247 }
248 
249 
250 /*
251  * Calibrate CPU clock using legacy 8254 timer/counter. Stolen from
252  * arch/i386/time.c.
253  */
254 
255 #define PIC_TICK_RATE   1193180UL
256 #define CALIBRATE_LATCH 0xffff
257 #define TIMEOUT_COUNT   0x100000
258 
259 static unsigned long __init
260 calibrate_cc_with_pic(void)
261 {
262         int cc, count = 0;
263 
264         /* Set the Gate high, disable speaker */
265         outb((inb(0x61) & ~0x02) | 0x01, 0x61);
266 
267         /*
268          * Now let's take care of CTC channel 2
269          *
270          * Set the Gate high, program CTC channel 2 for mode 0,
271          * (interrupt on terminal count mode), binary count,
272          * load 5 * LATCH count, (LSB and MSB) to begin countdown.
273          */
274         outb(0xb0, 0x43);               /* binary, mode 0, LSB/MSB, Ch 2 */
275         outb(CALIBRATE_LATCH & 0xff, 0x42);     /* LSB of count */
276         outb(CALIBRATE_LATCH >> 8, 0x42);       /* MSB of count */
277 
278         cc = rpcc();
279         do {
280                 count++;
281         } while ((inb(0x61) & 0x20) == 0 && count < TIMEOUT_COUNT);
282         cc = rpcc() - cc;
283 
284         /* Error: ECTCNEVERSET or ECPUTOOFAST.  */
285         if (count <= 1 || count == TIMEOUT_COUNT)
286                 return 0;
287 
288         return ((long)cc * PIC_TICK_RATE) / (CALIBRATE_LATCH + 1);
289 }
290 
291 /* The Linux interpretation of the CMOS clock register contents:
292    When the Update-In-Progress (UIP) flag goes from 1 to 0, the
293    RTC registers show the second which has precisely just started.
294    Let's hope other operating systems interpret the RTC the same way.  */
295 
296 static unsigned long __init
297 rpcc_after_update_in_progress(void)
298 {
299         do { } while (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP));
300         do { } while (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
301 
302         return rpcc();
303 }
304 
305 void __init
306 time_init(void)
307 {
308         unsigned int year, mon, day, hour, min, sec, cc1, cc2, epoch;
309         unsigned long cycle_freq, one_percent;
310         long diff;
311 
312         /* Calibrate CPU clock -- attempt #1.  */
313         if (!est_cycle_freq)
314                 est_cycle_freq = validate_cc_value(calibrate_cc_with_pic());
315 
316         cc1 = rpcc_after_update_in_progress();
317 
318         /* Calibrate CPU clock -- attempt #2.  */
319         if (!est_cycle_freq) {
320                 cc2 = rpcc_after_update_in_progress();
321                 est_cycle_freq = validate_cc_value(cc2 - cc1);
322                 cc1 = cc2;
323         }
324 
325         cycle_freq = hwrpb->cycle_freq;
326         if (est_cycle_freq) {
327                 /* If the given value is within 1% of what we calculated, 
328                    accept it.  Otherwise, use what we found.  */
329                 one_percent = cycle_freq / 100;
330                 diff = cycle_freq - est_cycle_freq;
331                 if (diff < 0)
332                         diff = -diff;
333                 if ((unsigned long)diff > one_percent) {
334                         cycle_freq = est_cycle_freq;
335                         printk("HWRPB cycle frequency bogus.  "
336                                "Estimated %lu Hz\n", cycle_freq);
337                 } else {
338                         est_cycle_freq = 0;
339                 }
340         } else if (! validate_cc_value (cycle_freq)) {
341                 printk("HWRPB cycle frequency bogus, "
342                        "and unable to estimate a proper value!\n");
343         }
344 
345         /* From John Bowman <bowman@math.ualberta.ca>: allow the values
346            to settle, as the Update-In-Progress bit going low isn't good
347            enough on some hardware.  2ms is our guess; we haven't found 
348            bogomips yet, but this is close on a 500Mhz box.  */
349         __delay(1000000);
350 
351         sec = CMOS_READ(RTC_SECONDS);
352         min = CMOS_READ(RTC_MINUTES);
353         hour = CMOS_READ(RTC_HOURS);
354         day = CMOS_READ(RTC_DAY_OF_MONTH);
355         mon = CMOS_READ(RTC_MONTH);
356         year = CMOS_READ(RTC_YEAR);
357 
358         if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
359                 BCD_TO_BIN(sec);
360                 BCD_TO_BIN(min);
361                 BCD_TO_BIN(hour);
362                 BCD_TO_BIN(day);
363                 BCD_TO_BIN(mon);
364                 BCD_TO_BIN(year);
365         }
366 
367         /* PC-like is standard; used for year < 20 || year >= 70 */
368         epoch = 1900;
369         if (year < 20)
370                 epoch = 2000;
371         else if (year >= 20 && year < 48)
372                 /* NT epoch */
373                 epoch = 1980;
374         else if (year >= 48 && year < 70)
375                 /* Digital UNIX epoch */
376                 epoch = 1952;
377 
378         printk(KERN_INFO "Using epoch = %d\n", epoch);
379 
380         if ((year += epoch) < 1970)
381                 year += 100;
382 
383         xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
384         xtime.tv_nsec = 0;
385 
386         wall_to_monotonic.tv_sec -= xtime.tv_sec;
387         wall_to_monotonic.tv_nsec = 0;
388 
389         if (HZ > (1<<16)) {
390                 extern void __you_loose (void);
391                 __you_loose();
392         }
393 
394         state.last_time = cc1;
395         state.scaled_ticks_per_cycle
396                 = ((unsigned long) HZ << FIX_SHIFT) / cycle_freq;
397         state.last_rtc_update = 0;
398         state.partial_tick = 0L;
399 
400         /* Startup the timer source. */
401         alpha_mv.init_rtc();
402 }
403 
404 /*
405  * Use the cycle counter to estimate an displacement from the last time
406  * tick.  Unfortunately the Alpha designers made only the low 32-bits of
407  * the cycle counter active, so we overflow on 8.2 seconds on a 500MHz
408  * part.  So we can't do the "find absolute time in terms of cycles" thing
409  * that the other ports do.
410  */
411 void
412 do_gettimeofday(struct timeval *tv)
413 {
414         unsigned long flags;
415         unsigned long sec, usec, lost, seq;
416         unsigned long delta_cycles, delta_usec, partial_tick;
417 
418         do {
419                 seq = read_seqbegin_irqsave(&xtime_lock, flags);
420 
421                 delta_cycles = rpcc() - state.last_time;
422                 sec = xtime.tv_sec;
423                 usec = (xtime.tv_nsec / 1000);
424                 partial_tick = state.partial_tick;
425                 lost = jiffies - wall_jiffies;
426 
427         } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
428 
429 #ifdef CONFIG_SMP
430         /* Until and unless we figure out how to get cpu cycle counters
431            in sync and keep them there, we can't use the rpcc tricks.  */
432         delta_usec = lost * (1000000 / HZ);
433 #else
434         /*
435          * usec = cycles * ticks_per_cycle * 2**48 * 1e6 / (2**48 * ticks)
436          *      = cycles * (s_t_p_c) * 1e6 / (2**48 * ticks)
437          *      = cycles * (s_t_p_c) * 15625 / (2**42 * ticks)
438          *
439          * which, given a 600MHz cycle and a 1024Hz tick, has a
440          * dynamic range of about 1.7e17, which is less than the
441          * 1.8e19 in an unsigned long, so we are safe from overflow.
442          *
443          * Round, but with .5 up always, since .5 to even is harder
444          * with no clear gain.
445          */
446 
447         delta_usec = (delta_cycles * state.scaled_ticks_per_cycle 
448                       + partial_tick
449                       + (lost << FIX_SHIFT)) * 15625;
450         delta_usec = ((delta_usec / ((1UL << (FIX_SHIFT-6-1)) * HZ)) + 1) / 2;
451 #endif
452 
453         usec += delta_usec;
454         if (usec >= 1000000) {
455                 sec += 1;
456                 usec -= 1000000;
457         }
458 
459         tv->tv_sec = sec;
460         tv->tv_usec = usec;
461 }
462 
463 EXPORT_SYMBOL(do_gettimeofday);
464 
465 int
466 do_settimeofday(struct timespec *tv)
467 {
468         time_t wtm_sec, sec = tv->tv_sec;
469         long wtm_nsec, nsec = tv->tv_nsec;
470         unsigned long delta_nsec;
471 
472         if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
473                 return -EINVAL;
474 
475         write_seqlock_irq(&xtime_lock);
476 
477         /* The offset that is added into time in do_gettimeofday above
478            must be subtracted out here to keep a coherent view of the
479            time.  Without this, a full-tick error is possible.  */
480 
481 #ifdef CONFIG_SMP
482         delta_nsec = (jiffies - wall_jiffies) * (NSEC_PER_SEC / HZ);
483 #else
484         delta_nsec = rpcc() - state.last_time;
485         delta_nsec = (delta_nsec * state.scaled_ticks_per_cycle 
486                       + state.partial_tick
487                       + ((jiffies - wall_jiffies) << FIX_SHIFT)) * 15625;
488         delta_nsec = ((delta_nsec / ((1UL << (FIX_SHIFT-6-1)) * HZ)) + 1) / 2;
489         delta_nsec *= 1000;
490 #endif
491 
492         nsec -= delta_nsec;
493 
494         wtm_sec  = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
495         wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
496 
497         set_normalized_timespec(&xtime, sec, nsec);
498         set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
499 
500         time_adjust = 0;                /* stop active adjtime() */
501         time_status |= STA_UNSYNC;
502         time_maxerror = NTP_PHASE_LIMIT;
503         time_esterror = NTP_PHASE_LIMIT;
504 
505         write_sequnlock_irq(&xtime_lock);
506         return 0;
507 }
508 
509 EXPORT_SYMBOL(do_settimeofday);
510 
511 
512 /*
513  * In order to set the CMOS clock precisely, set_rtc_mmss has to be
514  * called 500 ms after the second nowtime has started, because when
515  * nowtime is written into the registers of the CMOS clock, it will
516  * jump to the next second precisely 500 ms later. Check the Motorola
517  * MC146818A or Dallas DS12887 data sheet for details.
518  *
519  * BUG: This routine does not handle hour overflow properly; it just
520  *      sets the minutes. Usually you won't notice until after reboot!
521  */
522 
523 extern int abs(int);
524 
525 static int
526 set_rtc_mmss(unsigned long nowtime)
527 {
528         int retval = 0;
529         int real_seconds, real_minutes, cmos_minutes;
530         unsigned char save_control, save_freq_select;
531 
532         /* irq are locally disabled here */
533         spin_lock(&rtc_lock);
534         /* Tell the clock it's being set */
535         save_control = CMOS_READ(RTC_CONTROL);
536         CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
537 
538         /* Stop and reset prescaler */
539         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
540         CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
541 
542         cmos_minutes = CMOS_READ(RTC_MINUTES);
543         if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
544                 BCD_TO_BIN(cmos_minutes);
545 
546         /*
547          * since we're only adjusting minutes and seconds,
548          * don't interfere with hour overflow. This avoids
549          * messing with unknown time zones but requires your
550          * RTC not to be off by more than 15 minutes
551          */
552         real_seconds = nowtime % 60;
553         real_minutes = nowtime / 60;
554         if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) {
555                 /* correct for half hour time zone */
556                 real_minutes += 30;
557         }
558         real_minutes %= 60;
559 
560         if (abs(real_minutes - cmos_minutes) < 30) {
561                 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
562                         BIN_TO_BCD(real_seconds);
563                         BIN_TO_BCD(real_minutes);
564                 }
565                 CMOS_WRITE(real_seconds,RTC_SECONDS);
566                 CMOS_WRITE(real_minutes,RTC_MINUTES);
567         } else {
568                 printk(KERN_WARNING
569                        "set_rtc_mmss: can't update from %d to %d\n",
570                        cmos_minutes, real_minutes);
571                 retval = -1;
572         }
573 
574         /* The following flags have to be released exactly in this order,
575          * otherwise the DS12887 (popular MC146818A clone with integrated
576          * battery and quartz) will not reset the oscillator and will not
577          * update precisely 500 ms later. You won't find this mentioned in
578          * the Dallas Semiconductor data sheets, but who believes data
579          * sheets anyway ...                           -- Markus Kuhn
580          */
581         CMOS_WRITE(save_control, RTC_CONTROL);
582         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
583         spin_unlock(&rtc_lock);
584 
585         return retval;
586 }
587 

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