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TOMOYO Linux Cross Reference
Linux/arch/arc/include/asm/arcregs.h

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  1 /*
  2  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License version 2 as
  6  * published by the Free Software Foundation.
  7  */
  8 
  9 #ifndef _ASM_ARC_ARCREGS_H
 10 #define _ASM_ARC_ARCREGS_H
 11 
 12 /* Build Configuration Registers */
 13 #define ARC_REG_AUX_DCCM        0x18    /* DCCM Base Addr ARCv2 */
 14 #define ARC_REG_DCCM_BASE_BUILD 0x61    /* DCCM Base Addr ARCompact */
 15 #define ARC_REG_CRC_BCR         0x62
 16 #define ARC_REG_VECBASE_BCR     0x68
 17 #define ARC_REG_PERIBASE_BCR    0x69
 18 #define ARC_REG_FP_BCR          0x6B    /* ARCompact: Single-Precision FPU */
 19 #define ARC_REG_DPFP_BCR        0x6C    /* ARCompact: Dbl Precision FPU */
 20 #define ARC_REG_FP_V2_BCR       0xc8    /* ARCv2 FPU */
 21 #define ARC_REG_SLC_BCR         0xce
 22 #define ARC_REG_DCCM_BUILD      0x74    /* DCCM size (common) */
 23 #define ARC_REG_TIMERS_BCR      0x75
 24 #define ARC_REG_AP_BCR          0x76
 25 #define ARC_REG_ICCM_BUILD      0x78    /* ICCM size (common) */
 26 #define ARC_REG_XY_MEM_BCR      0x79
 27 #define ARC_REG_MAC_BCR         0x7a
 28 #define ARC_REG_MUL_BCR         0x7b
 29 #define ARC_REG_SWAP_BCR        0x7c
 30 #define ARC_REG_NORM_BCR        0x7d
 31 #define ARC_REG_MIXMAX_BCR      0x7e
 32 #define ARC_REG_BARREL_BCR      0x7f
 33 #define ARC_REG_D_UNCACH_BCR    0x6A
 34 #define ARC_REG_BPU_BCR         0xc0
 35 #define ARC_REG_ISA_CFG_BCR     0xc1
 36 #define ARC_REG_RTT_BCR         0xF2
 37 #define ARC_REG_IRQ_BCR         0xF3
 38 #define ARC_REG_SMART_BCR       0xFF
 39 #define ARC_REG_CLUSTER_BCR     0xcf
 40 #define ARC_REG_AUX_ICCM        0x208   /* ICCM Base Addr (ARCv2) */
 41 
 42 /* status32 Bits Positions */
 43 #define STATUS_AE_BIT           5       /* Exception active */
 44 #define STATUS_DE_BIT           6       /* PC is in delay slot */
 45 #define STATUS_U_BIT            7       /* User/Kernel mode */
 46 #define STATUS_L_BIT            12      /* Loop inhibit */
 47 
 48 /* These masks correspond to the status word(STATUS_32) bits */
 49 #define STATUS_AE_MASK          (1<<STATUS_AE_BIT)
 50 #define STATUS_DE_MASK          (1<<STATUS_DE_BIT)
 51 #define STATUS_U_MASK           (1<<STATUS_U_BIT)
 52 #define STATUS_L_MASK           (1<<STATUS_L_BIT)
 53 
 54 /*
 55  * ECR: Exception Cause Reg bits-n-pieces
 56  * [23:16] = Exception Vector
 57  * [15: 8] = Exception Cause Code
 58  * [ 7: 0] = Exception Parameters (for certain types only)
 59  */
 60 #ifdef CONFIG_ISA_ARCOMPACT
 61 #define ECR_V_MEM_ERR                   0x01
 62 #define ECR_V_INSN_ERR                  0x02
 63 #define ECR_V_MACH_CHK                  0x20
 64 #define ECR_V_ITLB_MISS                 0x21
 65 #define ECR_V_DTLB_MISS                 0x22
 66 #define ECR_V_PROTV                     0x23
 67 #define ECR_V_TRAP                      0x25
 68 #else
 69 #define ECR_V_MEM_ERR                   0x01
 70 #define ECR_V_INSN_ERR                  0x02
 71 #define ECR_V_MACH_CHK                  0x03
 72 #define ECR_V_ITLB_MISS                 0x04
 73 #define ECR_V_DTLB_MISS                 0x05
 74 #define ECR_V_PROTV                     0x06
 75 #define ECR_V_TRAP                      0x09
 76 #endif
 77 
 78 /* DTLB Miss and Protection Violation Cause Codes */
 79 
 80 #define ECR_C_PROTV_INST_FETCH          0x00
 81 #define ECR_C_PROTV_LOAD                0x01
 82 #define ECR_C_PROTV_STORE               0x02
 83 #define ECR_C_PROTV_XCHG                0x03
 84 #define ECR_C_PROTV_MISALIG_DATA        0x04
 85 
 86 #define ECR_C_BIT_PROTV_MISALIG_DATA    10
 87 
 88 /* Machine Check Cause Code Values */
 89 #define ECR_C_MCHK_DUP_TLB              0x01
 90 
 91 /* DTLB Miss Exception Cause Code Values */
 92 #define ECR_C_BIT_DTLB_LD_MISS          8
 93 #define ECR_C_BIT_DTLB_ST_MISS          9
 94 
 95 /* Auxiliary registers */
 96 #define AUX_IDENTITY            4
 97 #define AUX_INTR_VEC_BASE       0x25
 98 #define AUX_NON_VOL             0x5e
 99 
100 /*
101  * Floating Pt Registers
102  * Status regs are read-only (build-time) so need not be saved/restored
103  */
104 #define ARC_AUX_FP_STAT         0x300
105 #define ARC_AUX_DPFP_1L         0x301
106 #define ARC_AUX_DPFP_1H         0x302
107 #define ARC_AUX_DPFP_2L         0x303
108 #define ARC_AUX_DPFP_2H         0x304
109 #define ARC_AUX_DPFP_STAT       0x305
110 
111 #ifndef __ASSEMBLY__
112 
113 /*
114  ******************************************************************
115  *      Inline ASM macros to read/write AUX Regs
116  *      Essentially invocation of lr/sr insns from "C"
117  */
118 
119 #if 1
120 
121 #define read_aux_reg(reg)       __builtin_arc_lr(reg)
122 
123 /* gcc builtin sr needs reg param to be long immediate */
124 #define write_aux_reg(reg_immed, val)           \
125                 __builtin_arc_sr((unsigned int)(val), reg_immed)
126 
127 #else
128 
129 #define read_aux_reg(reg)               \
130 ({                                      \
131         unsigned int __ret;             \
132         __asm__ __volatile__(           \
133         "       lr    %0, [%1]"         \
134         : "=r"(__ret)                   \
135         : "i"(reg));                    \
136         __ret;                          \
137 })
138 
139 /*
140  * Aux Reg address is specified as long immediate by caller
141  * e.g.
142  *    write_aux_reg(0x69, some_val);
143  * This generates tightest code.
144  */
145 #define write_aux_reg(reg_imm, val)     \
146 ({                                      \
147         __asm__ __volatile__(           \
148         "       sr   %0, [%1]   \n"     \
149         :                               \
150         : "ir"(val), "i"(reg_imm));     \
151 })
152 
153 /*
154  * Aux Reg address is specified in a variable
155  *  * e.g.
156  *      reg_num = 0x69
157  *      write_aux_reg2(reg_num, some_val);
158  * This has to generate glue code to load the reg num from
159  *  memory to a reg hence not recommended.
160  */
161 #define write_aux_reg2(reg_in_var, val)         \
162 ({                                              \
163         unsigned int tmp;                       \
164                                                 \
165         __asm__ __volatile__(                   \
166         "       ld   %0, [%2]   \n\t"           \
167         "       sr   %1, [%0]   \n\t"           \
168         : "=&r"(tmp)                            \
169         : "r"(val), "memory"(&reg_in_var));     \
170 })
171 
172 #endif
173 
174 #define READ_BCR(reg, into)                             \
175 {                                                       \
176         unsigned int tmp;                               \
177         tmp = read_aux_reg(reg);                        \
178         if (sizeof(tmp) == sizeof(into)) {              \
179                 into = *((typeof(into) *)&tmp);         \
180         } else {                                        \
181                 extern void bogus_undefined(void);      \
182                 bogus_undefined();                      \
183         }                                               \
184 }
185 
186 #define WRITE_AUX(reg, into)                            \
187 {                                                       \
188         unsigned int tmp;                               \
189         if (sizeof(tmp) == sizeof(into)) {              \
190                 tmp = (*(unsigned int *)&(into));       \
191                 write_aux_reg(reg, tmp);                \
192         } else  {                                       \
193                 extern void bogus_undefined(void);      \
194                 bogus_undefined();                      \
195         }                                               \
196 }
197 
198 /* Helpers */
199 #define TO_KB(bytes)            ((bytes) >> 10)
200 #define TO_MB(bytes)            (TO_KB(bytes) >> 10)
201 #define PAGES_TO_KB(n_pages)    ((n_pages) << (PAGE_SHIFT - 10))
202 #define PAGES_TO_MB(n_pages)    (PAGES_TO_KB(n_pages) >> 10)
203 
204 
205 /*
206  ***************************************************************
207  * Build Configuration Registers, with encoded hardware config
208  */
209 struct bcr_identity {
210 #ifdef CONFIG_CPU_BIG_ENDIAN
211         unsigned int chip_id:16, cpu_id:8, family:8;
212 #else
213         unsigned int family:8, cpu_id:8, chip_id:16;
214 #endif
215 };
216 
217 struct bcr_isa {
218 #ifdef CONFIG_CPU_BIG_ENDIAN
219         unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
220                      pad1:11, atomic1:1, ver:8;
221 #else
222         unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1,
223                      ldd:1, pad2:4, div_rem:4;
224 #endif
225 };
226 
227 struct bcr_mpy {
228 #ifdef CONFIG_CPU_BIG_ENDIAN
229         unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
230 #else
231         unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
232 #endif
233 };
234 
235 struct bcr_extn_xymem {
236 #ifdef CONFIG_CPU_BIG_ENDIAN
237         unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
238 #else
239         unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
240 #endif
241 };
242 
243 struct bcr_perip {
244 #ifdef CONFIG_CPU_BIG_ENDIAN
245         unsigned int start:8, pad2:8, sz:8, ver:8;
246 #else
247         unsigned int ver:8, sz:8, pad2:8, start:8;
248 #endif
249 };
250 
251 struct bcr_iccm_arcompact {
252 #ifdef CONFIG_CPU_BIG_ENDIAN
253         unsigned int base:16, pad:5, sz:3, ver:8;
254 #else
255         unsigned int ver:8, sz:3, pad:5, base:16;
256 #endif
257 };
258 
259 struct bcr_iccm_arcv2 {
260 #ifdef CONFIG_CPU_BIG_ENDIAN
261         unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
262 #else
263         unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
264 #endif
265 };
266 
267 struct bcr_dccm_arcompact {
268 #ifdef CONFIG_CPU_BIG_ENDIAN
269         unsigned int res:21, sz:3, ver:8;
270 #else
271         unsigned int ver:8, sz:3, res:21;
272 #endif
273 };
274 
275 struct bcr_dccm_arcv2 {
276 #ifdef CONFIG_CPU_BIG_ENDIAN
277         unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
278 #else
279         unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
280 #endif
281 };
282 
283 /* ARCompact: Both SP and DP FPU BCRs have same format */
284 struct bcr_fp_arcompact {
285 #ifdef CONFIG_CPU_BIG_ENDIAN
286         unsigned int fast:1, ver:8;
287 #else
288         unsigned int ver:8, fast:1;
289 #endif
290 };
291 
292 struct bcr_fp_arcv2 {
293 #ifdef CONFIG_CPU_BIG_ENDIAN
294         unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
295 #else
296         unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
297 #endif
298 };
299 
300 struct bcr_timer {
301 #ifdef CONFIG_CPU_BIG_ENDIAN
302         unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
303 #else
304         unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
305 #endif
306 };
307 
308 struct bcr_bpu_arcompact {
309 #ifdef CONFIG_CPU_BIG_ENDIAN
310         unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
311 #else
312         unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
313 #endif
314 };
315 
316 struct bcr_bpu_arcv2 {
317 #ifdef CONFIG_CPU_BIG_ENDIAN
318         unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
319 #else
320         unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
321 #endif
322 };
323 
324 struct bcr_generic {
325 #ifdef CONFIG_CPU_BIG_ENDIAN
326         unsigned int info:24, ver:8;
327 #else
328         unsigned int ver:8, info:24;
329 #endif
330 };
331 
332 /*
333  *******************************************************************
334  * Generic structures to hold build configuration used at runtime
335  */
336 
337 struct cpuinfo_arc_mmu {
338         unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
339         unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
340 };
341 
342 struct cpuinfo_arc_cache {
343         unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1;
344 };
345 
346 struct cpuinfo_arc_bpu {
347         unsigned int ver, full, num_cache, num_pred;
348 };
349 
350 struct cpuinfo_arc_ccm {
351         unsigned int base_addr, sz;
352 };
353 
354 struct cpuinfo_arc {
355         struct cpuinfo_arc_cache icache, dcache, slc;
356         struct cpuinfo_arc_mmu mmu;
357         struct cpuinfo_arc_bpu bpu;
358         struct bcr_identity core;
359         struct bcr_isa isa;
360         unsigned int vec_base;
361         struct cpuinfo_arc_ccm iccm, dccm;
362         struct {
363                 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, pad1:3,
364                              fpu_sp:1, fpu_dp:1, pad2:6,
365                              debug:1, ap:1, smart:1, rtt:1, pad3:4,
366                              timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
367         } extn;
368         struct bcr_mpy extn_mpy;
369         struct bcr_extn_xymem extn_xymem;
370 };
371 
372 extern struct cpuinfo_arc cpuinfo_arc700[];
373 
374 static inline int is_isa_arcv2(void)
375 {
376         return IS_ENABLED(CONFIG_ISA_ARCV2);
377 }
378 
379 static inline int is_isa_arcompact(void)
380 {
381         return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
382 }
383 
384 #endif /* __ASEMBLY__ */
385 
386 #endif /* _ASM_ARC_ARCREGS_H */
387 

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