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Linux/arch/arc/include/asm/tlb-mmu1.h

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  1 /*
  2  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License version 2 as
  6  * published by the Free Software Foundation.
  7  */
  8 
  9 #ifndef __ASM_TLB_MMU_V1_H__
 10 #define __ASM_TLB_MMU_V1_H__
 11 
 12 #include <asm/mmu.h>
 13 
 14 #if defined(__ASSEMBLY__) && (CONFIG_ARC_MMU_VER == 1)
 15 
 16 .macro TLB_WRITE_HEURISTICS
 17 
 18 #define JH_HACK1
 19 #undef JH_HACK2
 20 #undef JH_HACK3
 21 
 22 #ifdef JH_HACK3
 23 ; Calculate set index for 2-way MMU
 24 ; -avoiding use of GetIndex from MMU
 25 ;   and its unpleasant LFSR pseudo-random sequence
 26 ;
 27 ; r1 = TLBPD0 from TLB_RELOAD above
 28 ;
 29 ; -- jh_ex_way_set not cleared on startup
 30 ;    didn't want to change setup.c
 31 ;    hence extra instruction to clean
 32 ;
 33 ; -- should be in cache since in same line
 34 ;    as r0/r1 saves above
 35 ;
 36 ld  r0,[jh_ex_way_sel]  ; victim pointer
 37 and r0,r0,1         ; clean
 38 xor.f   r0,r0,1         ; flip
 39 st  r0,[jh_ex_way_sel]  ; store back
 40 asr r0,r1,12        ; get set # <<1, note bit 12=R=0
 41 or.nz   r0,r0,1         ; set way bit
 42 and r0,r0,0xff      ; clean
 43 sr  r0,[ARC_REG_TLBINDEX]
 44 #endif
 45 
 46 #ifdef JH_HACK2
 47 ; JH hack #2
 48 ;  Faster than hack #1 in non-thrash case, but hard-coded for 2-way MMU
 49 ;  Slower in thrash case (where it matters) because more code is executed
 50 ;  Inefficient due to two-register paradigm of this miss handler
 51 ;
 52 /* r1 = data TLBPD0 at this point */
 53 lr      r0,[eret]               /* instruction address */
 54 xor     r0,r0,r1                /* compare set #       */
 55 and.f   r0,r0,0x000fe000        /* 2-way MMU mask      */
 56 bne     88f                     /* not in same set - no need to probe */
 57 
 58 lr      r0,[eret]               /* instruction address */
 59 and     r0,r0,PAGE_MASK         /* VPN of instruction address */
 60 ; lr  r1,[ARC_REG_TLBPD0]     /* Data VPN+ASID - already in r1 from TLB_RELOAD*/
 61 and     r1,r1,0xff              /* Data ASID */
 62 or      r0,r0,r1                /* Instruction address + Data ASID */
 63 
 64 lr      r1,[ARC_REG_TLBPD0]     /* save TLBPD0 containing data TLB*/
 65 sr      r0,[ARC_REG_TLBPD0]     /* write instruction address to TLBPD0 */
 66 sr      TLBProbe, [ARC_REG_TLBCOMMAND] /* Look for instruction */
 67 lr      r0,[ARC_REG_TLBINDEX]   /* r0 = index where instruction is, if at all */
 68 sr      r1,[ARC_REG_TLBPD0]     /* restore TLBPD0 */
 69 
 70 xor     r0,r0,1                 /* flip bottom bit of data index */
 71 b.d     89f
 72 sr      r0,[ARC_REG_TLBINDEX]   /* and put it back */
 73 88:
 74 sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
 75 89:
 76 #endif
 77 
 78 #ifdef JH_HACK1
 79 ;
 80 ; Always checks whether instruction will be kicked out by dtlb miss
 81 ;
 82 mov_s   r3, r1                  ; save PD0 prepared by TLB_RELOAD in r3
 83 lr      r0,[eret]               /* instruction address */
 84 and     r0,r0,PAGE_MASK         /* VPN of instruction address */
 85 bmsk    r1,r3,7                 /* Data ASID, bits 7-0 */
 86 or_s    r0,r0,r1                /* Instruction address + Data ASID */
 87 
 88 sr      r0,[ARC_REG_TLBPD0]     /* write instruction address to TLBPD0 */
 89 sr      TLBProbe, [ARC_REG_TLBCOMMAND] /* Look for instruction */
 90 lr      r0,[ARC_REG_TLBINDEX]   /* r0 = index where instruction is, if at all */
 91 sr      r3,[ARC_REG_TLBPD0]     /* restore TLBPD0 */
 92 
 93 sr      TLBGetIndex, [ARC_REG_TLBCOMMAND]
 94 lr      r1,[ARC_REG_TLBINDEX]   /* r1 = index where MMU wants to put data */
 95 cmp     r0,r1                   /* if no match on indices, go around */
 96 xor.eq  r1,r1,1                 /* flip bottom bit of data index */
 97 sr      r1,[ARC_REG_TLBINDEX]   /* and put it back */
 98 #endif
 99 
100 .endm
101 
102 #endif
103 
104 #endif
105 

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