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Linux/arch/arc/kernel/time.c

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  1 /*
  2  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License version 2 as
  6  * published by the Free Software Foundation.
  7  *
  8  * vineetg: Jan 1011
  9  *  -sched_clock( ) no longer jiffies based. Uses the same clocksource
 10  *   as gtod
 11  *
 12  * Rajeshwarr/Vineetg: Mar 2008
 13  *  -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code)
 14  *   for arch independent gettimeofday()
 15  *  -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers
 16  *
 17  * Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c
 18  */
 19 
 20 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1
 21  * Each can programmed to go from @count to @limit and optionally
 22  * interrupt when that happens.
 23  * A write to Control Register clears the Interrupt
 24  *
 25  * We've designated TIMER0 for events (clockevents)
 26  * while TIMER1 for free running (clocksource)
 27  *
 28  * Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1
 29  */
 30 
 31 #include <linux/spinlock.h>
 32 #include <linux/interrupt.h>
 33 #include <linux/module.h>
 34 #include <linux/sched.h>
 35 #include <linux/kernel.h>
 36 #include <linux/time.h>
 37 #include <linux/init.h>
 38 #include <linux/timex.h>
 39 #include <linux/profile.h>
 40 #include <linux/clocksource.h>
 41 #include <linux/clockchips.h>
 42 #include <asm/irq.h>
 43 #include <asm/arcregs.h>
 44 #include <asm/clk.h>
 45 #include <asm/mach_desc.h>
 46 
 47 /* Timer related Aux registers */
 48 #define ARC_REG_TIMER0_LIMIT    0x23    /* timer 0 limit */
 49 #define ARC_REG_TIMER0_CTRL     0x22    /* timer 0 control */
 50 #define ARC_REG_TIMER0_CNT      0x21    /* timer 0 count */
 51 #define ARC_REG_TIMER1_LIMIT    0x102   /* timer 1 limit */
 52 #define ARC_REG_TIMER1_CTRL     0x101   /* timer 1 control */
 53 #define ARC_REG_TIMER1_CNT      0x100   /* timer 1 count */
 54 
 55 #define TIMER_CTRL_IE           (1 << 0) /* Interupt when Count reachs limit */
 56 #define TIMER_CTRL_NH           (1 << 1) /* Count only when CPU NOT halted */
 57 
 58 #define ARC_TIMER_MAX   0xFFFFFFFF
 59 
 60 /********** Clock Source Device *********/
 61 
 62 #ifdef CONFIG_ARC_HAS_RTSC
 63 
 64 int arc_counter_setup(void)
 65 {
 66         /*
 67          * For SMP this needs to be 0. However Kconfig glue doesn't
 68          * enable this option for SMP configs
 69          */
 70         return 1;
 71 }
 72 
 73 static cycle_t arc_counter_read(struct clocksource *cs)
 74 {
 75         unsigned long flags;
 76         union {
 77 #ifdef CONFIG_CPU_BIG_ENDIAN
 78                 struct { u32 high, low; };
 79 #else
 80                 struct { u32 low, high; };
 81 #endif
 82                 cycle_t  full;
 83         } stamp;
 84 
 85         flags = arch_local_irq_save();
 86 
 87         __asm__ __volatile(
 88         "       .extCoreRegister tsch, 58,  r, cannot_shortcut  \n"
 89         "       rtsc %0, 0      \n"
 90         "       mov  %1, 0      \n"
 91         : "=r" (stamp.low), "=r" (stamp.high));
 92 
 93         arch_local_irq_restore(flags);
 94 
 95         return stamp.full;
 96 }
 97 
 98 static struct clocksource arc_counter = {
 99         .name   = "ARC RTSC",
100         .rating = 300,
101         .read   = arc_counter_read,
102         .mask   = CLOCKSOURCE_MASK(32),
103         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
104 };
105 
106 #else /* !CONFIG_ARC_HAS_RTSC */
107 
108 static bool is_usable_as_clocksource(void)
109 {
110 #ifdef CONFIG_SMP
111         return 0;
112 #else
113         return 1;
114 #endif
115 }
116 
117 /*
118  * set 32bit TIMER1 to keep counting monotonically and wraparound
119  */
120 int arc_counter_setup(void)
121 {
122         write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
123         write_aux_reg(ARC_REG_TIMER1_CNT, 0);
124         write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
125 
126         return is_usable_as_clocksource();
127 }
128 
129 static cycle_t arc_counter_read(struct clocksource *cs)
130 {
131         return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
132 }
133 
134 static struct clocksource arc_counter = {
135         .name   = "ARC Timer1",
136         .rating = 300,
137         .read   = arc_counter_read,
138         .mask   = CLOCKSOURCE_MASK(32),
139         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
140 };
141 
142 #endif
143 
144 /********** Clock Event Device *********/
145 
146 /*
147  * Arm the timer to interrupt after @cycles
148  * The distinction for oneshot/periodic is done in arc_event_timer_ack() below
149  */
150 static void arc_timer_event_setup(unsigned int cycles)
151 {
152         write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
153         write_aux_reg(ARC_REG_TIMER0_CNT, 0);   /* start from 0 */
154 
155         write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
156 }
157 
158 
159 static int arc_clkevent_set_next_event(unsigned long delta,
160                                        struct clock_event_device *dev)
161 {
162         arc_timer_event_setup(delta);
163         return 0;
164 }
165 
166 static void arc_clkevent_set_mode(enum clock_event_mode mode,
167                                   struct clock_event_device *dev)
168 {
169         switch (mode) {
170         case CLOCK_EVT_MODE_PERIODIC:
171                 /*
172                  * At X Hz, 1 sec = 1000ms -> X cycles;
173                  *                    10ms -> X / 100 cycles
174                  */
175                 arc_timer_event_setup(arc_get_core_freq() / HZ);
176                 break;
177         case CLOCK_EVT_MODE_ONESHOT:
178                 break;
179         default:
180                 break;
181         }
182 
183         return;
184 }
185 
186 static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
187         .name           = "ARC Timer0",
188         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
189         .mode           = CLOCK_EVT_MODE_UNUSED,
190         .rating         = 300,
191         .irq            = TIMER0_IRQ,   /* hardwired, no need for resources */
192         .set_next_event = arc_clkevent_set_next_event,
193         .set_mode       = arc_clkevent_set_mode,
194 };
195 
196 static irqreturn_t timer_irq_handler(int irq, void *dev_id)
197 {
198         /*
199          * Note that generic IRQ core could have passed @evt for @dev_id if
200          * irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
201          */
202         struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
203         int irq_reenable = evt->mode == CLOCK_EVT_MODE_PERIODIC;
204 
205         /*
206          * Any write to CTRL reg ACks the interrupt, we rewrite the
207          * Count when [N]ot [H]alted bit.
208          * And re-arm it if perioid by [I]nterrupt [E]nable bit
209          */
210         write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
211 
212         evt->event_handler(evt);
213 
214         return IRQ_HANDLED;
215 }
216 
217 /*
218  * Setup the local event timer for @cpu
219  */
220 void arc_local_timer_setup()
221 {
222         struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
223         int cpu = smp_processor_id();
224 
225         evt->cpumask = cpumask_of(cpu);
226         clockevents_config_and_register(evt, arc_get_core_freq(),
227                                         0, ARC_TIMER_MAX);
228 
229         /* setup the per-cpu timer IRQ handler - for all cpus */
230         arc_request_percpu_irq(TIMER0_IRQ, cpu, timer_irq_handler,
231                                "Timer0 (per-cpu-tick)", evt);
232 }
233 
234 /*
235  * Called from start_kernel() - boot CPU only
236  *
237  * -Sets up h/w timers as applicable on boot cpu
238  * -Also sets up any global state needed for timer subsystem:
239  *    - for "counting" timer, registers a clocksource, usable across CPUs
240  *      (provided that underlying counter h/w is synchronized across cores)
241  *    - for "event" timer, sets up TIMER0 IRQ (as that is platform agnostic)
242  */
243 void __init time_init(void)
244 {
245         /*
246          * sets up the timekeeping free-flowing counter which also returns
247          * whether the counter is usable as clocksource
248          */
249         if (arc_counter_setup())
250                 /*
251                  * CLK upto 4.29 GHz can be safely represented in 32 bits
252                  * because Max 32 bit number is 4,294,967,295
253                  */
254                 clocksource_register_hz(&arc_counter, arc_get_core_freq());
255 
256         /* sets up the periodic event timer */
257         arc_local_timer_setup();
258 
259         if (machine_desc->init_time)
260                 machine_desc->init_time();
261 }
262 

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