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Linux/arch/arm/common/it8152.c

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  1 /*
  2  * linux/arch/arm/common/it8152.c
  3  *
  4  * Copyright Compulab Ltd, 2002-2007
  5  * Mike Rapoport <mike@compulab.co.il>
  6  *
  7  * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
  8  * (see this file for respective copyrights)
  9  *
 10  * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
 11  * and demux code.
 12  *
 13  * This program is free software; you can redistribute it and/or modify
 14  * it under the terms of the GNU General Public License version 2 as
 15  * published by the Free Software Foundation.
 16  */
 17 
 18 #include <linux/sched.h>
 19 #include <linux/kernel.h>
 20 #include <linux/pci.h>
 21 #include <linux/ptrace.h>
 22 #include <linux/interrupt.h>
 23 #include <linux/mm.h>
 24 #include <linux/slab.h>
 25 #include <linux/init.h>
 26 #include <linux/ioport.h>
 27 #include <linux/irq.h>
 28 #include <linux/io.h>
 29 
 30 #include <asm/mach/pci.h>
 31 #include <asm/hardware/it8152.h>
 32 
 33 #define MAX_SLOTS               21
 34 
 35 static void it8152_mask_irq(unsigned int irq)
 36 {
 37        if (irq >= IT8152_LD_IRQ(0)) {
 38                __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) |
 39                             (1 << (irq - IT8152_LD_IRQ(0)))),
 40                             IT8152_INTC_LDCNIMR);
 41        } else if (irq >= IT8152_LP_IRQ(0)) {
 42                __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) |
 43                             (1 << (irq - IT8152_LP_IRQ(0)))),
 44                             IT8152_INTC_LPCNIMR);
 45        } else if (irq >= IT8152_PD_IRQ(0)) {
 46                __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) |
 47                             (1 << (irq - IT8152_PD_IRQ(0)))),
 48                             IT8152_INTC_PDCNIMR);
 49        }
 50 }
 51 
 52 static void it8152_unmask_irq(unsigned int irq)
 53 {
 54        if (irq >= IT8152_LD_IRQ(0)) {
 55                __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
 56                              ~(1 << (irq - IT8152_LD_IRQ(0)))),
 57                             IT8152_INTC_LDCNIMR);
 58        } else if (irq >= IT8152_LP_IRQ(0)) {
 59                __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) &
 60                              ~(1 << (irq - IT8152_LP_IRQ(0)))),
 61                             IT8152_INTC_LPCNIMR);
 62        } else if (irq >= IT8152_PD_IRQ(0)) {
 63                __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) &
 64                              ~(1 << (irq - IT8152_PD_IRQ(0)))),
 65                             IT8152_INTC_PDCNIMR);
 66        }
 67 }
 68 
 69 static struct irq_chip it8152_irq_chip = {
 70         .name           = "it8152",
 71         .ack            = it8152_mask_irq,
 72         .mask           = it8152_mask_irq,
 73         .unmask         = it8152_unmask_irq,
 74 };
 75 
 76 void it8152_init_irq(void)
 77 {
 78         int irq;
 79 
 80         __raw_writel((0xffff), IT8152_INTC_PDCNIMR);
 81         __raw_writel((0), IT8152_INTC_PDCNIRR);
 82         __raw_writel((0xffff), IT8152_INTC_LPCNIMR);
 83         __raw_writel((0), IT8152_INTC_LPCNIRR);
 84         __raw_writel((0xffff), IT8152_INTC_LDCNIMR);
 85         __raw_writel((0), IT8152_INTC_LDCNIRR);
 86 
 87         for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
 88                 set_irq_chip(irq, &it8152_irq_chip);
 89                 set_irq_handler(irq, handle_level_irq);
 90                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 91         }
 92 }
 93 
 94 void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
 95 {
 96        int bits_pd, bits_lp, bits_ld;
 97        int i;
 98 
 99        while (1) {
100                /* Read all */
101                bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
102                bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
103                bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
104 
105                /* Ack */
106                __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR);
107                __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR);
108                __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR);
109 
110                if (!(bits_ld | bits_lp | bits_pd)) {
111                        /* Re-read to guarantee, that there was a moment of
112                           time, when they all three were 0. */
113                        bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
114                        bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
115                        bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
116                        if (!(bits_ld | bits_lp | bits_pd))
117                                return;
118                }
119 
120                bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
121                while (bits_pd) {
122                        i = __ffs(bits_pd);
123                        generic_handle_irq(IT8152_PD_IRQ(i));
124                        bits_pd &= ~(1 << i);
125                }
126 
127                bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
128                while (bits_lp) {
129                        i = __ffs(bits_lp);
130                        generic_handle_irq(IT8152_LP_IRQ(i));
131                        bits_lp &= ~(1 << i);
132                }
133 
134                bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
135                while (bits_ld) {
136                        i = __ffs(bits_ld);
137                        generic_handle_irq(IT8152_LD_IRQ(i));
138                        bits_ld &= ~(1 << i);
139                }
140        }
141 }
142 
143 /* mapping for on-chip devices */
144 int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
145 {
146         if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
147             (dev->device == PCI_DEVICE_ID_ITE_8152)) {
148                 if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO)
149                         return IT8152_AUDIO_INT;
150                 if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)
151                         return IT8152_USB_INT;
152                 if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA)
153                         return IT8152_CDMA_INT;
154         }
155 
156         return 0;
157 }
158 
159 static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus,
160                                                  unsigned int devfn)
161 {
162         unsigned long addr = 0;
163 
164         if (bus->number == 0) {
165                         if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
166                                 addr = (devfn << 8);
167         } else
168                 addr = (bus->number << 16) | (devfn << 8);
169 
170         return addr;
171 }
172 
173 static int it8152_pci_read_config(struct pci_bus *bus,
174                                   unsigned int devfn, int where,
175                                   int size, u32 *value)
176 {
177         unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
178         u32 v;
179         int shift;
180 
181         shift = (where & 3);
182 
183         __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
184         v = (__raw_readl(IT8152_PCI_CFG_DATA)  >> (8 * (shift)));
185 
186         *value = v;
187 
188         return PCIBIOS_SUCCESSFUL;
189 }
190 
191 static int it8152_pci_write_config(struct pci_bus *bus,
192                                    unsigned int devfn, int where,
193                                    int size, u32 value)
194 {
195         unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
196         u32 v, vtemp, mask = 0;
197         int shift;
198 
199         if (size == 1)
200                 mask = 0xff;
201         if (size == 2)
202                 mask = 0xffff;
203 
204         shift = (where & 3);
205 
206         __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
207         vtemp = __raw_readl(IT8152_PCI_CFG_DATA);
208 
209         if (mask)
210                 vtemp &= ~(mask << (8 * shift));
211         else
212                 vtemp = 0;
213 
214         v = (value << (8 * shift));
215         __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
216         __raw_writel((v | vtemp), IT8152_PCI_CFG_DATA);
217 
218         return PCIBIOS_SUCCESSFUL;
219 }
220 
221 static struct pci_ops it8152_ops = {
222         .read = it8152_pci_read_config,
223         .write = it8152_pci_write_config,
224 };
225 
226 static struct resource it8152_io = {
227         .name   = "IT8152 PCI I/O region",
228         .flags  = IORESOURCE_IO,
229 };
230 
231 static struct resource it8152_mem = {
232         .name   = "IT8152 PCI memory region",
233         .start  = 0x10000000,
234         .end    = 0x13e00000,
235         .flags  = IORESOURCE_MEM,
236 };
237 
238 /*
239  * The following functions are needed for DMA bouncing.
240  * ITE8152 chip can addrees up to 64MByte, so all the devices
241  * connected to ITE8152 (PCI and USB) should have limited DMA window
242  */
243 
244 /*
245  * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
246  * other devices.
247  */
248 static int it8152_pci_platform_notify(struct device *dev)
249 {
250         if (dev->bus == &pci_bus_type) {
251                 if (dev->dma_mask)
252                         *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
253                 dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
254                 dmabounce_register_dev(dev, 2048, 4096);
255         }
256         return 0;
257 }
258 
259 static int it8152_pci_platform_notify_remove(struct device *dev)
260 {
261         if (dev->bus == &pci_bus_type)
262                 dmabounce_unregister_dev(dev);
263 
264         return 0;
265 }
266 
267 int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
268 {
269         dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
270                 __func__, dma_addr, size);
271         return (dev->bus == &pci_bus_type) &&
272                 ((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
273 }
274 
275 /*
276  * We override these so we properly do dmabounce otherwise drivers
277  * are able to set the dma_mask to 0xffffffff and we can no longer
278  * trap bounces. :(
279  *
280  * We just return true on everyhing except for < 64MB in which case
281  * we will fail miseralby and die since we can't handle that case.
282  */
283 int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
284 {
285         dev_dbg(&dev->dev, "%s: %llx\n", __func__, mask);
286         if (mask >= PHYS_OFFSET + SZ_64M - 1)
287                 return 0;
288 
289         return -EIO;
290 }
291 
292 int
293 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
294 {
295         dev_dbg(&dev->dev, "%s: %llx\n", __func__, mask);
296         if (mask >= PHYS_OFFSET + SZ_64M - 1)
297                 return 0;
298 
299         return -EIO;
300 }
301 
302 int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
303 {
304         it8152_io.start = IT8152_IO_BASE + 0x12000;
305         it8152_io.end   = IT8152_IO_BASE + 0x12000 + 0x100000;
306 
307         sys->mem_offset = 0x10000000;
308         sys->io_offset  = IT8152_IO_BASE;
309 
310         if (request_resource(&ioport_resource, &it8152_io)) {
311                 printk(KERN_ERR "PCI: unable to allocate IO region\n");
312                 goto err0;
313         }
314         if (request_resource(&iomem_resource, &it8152_mem)) {
315                 printk(KERN_ERR "PCI: unable to allocate memory region\n");
316                 goto err1;
317         }
318 
319         sys->resource[0] = &it8152_io;
320         sys->resource[1] = &it8152_mem;
321 
322         if (platform_notify || platform_notify_remove) {
323                 printk(KERN_ERR "PCI: Can't use platform_notify\n");
324                 goto err2;
325         }
326 
327         platform_notify = it8152_pci_platform_notify;
328         platform_notify_remove = it8152_pci_platform_notify_remove;
329 
330         return 1;
331 
332 err2:
333         release_resource(&it8152_io);
334 err1:
335         release_resource(&it8152_mem);
336 err0:
337         return -EBUSY;
338 }
339 
340 /*
341  * If we set up a device for bus mastering, we need to check the latency
342  * timer as we don't have even crappy BIOSes to set it properly.
343  * The implementation is from arch/i386/pci/i386.c
344  */
345 unsigned int pcibios_max_latency = 255;
346 
347 void pcibios_set_master(struct pci_dev *dev)
348 {
349         u8 lat;
350 
351         /* no need to update on-chip OHCI controller */
352         if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
353             (dev->device == PCI_DEVICE_ID_ITE_8152) &&
354             ((dev->class >> 8) == PCI_CLASS_SERIAL_USB))
355                 return;
356 
357         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
358         if (lat < 16)
359                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
360         else if (lat > pcibios_max_latency)
361                 lat = pcibios_max_latency;
362         else
363                 return;
364         printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
365                pci_name(dev), lat);
366         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
367 }
368 
369 
370 struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
371 {
372         return pci_scan_bus(nr, &it8152_ops, sys);
373 }
374 
375 

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