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Linux/arch/arm/common/it8152.c

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  1 /*
  2  * linux/arch/arm/common/it8152.c
  3  *
  4  * Copyright Compulab Ltd, 2002-2007
  5  * Mike Rapoport <mike@compulab.co.il>
  6  *
  7  * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
  8  * (see this file for respective copyrights)
  9  *
 10  * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
 11  * and demux code.
 12  *
 13  * This program is free software; you can redistribute it and/or modify
 14  * it under the terms of the GNU General Public License version 2 as
 15  * published by the Free Software Foundation.
 16  */
 17 
 18 #include <linux/sched.h>
 19 #include <linux/kernel.h>
 20 #include <linux/pci.h>
 21 #include <linux/ptrace.h>
 22 #include <linux/interrupt.h>
 23 #include <linux/mm.h>
 24 #include <linux/init.h>
 25 #include <linux/ioport.h>
 26 #include <linux/irq.h>
 27 #include <linux/io.h>
 28 #include <linux/export.h>
 29 
 30 #include <asm/mach/pci.h>
 31 #include <asm/hardware/it8152.h>
 32 
 33 #define MAX_SLOTS               21
 34 
 35 static void it8152_mask_irq(struct irq_data *d)
 36 {
 37         unsigned int irq = d->irq;
 38 
 39        if (irq >= IT8152_LD_IRQ(0)) {
 40                __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) |
 41                             (1 << (irq - IT8152_LD_IRQ(0)))),
 42                             IT8152_INTC_LDCNIMR);
 43        } else if (irq >= IT8152_LP_IRQ(0)) {
 44                __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) |
 45                             (1 << (irq - IT8152_LP_IRQ(0)))),
 46                             IT8152_INTC_LPCNIMR);
 47        } else if (irq >= IT8152_PD_IRQ(0)) {
 48                __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) |
 49                             (1 << (irq - IT8152_PD_IRQ(0)))),
 50                             IT8152_INTC_PDCNIMR);
 51        }
 52 }
 53 
 54 static void it8152_unmask_irq(struct irq_data *d)
 55 {
 56         unsigned int irq = d->irq;
 57 
 58        if (irq >= IT8152_LD_IRQ(0)) {
 59                __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
 60                              ~(1 << (irq - IT8152_LD_IRQ(0)))),
 61                             IT8152_INTC_LDCNIMR);
 62        } else if (irq >= IT8152_LP_IRQ(0)) {
 63                __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) &
 64                              ~(1 << (irq - IT8152_LP_IRQ(0)))),
 65                             IT8152_INTC_LPCNIMR);
 66        } else if (irq >= IT8152_PD_IRQ(0)) {
 67                __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) &
 68                              ~(1 << (irq - IT8152_PD_IRQ(0)))),
 69                             IT8152_INTC_PDCNIMR);
 70        }
 71 }
 72 
 73 static struct irq_chip it8152_irq_chip = {
 74         .name           = "it8152",
 75         .irq_ack        = it8152_mask_irq,
 76         .irq_mask       = it8152_mask_irq,
 77         .irq_unmask     = it8152_unmask_irq,
 78 };
 79 
 80 void it8152_init_irq(void)
 81 {
 82         int irq;
 83 
 84         __raw_writel((0xffff), IT8152_INTC_PDCNIMR);
 85         __raw_writel((0), IT8152_INTC_PDCNIRR);
 86         __raw_writel((0xffff), IT8152_INTC_LPCNIMR);
 87         __raw_writel((0), IT8152_INTC_LPCNIRR);
 88         __raw_writel((0xffff), IT8152_INTC_LDCNIMR);
 89         __raw_writel((0), IT8152_INTC_LDCNIRR);
 90 
 91         for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
 92                 irq_set_chip_and_handler(irq, &it8152_irq_chip,
 93                                          handle_level_irq);
 94                 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
 95         }
 96 }
 97 
 98 void it8152_irq_demux(struct irq_desc *desc)
 99 {
100        int bits_pd, bits_lp, bits_ld;
101        int i;
102 
103        while (1) {
104                /* Read all */
105                bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
106                bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
107                bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
108 
109                /* Ack */
110                __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR);
111                __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR);
112                __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR);
113 
114                if (!(bits_ld | bits_lp | bits_pd)) {
115                        /* Re-read to guarantee, that there was a moment of
116                           time, when they all three were 0. */
117                        bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
118                        bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
119                        bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
120                        if (!(bits_ld | bits_lp | bits_pd))
121                                return;
122                }
123 
124                bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
125                while (bits_pd) {
126                        i = __ffs(bits_pd);
127                        generic_handle_irq(IT8152_PD_IRQ(i));
128                        bits_pd &= ~(1 << i);
129                }
130 
131                bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
132                while (bits_lp) {
133                        i = __ffs(bits_lp);
134                        generic_handle_irq(IT8152_LP_IRQ(i));
135                        bits_lp &= ~(1 << i);
136                }
137 
138                bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
139                while (bits_ld) {
140                        i = __ffs(bits_ld);
141                        generic_handle_irq(IT8152_LD_IRQ(i));
142                        bits_ld &= ~(1 << i);
143                }
144        }
145 }
146 
147 /* mapping for on-chip devices */
148 int __init it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
149 {
150         if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
151             (dev->device == PCI_DEVICE_ID_ITE_8152)) {
152                 if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO)
153                         return IT8152_AUDIO_INT;
154                 if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)
155                         return IT8152_USB_INT;
156                 if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA)
157                         return IT8152_CDMA_INT;
158         }
159 
160         return 0;
161 }
162 
163 static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus,
164                                                  unsigned int devfn)
165 {
166         unsigned long addr = 0;
167 
168         if (bus->number == 0) {
169                         if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
170                                 addr = (devfn << 8);
171         } else
172                 addr = (bus->number << 16) | (devfn << 8);
173 
174         return addr;
175 }
176 
177 static int it8152_pci_read_config(struct pci_bus *bus,
178                                   unsigned int devfn, int where,
179                                   int size, u32 *value)
180 {
181         unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
182         u32 v;
183         int shift;
184 
185         shift = (where & 3);
186 
187         __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
188         v = (__raw_readl(IT8152_PCI_CFG_DATA)  >> (8 * (shift)));
189 
190         *value = v;
191 
192         return PCIBIOS_SUCCESSFUL;
193 }
194 
195 static int it8152_pci_write_config(struct pci_bus *bus,
196                                    unsigned int devfn, int where,
197                                    int size, u32 value)
198 {
199         unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
200         u32 v, vtemp, mask = 0;
201         int shift;
202 
203         if (size == 1)
204                 mask = 0xff;
205         if (size == 2)
206                 mask = 0xffff;
207 
208         shift = (where & 3);
209 
210         __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
211         vtemp = __raw_readl(IT8152_PCI_CFG_DATA);
212 
213         if (mask)
214                 vtemp &= ~(mask << (8 * shift));
215         else
216                 vtemp = 0;
217 
218         v = (value << (8 * shift));
219         __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
220         __raw_writel((v | vtemp), IT8152_PCI_CFG_DATA);
221 
222         return PCIBIOS_SUCCESSFUL;
223 }
224 
225 struct pci_ops it8152_ops = {
226         .read = it8152_pci_read_config,
227         .write = it8152_pci_write_config,
228 };
229 
230 static struct resource it8152_io = {
231         .name   = "IT8152 PCI I/O region",
232         .flags  = IORESOURCE_IO,
233 };
234 
235 static struct resource it8152_mem = {
236         .name   = "IT8152 PCI memory region",
237         .start  = 0x10000000,
238         .end    = 0x13e00000,
239         .flags  = IORESOURCE_MEM,
240 };
241 
242 /*
243  * The following functions are needed for DMA bouncing.
244  * ITE8152 chip can address up to 64MByte, so all the devices
245  * connected to ITE8152 (PCI and USB) should have limited DMA window
246  */
247 static int it8152_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
248 {
249         dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
250                 __func__, dma_addr, size);
251         return (dma_addr + size - PHYS_OFFSET) >= SZ_64M;
252 }
253 
254 /*
255  * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
256  * other devices.
257  */
258 static int it8152_pci_platform_notify(struct device *dev)
259 {
260         if (dev_is_pci(dev)) {
261                 if (dev->dma_mask)
262                         *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
263                 dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
264                 dmabounce_register_dev(dev, 2048, 4096, it8152_needs_bounce);
265         }
266         return 0;
267 }
268 
269 static int it8152_pci_platform_notify_remove(struct device *dev)
270 {
271         if (dev_is_pci(dev))
272                 dmabounce_unregister_dev(dev);
273 
274         return 0;
275 }
276 
277 int dma_set_coherent_mask(struct device *dev, u64 mask)
278 {
279         if (mask >= PHYS_OFFSET + SZ_64M - 1)
280                 return 0;
281 
282         return -EIO;
283 }
284 
285 int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
286 {
287         /*
288          * FIXME: use pci_ioremap_io to remap the IO space here and
289          * move over to the generic io.h implementation.
290          * This requires solving the same problem for PXA PCMCIA
291          * support.
292          */
293         it8152_io.start = (unsigned long)IT8152_IO_BASE + 0x12000;
294         it8152_io.end   = (unsigned long)IT8152_IO_BASE + 0x12000 + 0x100000;
295 
296         sys->mem_offset = 0x10000000;
297         sys->io_offset  = (unsigned long)IT8152_IO_BASE;
298 
299         if (request_resource(&ioport_resource, &it8152_io)) {
300                 printk(KERN_ERR "PCI: unable to allocate IO region\n");
301                 goto err0;
302         }
303         if (request_resource(&iomem_resource, &it8152_mem)) {
304                 printk(KERN_ERR "PCI: unable to allocate memory region\n");
305                 goto err1;
306         }
307 
308         pci_add_resource_offset(&sys->resources, &it8152_io, sys->io_offset);
309         pci_add_resource_offset(&sys->resources, &it8152_mem, sys->mem_offset);
310 
311         if (platform_notify || platform_notify_remove) {
312                 printk(KERN_ERR "PCI: Can't use platform_notify\n");
313                 goto err2;
314         }
315 
316         platform_notify = it8152_pci_platform_notify;
317         platform_notify_remove = it8152_pci_platform_notify_remove;
318 
319         return 1;
320 
321 err2:
322         release_resource(&it8152_io);
323 err1:
324         release_resource(&it8152_mem);
325 err0:
326         return -EBUSY;
327 }
328 
329 /* ITE bridge requires setting latency timer to avoid early bus access
330    termination by PCI bus master devices
331 */
332 void pcibios_set_master(struct pci_dev *dev)
333 {
334         u8 lat;
335 
336         /* no need to update on-chip OHCI controller */
337         if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
338             (dev->device == PCI_DEVICE_ID_ITE_8152) &&
339             ((dev->class >> 8) == PCI_CLASS_SERIAL_USB))
340                 return;
341 
342         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
343         if (lat < 16)
344                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
345         else if (lat > pcibios_max_latency)
346                 lat = pcibios_max_latency;
347         else
348                 return;
349         printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
350                pci_name(dev), lat);
351         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
352 }
353 
354 
355 EXPORT_SYMBOL(dma_set_coherent_mask);
356 

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