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TOMOYO Linux Cross Reference
Linux/arch/arm/kernel/perf_event.c

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  1 #undef DEBUG
  2 
  3 /*
  4  * ARM performance counter support.
  5  *
  6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
  7  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
  8  *
  9  * This code is based on the sparc64 perf event code, which is in turn based
 10  * on the x86 code. Callchain code is based on the ARM OProfile backtrace
 11  * code.
 12  */
 13 #define pr_fmt(fmt) "hw perfevents: " fmt
 14 
 15 #include <linux/bitmap.h>
 16 #include <linux/interrupt.h>
 17 #include <linux/kernel.h>
 18 #include <linux/export.h>
 19 #include <linux/perf_event.h>
 20 #include <linux/platform_device.h>
 21 #include <linux/spinlock.h>
 22 #include <linux/uaccess.h>
 23 
 24 #include <asm/cputype.h>
 25 #include <asm/irq.h>
 26 #include <asm/irq_regs.h>
 27 #include <asm/pmu.h>
 28 #include <asm/stacktrace.h>
 29 
 30 /*
 31  * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
 32  * another platform that supports more, we need to increase this to be the
 33  * largest of all platforms.
 34  *
 35  * ARMv7 supports up to 32 events:
 36  *  cycle counter CCNT + 31 events counters CNT0..30.
 37  *  Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
 38  */
 39 #define ARMPMU_MAX_HWEVENTS             32
 40 
 41 static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
 42 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
 43 static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
 44 
 45 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
 46 
 47 /* Set at runtime when we know what CPU type we are. */
 48 static struct arm_pmu *cpu_pmu;
 49 
 50 enum arm_perf_pmu_ids
 51 armpmu_get_pmu_id(void)
 52 {
 53         int id = -ENODEV;
 54 
 55         if (cpu_pmu != NULL)
 56                 id = cpu_pmu->id;
 57 
 58         return id;
 59 }
 60 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
 61 
 62 int
 63 armpmu_get_max_events(void)
 64 {
 65         int max_events = 0;
 66 
 67         if (cpu_pmu != NULL)
 68                 max_events = cpu_pmu->num_events;
 69 
 70         return max_events;
 71 }
 72 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
 73 
 74 int perf_num_counters(void)
 75 {
 76         return armpmu_get_max_events();
 77 }
 78 EXPORT_SYMBOL_GPL(perf_num_counters);
 79 
 80 #define HW_OP_UNSUPPORTED               0xFFFF
 81 
 82 #define C(_x) \
 83         PERF_COUNT_HW_CACHE_##_x
 84 
 85 #define CACHE_OP_UNSUPPORTED            0xFFFF
 86 
 87 static int
 88 armpmu_map_cache_event(const unsigned (*cache_map)
 89                                       [PERF_COUNT_HW_CACHE_MAX]
 90                                       [PERF_COUNT_HW_CACHE_OP_MAX]
 91                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
 92                        u64 config)
 93 {
 94         unsigned int cache_type, cache_op, cache_result, ret;
 95 
 96         cache_type = (config >>  0) & 0xff;
 97         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 98                 return -EINVAL;
 99 
100         cache_op = (config >>  8) & 0xff;
101         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
102                 return -EINVAL;
103 
104         cache_result = (config >> 16) & 0xff;
105         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
106                 return -EINVAL;
107 
108         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
109 
110         if (ret == CACHE_OP_UNSUPPORTED)
111                 return -ENOENT;
112 
113         return ret;
114 }
115 
116 static int
117 armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
118 {
119         int mapping;
120 
121         if (config >= PERF_COUNT_HW_MAX)
122                 return -ENOENT;
123 
124         mapping = (*event_map)[config];
125         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
126 }
127 
128 static int
129 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
130 {
131         return (int)(config & raw_event_mask);
132 }
133 
134 static int map_cpu_event(struct perf_event *event,
135                          const unsigned (*event_map)[PERF_COUNT_HW_MAX],
136                          const unsigned (*cache_map)
137                                         [PERF_COUNT_HW_CACHE_MAX]
138                                         [PERF_COUNT_HW_CACHE_OP_MAX]
139                                         [PERF_COUNT_HW_CACHE_RESULT_MAX],
140                          u32 raw_event_mask)
141 {
142         u64 config = event->attr.config;
143 
144         switch (event->attr.type) {
145         case PERF_TYPE_HARDWARE:
146                 return armpmu_map_event(event_map, config);
147         case PERF_TYPE_HW_CACHE:
148                 return armpmu_map_cache_event(cache_map, config);
149         case PERF_TYPE_RAW:
150                 return armpmu_map_raw_event(raw_event_mask, config);
151         }
152 
153         return -ENOENT;
154 }
155 
156 int
157 armpmu_event_set_period(struct perf_event *event,
158                         struct hw_perf_event *hwc,
159                         int idx)
160 {
161         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
162         s64 left = local64_read(&hwc->period_left);
163         s64 period = hwc->sample_period;
164         int ret = 0;
165 
166         if (unlikely(left <= -period)) {
167                 left = period;
168                 local64_set(&hwc->period_left, left);
169                 hwc->last_period = period;
170                 ret = 1;
171         }
172 
173         if (unlikely(left <= 0)) {
174                 left += period;
175                 local64_set(&hwc->period_left, left);
176                 hwc->last_period = period;
177                 ret = 1;
178         }
179 
180         if (left > (s64)armpmu->max_period)
181                 left = armpmu->max_period;
182 
183         local64_set(&hwc->prev_count, (u64)-left);
184 
185         armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
186 
187         perf_event_update_userpage(event);
188 
189         return ret;
190 }
191 
192 u64
193 armpmu_event_update(struct perf_event *event,
194                     struct hw_perf_event *hwc,
195                     int idx)
196 {
197         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
198         u64 delta, prev_raw_count, new_raw_count;
199 
200 again:
201         prev_raw_count = local64_read(&hwc->prev_count);
202         new_raw_count = armpmu->read_counter(idx);
203 
204         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
205                              new_raw_count) != prev_raw_count)
206                 goto again;
207 
208         delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
209 
210         local64_add(delta, &event->count);
211         local64_sub(delta, &hwc->period_left);
212 
213         return new_raw_count;
214 }
215 
216 static void
217 armpmu_read(struct perf_event *event)
218 {
219         struct hw_perf_event *hwc = &event->hw;
220 
221         /* Don't read disabled counters! */
222         if (hwc->idx < 0)
223                 return;
224 
225         armpmu_event_update(event, hwc, hwc->idx);
226 }
227 
228 static void
229 armpmu_stop(struct perf_event *event, int flags)
230 {
231         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
232         struct hw_perf_event *hwc = &event->hw;
233 
234         /*
235          * ARM pmu always has to update the counter, so ignore
236          * PERF_EF_UPDATE, see comments in armpmu_start().
237          */
238         if (!(hwc->state & PERF_HES_STOPPED)) {
239                 armpmu->disable(hwc, hwc->idx);
240                 barrier(); /* why? */
241                 armpmu_event_update(event, hwc, hwc->idx);
242                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
243         }
244 }
245 
246 static void
247 armpmu_start(struct perf_event *event, int flags)
248 {
249         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
250         struct hw_perf_event *hwc = &event->hw;
251 
252         /*
253          * ARM pmu always has to reprogram the period, so ignore
254          * PERF_EF_RELOAD, see the comment below.
255          */
256         if (flags & PERF_EF_RELOAD)
257                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
258 
259         hwc->state = 0;
260         /*
261          * Set the period again. Some counters can't be stopped, so when we
262          * were stopped we simply disabled the IRQ source and the counter
263          * may have been left counting. If we don't do this step then we may
264          * get an interrupt too soon or *way* too late if the overflow has
265          * happened since disabling.
266          */
267         armpmu_event_set_period(event, hwc, hwc->idx);
268         armpmu->enable(hwc, hwc->idx);
269 }
270 
271 static void
272 armpmu_del(struct perf_event *event, int flags)
273 {
274         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
275         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
276         struct hw_perf_event *hwc = &event->hw;
277         int idx = hwc->idx;
278 
279         WARN_ON(idx < 0);
280 
281         armpmu_stop(event, PERF_EF_UPDATE);
282         hw_events->events[idx] = NULL;
283         clear_bit(idx, hw_events->used_mask);
284 
285         perf_event_update_userpage(event);
286 }
287 
288 static int
289 armpmu_add(struct perf_event *event, int flags)
290 {
291         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
292         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
293         struct hw_perf_event *hwc = &event->hw;
294         int idx;
295         int err = 0;
296 
297         perf_pmu_disable(event->pmu);
298 
299         /* If we don't have a space for the counter then finish early. */
300         idx = armpmu->get_event_idx(hw_events, hwc);
301         if (idx < 0) {
302                 err = idx;
303                 goto out;
304         }
305 
306         /*
307          * If there is an event in the counter we are going to use then make
308          * sure it is disabled.
309          */
310         event->hw.idx = idx;
311         armpmu->disable(hwc, idx);
312         hw_events->events[idx] = event;
313 
314         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
315         if (flags & PERF_EF_START)
316                 armpmu_start(event, PERF_EF_RELOAD);
317 
318         /* Propagate our changes to the userspace mapping. */
319         perf_event_update_userpage(event);
320 
321 out:
322         perf_pmu_enable(event->pmu);
323         return err;
324 }
325 
326 static int
327 validate_event(struct pmu_hw_events *hw_events,
328                struct perf_event *event)
329 {
330         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
331         struct hw_perf_event fake_event = event->hw;
332         struct pmu *leader_pmu = event->group_leader->pmu;
333 
334         if (is_software_event(event))
335                 return 1;
336 
337         if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF)
338                 return 1;
339 
340         if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
341                 return 1;
342 
343         return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
344 }
345 
346 static int
347 validate_group(struct perf_event *event)
348 {
349         struct perf_event *sibling, *leader = event->group_leader;
350         struct pmu_hw_events fake_pmu;
351         DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
352 
353         /*
354          * Initialise the fake PMU. We only need to populate the
355          * used_mask for the purposes of validation.
356          */
357         memset(fake_used_mask, 0, sizeof(fake_used_mask));
358         fake_pmu.used_mask = fake_used_mask;
359 
360         if (!validate_event(&fake_pmu, leader))
361                 return -EINVAL;
362 
363         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
364                 if (!validate_event(&fake_pmu, sibling))
365                         return -EINVAL;
366         }
367 
368         if (!validate_event(&fake_pmu, event))
369                 return -EINVAL;
370 
371         return 0;
372 }
373 
374 static irqreturn_t armpmu_platform_irq(int irq, void *dev)
375 {
376         struct arm_pmu *armpmu = (struct arm_pmu *) dev;
377         struct platform_device *plat_device = armpmu->plat_device;
378         struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
379 
380         return plat->handle_irq(irq, dev, armpmu->handle_irq);
381 }
382 
383 static void
384 armpmu_release_hardware(struct arm_pmu *armpmu)
385 {
386         int i, irq, irqs;
387         struct platform_device *pmu_device = armpmu->plat_device;
388 
389         irqs = min(pmu_device->num_resources, num_possible_cpus());
390 
391         for (i = 0; i < irqs; ++i) {
392                 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
393                         continue;
394                 irq = platform_get_irq(pmu_device, i);
395                 if (irq >= 0)
396                         free_irq(irq, armpmu);
397         }
398 
399         release_pmu(armpmu->type);
400 }
401 
402 static int
403 armpmu_reserve_hardware(struct arm_pmu *armpmu)
404 {
405         struct arm_pmu_platdata *plat;
406         irq_handler_t handle_irq;
407         int i, err, irq, irqs;
408         struct platform_device *pmu_device = armpmu->plat_device;
409 
410         if (!pmu_device)
411                 return -ENODEV;
412 
413         err = reserve_pmu(armpmu->type);
414         if (err) {
415                 pr_warning("unable to reserve pmu\n");
416                 return err;
417         }
418 
419         plat = dev_get_platdata(&pmu_device->dev);
420         if (plat && plat->handle_irq)
421                 handle_irq = armpmu_platform_irq;
422         else
423                 handle_irq = armpmu->handle_irq;
424 
425         irqs = min(pmu_device->num_resources, num_possible_cpus());
426         if (irqs < 1) {
427                 pr_err("no irqs for PMUs defined\n");
428                 return -ENODEV;
429         }
430 
431         for (i = 0; i < irqs; ++i) {
432                 err = 0;
433                 irq = platform_get_irq(pmu_device, i);
434                 if (irq < 0)
435                         continue;
436 
437                 /*
438                  * If we have a single PMU interrupt that we can't shift,
439                  * assume that we're running on a uniprocessor machine and
440                  * continue. Otherwise, continue without this interrupt.
441                  */
442                 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
443                         pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
444                                     irq, i);
445                         continue;
446                 }
447 
448                 err = request_irq(irq, handle_irq,
449                                   IRQF_DISABLED | IRQF_NOBALANCING,
450                                   "arm-pmu", armpmu);
451                 if (err) {
452                         pr_err("unable to request IRQ%d for ARM PMU counters\n",
453                                 irq);
454                         armpmu_release_hardware(armpmu);
455                         return err;
456                 }
457 
458                 cpumask_set_cpu(i, &armpmu->active_irqs);
459         }
460 
461         return 0;
462 }
463 
464 static void
465 hw_perf_event_destroy(struct perf_event *event)
466 {
467         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
468         atomic_t *active_events  = &armpmu->active_events;
469         struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
470 
471         if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
472                 armpmu_release_hardware(armpmu);
473                 mutex_unlock(pmu_reserve_mutex);
474         }
475 }
476 
477 static int
478 event_requires_mode_exclusion(struct perf_event_attr *attr)
479 {
480         return attr->exclude_idle || attr->exclude_user ||
481                attr->exclude_kernel || attr->exclude_hv;
482 }
483 
484 static int
485 __hw_perf_event_init(struct perf_event *event)
486 {
487         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
488         struct hw_perf_event *hwc = &event->hw;
489         int mapping, err;
490 
491         mapping = armpmu->map_event(event);
492 
493         if (mapping < 0) {
494                 pr_debug("event %x:%llx not supported\n", event->attr.type,
495                          event->attr.config);
496                 return mapping;
497         }
498 
499         /*
500          * We don't assign an index until we actually place the event onto
501          * hardware. Use -1 to signify that we haven't decided where to put it
502          * yet. For SMP systems, each core has it's own PMU so we can't do any
503          * clever allocation or constraints checking at this point.
504          */
505         hwc->idx                = -1;
506         hwc->config_base        = 0;
507         hwc->config             = 0;
508         hwc->event_base         = 0;
509 
510         /*
511          * Check whether we need to exclude the counter from certain modes.
512          */
513         if ((!armpmu->set_event_filter ||
514              armpmu->set_event_filter(hwc, &event->attr)) &&
515              event_requires_mode_exclusion(&event->attr)) {
516                 pr_debug("ARM performance counters do not support "
517                          "mode exclusion\n");
518                 return -EPERM;
519         }
520 
521         /*
522          * Store the event encoding into the config_base field.
523          */
524         hwc->config_base            |= (unsigned long)mapping;
525 
526         if (!hwc->sample_period) {
527                 /*
528                  * For non-sampling runs, limit the sample_period to half
529                  * of the counter width. That way, the new counter value
530                  * is far less likely to overtake the previous one unless
531                  * you have some serious IRQ latency issues.
532                  */
533                 hwc->sample_period  = armpmu->max_period >> 1;
534                 hwc->last_period    = hwc->sample_period;
535                 local64_set(&hwc->period_left, hwc->sample_period);
536         }
537 
538         err = 0;
539         if (event->group_leader != event) {
540                 err = validate_group(event);
541                 if (err)
542                         return -EINVAL;
543         }
544 
545         return err;
546 }
547 
548 static int armpmu_event_init(struct perf_event *event)
549 {
550         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
551         int err = 0;
552         atomic_t *active_events = &armpmu->active_events;
553 
554         if (armpmu->map_event(event) == -ENOENT)
555                 return -ENOENT;
556 
557         event->destroy = hw_perf_event_destroy;
558 
559         if (!atomic_inc_not_zero(active_events)) {
560                 mutex_lock(&armpmu->reserve_mutex);
561                 if (atomic_read(active_events) == 0)
562                         err = armpmu_reserve_hardware(armpmu);
563 
564                 if (!err)
565                         atomic_inc(active_events);
566                 mutex_unlock(&armpmu->reserve_mutex);
567         }
568 
569         if (err)
570                 return err;
571 
572         err = __hw_perf_event_init(event);
573         if (err)
574                 hw_perf_event_destroy(event);
575 
576         return err;
577 }
578 
579 static void armpmu_enable(struct pmu *pmu)
580 {
581         struct arm_pmu *armpmu = to_arm_pmu(pmu);
582         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
583         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
584 
585         if (enabled)
586                 armpmu->start();
587 }
588 
589 static void armpmu_disable(struct pmu *pmu)
590 {
591         struct arm_pmu *armpmu = to_arm_pmu(pmu);
592         armpmu->stop();
593 }
594 
595 static void __init armpmu_init(struct arm_pmu *armpmu)
596 {
597         atomic_set(&armpmu->active_events, 0);
598         mutex_init(&armpmu->reserve_mutex);
599 
600         armpmu->pmu = (struct pmu) {
601                 .pmu_enable     = armpmu_enable,
602                 .pmu_disable    = armpmu_disable,
603                 .event_init     = armpmu_event_init,
604                 .add            = armpmu_add,
605                 .del            = armpmu_del,
606                 .start          = armpmu_start,
607                 .stop           = armpmu_stop,
608                 .read           = armpmu_read,
609         };
610 }
611 
612 int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
613 {
614         armpmu_init(armpmu);
615         return perf_pmu_register(&armpmu->pmu, name, type);
616 }
617 
618 /* Include the PMU-specific implementations. */
619 #include "perf_event_xscale.c"
620 #include "perf_event_v6.c"
621 #include "perf_event_v7.c"
622 
623 /*
624  * Ensure the PMU has sane values out of reset.
625  * This requires SMP to be available, so exists as a separate initcall.
626  */
627 static int __init
628 cpu_pmu_reset(void)
629 {
630         if (cpu_pmu && cpu_pmu->reset)
631                 return on_each_cpu(cpu_pmu->reset, NULL, 1);
632         return 0;
633 }
634 arch_initcall(cpu_pmu_reset);
635 
636 /*
637  * PMU platform driver and devicetree bindings.
638  */
639 static struct of_device_id armpmu_of_device_ids[] = {
640         {.compatible = "arm,cortex-a9-pmu"},
641         {.compatible = "arm,cortex-a8-pmu"},
642         {.compatible = "arm,arm1136-pmu"},
643         {.compatible = "arm,arm1176-pmu"},
644         {},
645 };
646 
647 static struct platform_device_id armpmu_plat_device_ids[] = {
648         {.name = "arm-pmu"},
649         {},
650 };
651 
652 static int __devinit armpmu_device_probe(struct platform_device *pdev)
653 {
654         if (!cpu_pmu)
655                 return -ENODEV;
656 
657         cpu_pmu->plat_device = pdev;
658         return 0;
659 }
660 
661 static struct platform_driver armpmu_driver = {
662         .driver         = {
663                 .name   = "arm-pmu",
664                 .of_match_table = armpmu_of_device_ids,
665         },
666         .probe          = armpmu_device_probe,
667         .id_table       = armpmu_plat_device_ids,
668 };
669 
670 static int __init register_pmu_driver(void)
671 {
672         return platform_driver_register(&armpmu_driver);
673 }
674 device_initcall(register_pmu_driver);
675 
676 static struct pmu_hw_events *armpmu_get_cpu_events(void)
677 {
678         return &__get_cpu_var(cpu_hw_events);
679 }
680 
681 static void __init cpu_pmu_init(struct arm_pmu *armpmu)
682 {
683         int cpu;
684         for_each_possible_cpu(cpu) {
685                 struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
686                 events->events = per_cpu(hw_events, cpu);
687                 events->used_mask = per_cpu(used_mask, cpu);
688                 raw_spin_lock_init(&events->pmu_lock);
689         }
690         armpmu->get_hw_events = armpmu_get_cpu_events;
691         armpmu->type = ARM_PMU_DEVICE_CPU;
692 }
693 
694 /*
695  * CPU PMU identification and registration.
696  */
697 static int __init
698 init_hw_perf_events(void)
699 {
700         unsigned long cpuid = read_cpuid_id();
701         unsigned long implementor = (cpuid & 0xFF000000) >> 24;
702         unsigned long part_number = (cpuid & 0xFFF0);
703 
704         /* ARM Ltd CPUs. */
705         if (0x41 == implementor) {
706                 switch (part_number) {
707                 case 0xB360:    /* ARM1136 */
708                 case 0xB560:    /* ARM1156 */
709                 case 0xB760:    /* ARM1176 */
710                         cpu_pmu = armv6pmu_init();
711                         break;
712                 case 0xB020:    /* ARM11mpcore */
713                         cpu_pmu = armv6mpcore_pmu_init();
714                         break;
715                 case 0xC080:    /* Cortex-A8 */
716                         cpu_pmu = armv7_a8_pmu_init();
717                         break;
718                 case 0xC090:    /* Cortex-A9 */
719                         cpu_pmu = armv7_a9_pmu_init();
720                         break;
721                 case 0xC050:    /* Cortex-A5 */
722                         cpu_pmu = armv7_a5_pmu_init();
723                         break;
724                 case 0xC0F0:    /* Cortex-A15 */
725                         cpu_pmu = armv7_a15_pmu_init();
726                         break;
727                 }
728         /* Intel CPUs [xscale]. */
729         } else if (0x69 == implementor) {
730                 part_number = (cpuid >> 13) & 0x7;
731                 switch (part_number) {
732                 case 1:
733                         cpu_pmu = xscale1pmu_init();
734                         break;
735                 case 2:
736                         cpu_pmu = xscale2pmu_init();
737                         break;
738                 }
739         }
740 
741         if (cpu_pmu) {
742                 pr_info("enabled with %s PMU driver, %d counters available\n",
743                         cpu_pmu->name, cpu_pmu->num_events);
744                 cpu_pmu_init(cpu_pmu);
745                 armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
746         } else {
747                 pr_info("no hardware support available\n");
748         }
749 
750         return 0;
751 }
752 early_initcall(init_hw_perf_events);
753 
754 /*
755  * Callchain handling code.
756  */
757 
758 /*
759  * The registers we're interested in are at the end of the variable
760  * length saved register structure. The fp points at the end of this
761  * structure so the address of this struct is:
762  * (struct frame_tail *)(xxx->fp)-1
763  *
764  * This code has been adapted from the ARM OProfile support.
765  */
766 struct frame_tail {
767         struct frame_tail __user *fp;
768         unsigned long sp;
769         unsigned long lr;
770 } __attribute__((packed));
771 
772 /*
773  * Get the return address for a single stackframe and return a pointer to the
774  * next frame tail.
775  */
776 static struct frame_tail __user *
777 user_backtrace(struct frame_tail __user *tail,
778                struct perf_callchain_entry *entry)
779 {
780         struct frame_tail buftail;
781 
782         /* Also check accessibility of one struct frame_tail beyond */
783         if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
784                 return NULL;
785         if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
786                 return NULL;
787 
788         perf_callchain_store(entry, buftail.lr);
789 
790         /*
791          * Frame pointers should strictly progress back up the stack
792          * (towards higher addresses).
793          */
794         if (tail + 1 >= buftail.fp)
795                 return NULL;
796 
797         return buftail.fp - 1;
798 }
799 
800 void
801 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
802 {
803         struct frame_tail __user *tail;
804 
805 
806         perf_callchain_store(entry, regs->ARM_pc);
807         tail = (struct frame_tail __user *)regs->ARM_fp - 1;
808 
809         while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
810                tail && !((unsigned long)tail & 0x3))
811                 tail = user_backtrace(tail, entry);
812 }
813 
814 /*
815  * Gets called by walk_stackframe() for every stackframe. This will be called
816  * whist unwinding the stackframe and is like a subroutine return so we use
817  * the PC.
818  */
819 static int
820 callchain_trace(struct stackframe *fr,
821                 void *data)
822 {
823         struct perf_callchain_entry *entry = data;
824         perf_callchain_store(entry, fr->pc);
825         return 0;
826 }
827 
828 void
829 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
830 {
831         struct stackframe fr;
832 
833         fr.fp = regs->ARM_fp;
834         fr.sp = regs->ARM_sp;
835         fr.lr = regs->ARM_lr;
836         fr.pc = regs->ARM_pc;
837         walk_stackframe(&fr, callchain_trace, entry);
838 }
839 

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