~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/arch/arm/mach-at91/at91sam926x_time.c

Version: ~ [ linux-5.19-rc3 ] ~ [ linux-5.18.5 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.48 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.123 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.199 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.248 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.284 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.319 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.302 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.9 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
  3  *
  4  * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
  5  * Revision      2005 M. Nicolas Diremdjian, ATMEL Rousset, France
  6  * Converted to ClockSource/ClockEvents by David Brownell.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License version 2 as
 10  * published by the Free Software Foundation.
 11  */
 12 #include <linux/interrupt.h>
 13 #include <linux/irq.h>
 14 #include <linux/kernel.h>
 15 #include <linux/clk.h>
 16 #include <linux/clockchips.h>
 17 #include <linux/of.h>
 18 #include <linux/of_address.h>
 19 #include <linux/of_irq.h>
 20 
 21 #include <asm/mach/time.h>
 22 
 23 #define AT91_PIT_MR             0x00                    /* Mode Register */
 24 #define         AT91_PIT_PITIEN         (1 << 25)               /* Timer Interrupt Enable */
 25 #define         AT91_PIT_PITEN          (1 << 24)               /* Timer Enabled */
 26 #define         AT91_PIT_PIV            (0xfffff)               /* Periodic Interval Value */
 27 
 28 #define AT91_PIT_SR             0x04                    /* Status Register */
 29 #define         AT91_PIT_PITS           (1 << 0)                /* Timer Status */
 30 
 31 #define AT91_PIT_PIVR           0x08                    /* Periodic Interval Value Register */
 32 #define AT91_PIT_PIIR           0x0c                    /* Periodic Interval Image Register */
 33 #define         AT91_PIT_PICNT          (0xfff << 20)           /* Interval Counter */
 34 #define         AT91_PIT_CPIV           (0xfffff)               /* Inverval Value */
 35 
 36 #define PIT_CPIV(x)     ((x) & AT91_PIT_CPIV)
 37 #define PIT_PICNT(x)    (((x) & AT91_PIT_PICNT) >> 20)
 38 
 39 static u32 pit_cycle;           /* write-once */
 40 static u32 pit_cnt;             /* access only w/system irq blocked */
 41 static void __iomem *pit_base_addr __read_mostly;
 42 
 43 static inline unsigned int pit_read(unsigned int reg_offset)
 44 {
 45         return __raw_readl(pit_base_addr + reg_offset);
 46 }
 47 
 48 static inline void pit_write(unsigned int reg_offset, unsigned long value)
 49 {
 50         __raw_writel(value, pit_base_addr + reg_offset);
 51 }
 52 
 53 /*
 54  * Clocksource:  just a monotonic counter of MCK/16 cycles.
 55  * We don't care whether or not PIT irqs are enabled.
 56  */
 57 static cycle_t read_pit_clk(struct clocksource *cs)
 58 {
 59         unsigned long flags;
 60         u32 elapsed;
 61         u32 t;
 62 
 63         raw_local_irq_save(flags);
 64         elapsed = pit_cnt;
 65         t = pit_read(AT91_PIT_PIIR);
 66         raw_local_irq_restore(flags);
 67 
 68         elapsed += PIT_PICNT(t) * pit_cycle;
 69         elapsed += PIT_CPIV(t);
 70         return elapsed;
 71 }
 72 
 73 static struct clocksource pit_clk = {
 74         .name           = "pit",
 75         .rating         = 175,
 76         .read           = read_pit_clk,
 77         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 78 };
 79 
 80 
 81 /*
 82  * Clockevent device:  interrupts every 1/HZ (== pit_cycles * MCK/16)
 83  */
 84 static void
 85 pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 86 {
 87         switch (mode) {
 88         case CLOCK_EVT_MODE_PERIODIC:
 89                 /* update clocksource counter */
 90                 pit_cnt += pit_cycle * PIT_PICNT(pit_read(AT91_PIT_PIVR));
 91                 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
 92                                 | AT91_PIT_PITIEN);
 93                 break;
 94         case CLOCK_EVT_MODE_ONESHOT:
 95                 BUG();
 96                 /* FALLTHROUGH */
 97         case CLOCK_EVT_MODE_SHUTDOWN:
 98         case CLOCK_EVT_MODE_UNUSED:
 99                 /* disable irq, leaving the clocksource active */
100                 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
101                 break;
102         case CLOCK_EVT_MODE_RESUME:
103                 break;
104         }
105 }
106 
107 static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
108 {
109         /* Disable timer */
110         pit_write(AT91_PIT_MR, 0);
111 }
112 
113 static void at91sam926x_pit_reset(void)
114 {
115         /* Disable timer and irqs */
116         pit_write(AT91_PIT_MR, 0);
117 
118         /* Clear any pending interrupts, wait for PIT to stop counting */
119         while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0)
120                 cpu_relax();
121 
122         /* Start PIT but don't enable IRQ */
123         pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
124 }
125 
126 static void at91sam926x_pit_resume(struct clock_event_device *cedev)
127 {
128         at91sam926x_pit_reset();
129 }
130 
131 static struct clock_event_device pit_clkevt = {
132         .name           = "pit",
133         .features       = CLOCK_EVT_FEAT_PERIODIC,
134         .shift          = 32,
135         .rating         = 100,
136         .set_mode       = pit_clkevt_mode,
137         .suspend        = at91sam926x_pit_suspend,
138         .resume         = at91sam926x_pit_resume,
139 };
140 
141 
142 /*
143  * IRQ handler for the timer.
144  */
145 static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
146 {
147         /*
148          * irqs should be disabled here, but as the irq is shared they are only
149          * guaranteed to be off if the timer irq is registered first.
150          */
151         WARN_ON_ONCE(!irqs_disabled());
152 
153         /* The PIT interrupt may be disabled, and is shared */
154         if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
155                         && (pit_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
156                 unsigned nr_ticks;
157 
158                 /* Get number of ticks performed before irq, and ack it */
159                 nr_ticks = PIT_PICNT(pit_read(AT91_PIT_PIVR));
160                 do {
161                         pit_cnt += pit_cycle;
162                         pit_clkevt.event_handler(&pit_clkevt);
163                         nr_ticks--;
164                 } while (nr_ticks);
165 
166                 return IRQ_HANDLED;
167         }
168 
169         return IRQ_NONE;
170 }
171 
172 static struct irqaction at91sam926x_pit_irq = {
173         .name           = "at91_tick",
174         .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
175         .handler        = at91sam926x_pit_interrupt,
176         .irq            = NR_IRQS_LEGACY + AT91_ID_SYS,
177 };
178 
179 #ifdef CONFIG_OF
180 static struct of_device_id pit_timer_ids[] = {
181         { .compatible = "atmel,at91sam9260-pit" },
182         { /* sentinel */ }
183 };
184 
185 static int __init of_at91sam926x_pit_init(void)
186 {
187         struct device_node      *np;
188         int                     ret;
189 
190         np = of_find_matching_node(NULL, pit_timer_ids);
191         if (!np)
192                 goto err;
193 
194         pit_base_addr = of_iomap(np, 0);
195         if (!pit_base_addr)
196                 goto node_err;
197 
198         /* Get the interrupts property */
199         ret = irq_of_parse_and_map(np, 0);
200         if (!ret) {
201                 pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
202                 goto ioremap_err;
203         }
204         at91sam926x_pit_irq.irq = ret;
205 
206         of_node_put(np);
207 
208         return 0;
209 
210 ioremap_err:
211         iounmap(pit_base_addr);
212 node_err:
213         of_node_put(np);
214 err:
215         return -EINVAL;
216 }
217 #else
218 static int __init of_at91sam926x_pit_init(void)
219 {
220         return -EINVAL;
221 }
222 #endif
223 
224 /*
225  * Set up both clocksource and clockevent support.
226  */
227 void __init at91sam926x_pit_init(void)
228 {
229         unsigned long   pit_rate;
230         unsigned        bits;
231         int             ret;
232 
233         /* For device tree enabled device: initialize here */
234         of_at91sam926x_pit_init();
235 
236         /*
237          * Use our actual MCK to figure out how many MCK/16 ticks per
238          * 1/HZ period (instead of a compile-time constant LATCH).
239          */
240         pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
241         pit_cycle = (pit_rate + HZ/2) / HZ;
242         WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
243 
244         /* Initialize and enable the timer */
245         at91sam926x_pit_reset();
246 
247         /*
248          * Register clocksource.  The high order bits of PIV are unused,
249          * so this isn't a 32-bit counter unless we get clockevent irqs.
250          */
251         bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
252         pit_clk.mask = CLOCKSOURCE_MASK(bits);
253         clocksource_register_hz(&pit_clk, pit_rate);
254 
255         /* Set up irq handler */
256         ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
257         if (ret)
258                 pr_crit("AT91: PIT: Unable to setup IRQ\n");
259 
260         /* Set up and register clockevents */
261         pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
262         pit_clkevt.cpumask = cpumask_of(0);
263         clockevents_register_device(&pit_clkevt);
264 }
265 
266 void __init at91sam926x_ioremap_pit(u32 addr)
267 {
268 #if defined(CONFIG_OF)
269         struct device_node *np =
270                 of_find_matching_node(NULL, pit_timer_ids);
271 
272         if (np) {
273                 of_node_put(np);
274                 return;
275         }
276 #endif
277         pit_base_addr = ioremap(addr, 16);
278 
279         if (!pit_base_addr)
280                 panic("Impossible to ioremap PIT\n");
281 }
282 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp