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Linux/arch/arm/mach-at91/clock.c

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  1 /*
  2  * linux/arch/arm/mach-at91/clock.c
  3  *
  4  * Copyright (C) 2005 David Brownell
  5  * Copyright (C) 2005 Ivan Kokshaysky
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  */
 12 
 13 #include <linux/module.h>
 14 #include <linux/kernel.h>
 15 #include <linux/init.h>
 16 #include <linux/fs.h>
 17 #include <linux/debugfs.h>
 18 #include <linux/seq_file.h>
 19 #include <linux/list.h>
 20 #include <linux/errno.h>
 21 #include <linux/err.h>
 22 #include <linux/spinlock.h>
 23 #include <linux/delay.h>
 24 #include <linux/clk.h>
 25 #include <linux/io.h>
 26 #include <linux/of_address.h>
 27 
 28 #include <mach/hardware.h>
 29 #include <mach/at91_pmc.h>
 30 #include <mach/cpu.h>
 31 
 32 #include <asm/proc-fns.h>
 33 
 34 #include "clock.h"
 35 #include "generic.h"
 36 
 37 void __iomem *at91_pmc_base;
 38 EXPORT_SYMBOL_GPL(at91_pmc_base);
 39 
 40 /*
 41  * There's a lot more which can be done with clocks, including cpufreq
 42  * integration, slow clock mode support (for system suspend), letting
 43  * PLLB be used at other rates (on boards that don't need USB), etc.
 44  */
 45 
 46 #define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
 47 #define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
 48 #define clk_is_peripheral(x)    ((x)->type & CLK_TYPE_PERIPHERAL)
 49 #define clk_is_sys(x)           ((x)->type & CLK_TYPE_SYSTEM)
 50 
 51 
 52 /*
 53  * Chips have some kind of clocks : group them by functionality
 54  */
 55 #define cpu_has_utmi()          (  cpu_is_at91sam9rl() \
 56                                 || cpu_is_at91sam9g45() \
 57                                 || cpu_is_at91sam9x5() \
 58                                 || cpu_is_sama5d3())
 59 
 60 #define cpu_has_1056M_plla()    (cpu_is_sama5d3())
 61 
 62 #define cpu_has_800M_plla()     (  cpu_is_at91sam9g20() \
 63                                 || cpu_is_at91sam9g45() \
 64                                 || cpu_is_at91sam9x5() \
 65                                 || cpu_is_at91sam9n12())
 66 
 67 #define cpu_has_300M_plla()     (cpu_is_at91sam9g10())
 68 
 69 #define cpu_has_240M_plla()     (cpu_is_at91sam9261() \
 70                                 || cpu_is_at91sam9263() \
 71                                 || cpu_is_at91sam9rl())
 72 
 73 #define cpu_has_210M_plla()     (cpu_is_at91sam9260())
 74 
 75 #define cpu_has_pllb()          (!(cpu_is_at91sam9rl() \
 76                                 || cpu_is_at91sam9g45() \
 77                                 || cpu_is_at91sam9x5() \
 78                                 || cpu_is_sama5d3()))
 79 
 80 #define cpu_has_upll()          (cpu_is_at91sam9g45() \
 81                                 || cpu_is_at91sam9x5() \
 82                                 || cpu_is_sama5d3())
 83 
 84 /* USB host HS & FS */
 85 #define cpu_has_uhp()           (!cpu_is_at91sam9rl())
 86 
 87 /* USB device FS only */
 88 #define cpu_has_udpfs()         (!(cpu_is_at91sam9rl() \
 89                                 || cpu_is_at91sam9g45() \
 90                                 || cpu_is_at91sam9x5() \
 91                                 || cpu_is_sama5d3()))
 92 
 93 #define cpu_has_plladiv2()      (cpu_is_at91sam9g45() \
 94                                 || cpu_is_at91sam9x5() \
 95                                 || cpu_is_at91sam9n12() \
 96                                 || cpu_is_sama5d3())
 97 
 98 #define cpu_has_mdiv3()         (cpu_is_at91sam9g45() \
 99                                 || cpu_is_at91sam9x5() \
100                                 || cpu_is_at91sam9n12() \
101                                 || cpu_is_sama5d3())
102 
103 #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
104                                 || cpu_is_at91sam9n12() \
105                                 || cpu_is_sama5d3())
106 
107 static LIST_HEAD(clocks);
108 static DEFINE_SPINLOCK(clk_lock);
109 
110 static u32 at91_pllb_usb_init;
111 
112 /*
113  * Four primary clock sources:  two crystal oscillators (32K, main), and
114  * two PLLs.  PLLA usually runs the master clock; and PLLB must run at
115  * 48 MHz (unless no USB function clocks are needed).  The main clock and
116  * both PLLs are turned off to run in "slow clock mode" (system suspend).
117  */
118 static struct clk clk32k = {
119         .name           = "clk32k",
120         .rate_hz        = AT91_SLOW_CLOCK,
121         .users          = 1,            /* always on */
122         .id             = 0,
123         .type           = CLK_TYPE_PRIMARY,
124 };
125 static struct clk main_clk = {
126         .name           = "main",
127         .pmc_mask       = AT91_PMC_MOSCS,       /* in PMC_SR */
128         .id             = 1,
129         .type           = CLK_TYPE_PRIMARY,
130 };
131 static struct clk plla = {
132         .name           = "plla",
133         .parent         = &main_clk,
134         .pmc_mask       = AT91_PMC_LOCKA,       /* in PMC_SR */
135         .id             = 2,
136         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
137 };
138 
139 static void pllb_mode(struct clk *clk, int is_on)
140 {
141         u32     value;
142 
143         if (is_on) {
144                 is_on = AT91_PMC_LOCKB;
145                 value = at91_pllb_usb_init;
146         } else
147                 value = 0;
148 
149         // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
150         at91_pmc_write(AT91_CKGR_PLLBR, value);
151 
152         do {
153                 cpu_relax();
154         } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
155 }
156 
157 static struct clk pllb = {
158         .name           = "pllb",
159         .parent         = &main_clk,
160         .pmc_mask       = AT91_PMC_LOCKB,       /* in PMC_SR */
161         .mode           = pllb_mode,
162         .id             = 3,
163         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
164 };
165 
166 static void pmc_sys_mode(struct clk *clk, int is_on)
167 {
168         if (is_on)
169                 at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
170         else
171                 at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
172 }
173 
174 static void pmc_uckr_mode(struct clk *clk, int is_on)
175 {
176         unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
177 
178         if (is_on) {
179                 is_on = AT91_PMC_LOCKU;
180                 at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
181         } else
182                 at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
183 
184         do {
185                 cpu_relax();
186         } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
187 }
188 
189 /* USB function clocks (PLLB must be 48 MHz) */
190 static struct clk udpck = {
191         .name           = "udpck",
192         .parent         = &pllb,
193         .mode           = pmc_sys_mode,
194 };
195 struct clk utmi_clk = {
196         .name           = "utmi_clk",
197         .parent         = &main_clk,
198         .pmc_mask       = AT91_PMC_UPLLEN,      /* in CKGR_UCKR */
199         .mode           = pmc_uckr_mode,
200         .type           = CLK_TYPE_PLL,
201 };
202 static struct clk uhpck = {
203         .name           = "uhpck",
204         /*.parent               = ... we choose parent at runtime */
205         .mode           = pmc_sys_mode,
206 };
207 
208 
209 /*
210  * The master clock is divided from the CPU clock (by 1-4).  It's used for
211  * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
212  * (e.g baud rate generation).  It's sourced from one of the primary clocks.
213  */
214 struct clk mck = {
215         .name           = "mck",
216         .pmc_mask       = AT91_PMC_MCKRDY,      /* in PMC_SR */
217 };
218 
219 static void pmc_periph_mode(struct clk *clk, int is_on)
220 {
221         u32 regval = 0;
222 
223         /*
224          * With sama5d3 devices, we are managing clock division so we have to
225          * use the Peripheral Control Register introduced from at91sam9x5
226          * devices.
227          */
228         if (cpu_is_sama5d3()) {
229                 regval |= AT91_PMC_PCR_CMD; /* write command */
230                 regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */
231                 regval |= AT91_PMC_PCR_DIV(clk->div);
232                 if (is_on)
233                         regval |= AT91_PMC_PCR_EN; /* enable clock */
234                 at91_pmc_write(AT91_PMC_PCR, regval);
235         } else {
236                 if (is_on)
237                         at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
238                 else
239                         at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
240         }
241 }
242 
243 static struct clk __init *at91_css_to_clk(unsigned long css)
244 {
245         switch (css) {
246                 case AT91_PMC_CSS_SLOW:
247                         return &clk32k;
248                 case AT91_PMC_CSS_MAIN:
249                         return &main_clk;
250                 case AT91_PMC_CSS_PLLA:
251                         return &plla;
252                 case AT91_PMC_CSS_PLLB:
253                         if (cpu_has_upll())
254                                 /* CSS_PLLB == CSS_UPLL */
255                                 return &utmi_clk;
256                         else if (cpu_has_pllb())
257                                 return &pllb;
258                         break;
259                 /* alternate PMC: can use master clock */
260                 case AT91_PMC_CSS_MASTER:
261                         return &mck;
262         }
263 
264         return NULL;
265 }
266 
267 static int pmc_prescaler_divider(u32 reg)
268 {
269         if (cpu_has_alt_prescaler()) {
270                 return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
271         } else {
272                 return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
273         }
274 }
275 
276 static void __clk_enable(struct clk *clk)
277 {
278         if (clk->parent)
279                 __clk_enable(clk->parent);
280         if (clk->users++ == 0 && clk->mode)
281                 clk->mode(clk, 1);
282 }
283 
284 int clk_enable(struct clk *clk)
285 {
286         unsigned long   flags;
287 
288         spin_lock_irqsave(&clk_lock, flags);
289         __clk_enable(clk);
290         spin_unlock_irqrestore(&clk_lock, flags);
291         return 0;
292 }
293 EXPORT_SYMBOL(clk_enable);
294 
295 static void __clk_disable(struct clk *clk)
296 {
297         BUG_ON(clk->users == 0);
298         if (--clk->users == 0 && clk->mode)
299                 clk->mode(clk, 0);
300         if (clk->parent)
301                 __clk_disable(clk->parent);
302 }
303 
304 void clk_disable(struct clk *clk)
305 {
306         unsigned long   flags;
307 
308         spin_lock_irqsave(&clk_lock, flags);
309         __clk_disable(clk);
310         spin_unlock_irqrestore(&clk_lock, flags);
311 }
312 EXPORT_SYMBOL(clk_disable);
313 
314 unsigned long clk_get_rate(struct clk *clk)
315 {
316         unsigned long   flags;
317         unsigned long   rate;
318 
319         spin_lock_irqsave(&clk_lock, flags);
320         for (;;) {
321                 rate = clk->rate_hz;
322                 if (rate || !clk->parent)
323                         break;
324                 clk = clk->parent;
325         }
326         spin_unlock_irqrestore(&clk_lock, flags);
327         return rate;
328 }
329 EXPORT_SYMBOL(clk_get_rate);
330 
331 /*------------------------------------------------------------------------*/
332 
333 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
334 
335 /*
336  * For now, only the programmable clocks support reparenting (MCK could
337  * do this too, with care) or rate changing (the PLLs could do this too,
338  * ditto MCK but that's more for cpufreq).  Drivers may reparent to get
339  * a better rate match; we don't.
340  */
341 
342 long clk_round_rate(struct clk *clk, unsigned long rate)
343 {
344         unsigned long   flags;
345         unsigned        prescale;
346         unsigned long   actual;
347         unsigned long   prev = ULONG_MAX;
348 
349         if (!clk_is_programmable(clk))
350                 return -EINVAL;
351         spin_lock_irqsave(&clk_lock, flags);
352 
353         actual = clk->parent->rate_hz;
354         for (prescale = 0; prescale < 7; prescale++) {
355                 if (actual > rate)
356                         prev = actual;
357 
358                 if (actual && actual <= rate) {
359                         if ((prev - rate) < (rate - actual)) {
360                                 actual = prev;
361                                 prescale--;
362                         }
363                         break;
364                 }
365                 actual >>= 1;
366         }
367 
368         spin_unlock_irqrestore(&clk_lock, flags);
369         return (prescale < 7) ? actual : -ENOENT;
370 }
371 EXPORT_SYMBOL(clk_round_rate);
372 
373 int clk_set_rate(struct clk *clk, unsigned long rate)
374 {
375         unsigned long   flags;
376         unsigned        prescale;
377         unsigned long   prescale_offset, css_mask;
378         unsigned long   actual;
379 
380         if (!clk_is_programmable(clk))
381                 return -EINVAL;
382         if (clk->users)
383                 return -EBUSY;
384 
385         if (cpu_has_alt_prescaler()) {
386                 prescale_offset = PMC_ALT_PRES_OFFSET;
387                 css_mask = AT91_PMC_ALT_PCKR_CSS;
388         } else {
389                 prescale_offset = PMC_PRES_OFFSET;
390                 css_mask = AT91_PMC_CSS;
391         }
392 
393         spin_lock_irqsave(&clk_lock, flags);
394 
395         actual = clk->parent->rate_hz;
396         for (prescale = 0; prescale < 7; prescale++) {
397                 if (actual && actual <= rate) {
398                         u32     pckr;
399 
400                         pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
401                         pckr &= css_mask;       /* keep clock selection */
402                         pckr |= prescale << prescale_offset;
403                         at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
404                         clk->rate_hz = actual;
405                         break;
406                 }
407                 actual >>= 1;
408         }
409 
410         spin_unlock_irqrestore(&clk_lock, flags);
411         return (prescale < 7) ? actual : -ENOENT;
412 }
413 EXPORT_SYMBOL(clk_set_rate);
414 
415 struct clk *clk_get_parent(struct clk *clk)
416 {
417         return clk->parent;
418 }
419 EXPORT_SYMBOL(clk_get_parent);
420 
421 int clk_set_parent(struct clk *clk, struct clk *parent)
422 {
423         unsigned long   flags;
424 
425         if (clk->users)
426                 return -EBUSY;
427         if (!clk_is_primary(parent) || !clk_is_programmable(clk))
428                 return -EINVAL;
429 
430         if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
431                 return -EINVAL;
432 
433         spin_lock_irqsave(&clk_lock, flags);
434 
435         clk->rate_hz = parent->rate_hz;
436         clk->parent = parent;
437         at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
438 
439         spin_unlock_irqrestore(&clk_lock, flags);
440         return 0;
441 }
442 EXPORT_SYMBOL(clk_set_parent);
443 
444 /* establish PCK0..PCKN parentage and rate */
445 static void __init init_programmable_clock(struct clk *clk)
446 {
447         struct clk      *parent;
448         u32             pckr;
449         unsigned int    css_mask;
450 
451         if (cpu_has_alt_prescaler())
452                 css_mask = AT91_PMC_ALT_PCKR_CSS;
453         else
454                 css_mask = AT91_PMC_CSS;
455 
456         pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
457         parent = at91_css_to_clk(pckr & css_mask);
458         clk->parent = parent;
459         clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
460 }
461 
462 #endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
463 
464 /*------------------------------------------------------------------------*/
465 
466 #ifdef CONFIG_DEBUG_FS
467 
468 static int at91_clk_show(struct seq_file *s, void *unused)
469 {
470         u32             scsr, pcsr, pcsr1 = 0, uckr = 0, sr;
471         struct clk      *clk;
472 
473         scsr = at91_pmc_read(AT91_PMC_SCSR);
474         pcsr = at91_pmc_read(AT91_PMC_PCSR);
475         if (cpu_is_sama5d3())
476                 pcsr1 = at91_pmc_read(AT91_PMC_PCSR1);
477         sr = at91_pmc_read(AT91_PMC_SR);
478         seq_printf(s, "SCSR = %8x\n", scsr);
479         seq_printf(s, "PCSR = %8x\n", pcsr);
480         if (cpu_is_sama5d3())
481                 seq_printf(s, "PCSR1 = %8x\n", pcsr1);
482         seq_printf(s, "MOR  = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
483         seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
484         seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
485         if (cpu_has_pllb())
486                 seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
487         if (cpu_has_utmi()) {
488                 uckr = at91_pmc_read(AT91_CKGR_UCKR);
489                 seq_printf(s, "UCKR = %8x\n", uckr);
490         }
491         seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
492         if (cpu_has_upll() || cpu_is_at91sam9n12())
493                 seq_printf(s, "USB  = %8x\n", at91_pmc_read(AT91_PMC_USB));
494         seq_printf(s, "SR   = %8x\n", sr);
495 
496         seq_printf(s, "\n");
497 
498         list_for_each_entry(clk, &clocks, node) {
499                 char    *state;
500 
501                 if (clk->mode == pmc_sys_mode) {
502                         state = (scsr & clk->pmc_mask) ? "on" : "off";
503                 } else if (clk->mode == pmc_periph_mode) {
504                         if (cpu_is_sama5d3()) {
505                                 u32 pmc_mask = 1 << (clk->pid % 32);
506 
507                                 if (clk->pid > 31)
508                                         state = (pcsr1 & pmc_mask) ? "on" : "off";
509                                 else
510                                         state = (pcsr & pmc_mask) ? "on" : "off";
511                         } else {
512                                 state = (pcsr & clk->pmc_mask) ? "on" : "off";
513                         }
514                 } else if (clk->mode == pmc_uckr_mode) {
515                         state = (uckr & clk->pmc_mask) ? "on" : "off";
516                 } else if (clk->pmc_mask) {
517                         state = (sr & clk->pmc_mask) ? "on" : "off";
518                 } else if (clk == &clk32k || clk == &main_clk) {
519                         state = "on";
520                 } else {
521                         state = "";
522                 }
523 
524                 seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n",
525                         clk->name, clk->users, state, clk_get_rate(clk),
526                         clk->parent ? clk->parent->name : "");
527         }
528         return 0;
529 }
530 
531 static int at91_clk_open(struct inode *inode, struct file *file)
532 {
533         return single_open(file, at91_clk_show, NULL);
534 }
535 
536 static const struct file_operations at91_clk_operations = {
537         .open           = at91_clk_open,
538         .read           = seq_read,
539         .llseek         = seq_lseek,
540         .release        = single_release,
541 };
542 
543 static int __init at91_clk_debugfs_init(void)
544 {
545         /* /sys/kernel/debug/at91_clk */
546         (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
547 
548         return 0;
549 }
550 postcore_initcall(at91_clk_debugfs_init);
551 
552 #endif
553 
554 /*------------------------------------------------------------------------*/
555 
556 /* Register a new clock */
557 static void __init at91_clk_add(struct clk *clk)
558 {
559         list_add_tail(&clk->node, &clocks);
560 
561         clk->cl.con_id = clk->name;
562         clk->cl.clk = clk;
563         clkdev_add(&clk->cl);
564 }
565 
566 int __init clk_register(struct clk *clk)
567 {
568         if (clk_is_peripheral(clk)) {
569                 if (!clk->parent)
570                         clk->parent = &mck;
571                 if (cpu_is_sama5d3())
572                         clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz,
573                                                     1 << clk->div);
574                 clk->mode = pmc_periph_mode;
575         }
576         else if (clk_is_sys(clk)) {
577                 clk->parent = &mck;
578                 clk->mode = pmc_sys_mode;
579         }
580 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
581         else if (clk_is_programmable(clk)) {
582                 clk->mode = pmc_sys_mode;
583                 init_programmable_clock(clk);
584         }
585 #endif
586 
587         at91_clk_add(clk);
588 
589         return 0;
590 }
591 
592 /*------------------------------------------------------------------------*/
593 
594 static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
595 {
596         unsigned mul, div;
597 
598         div = reg & 0xff;
599         if (cpu_is_sama5d3())
600                 mul = AT91_PMC3_MUL_GET(reg);
601         else
602                 mul = AT91_PMC_MUL_GET(reg);
603 
604         if (div && mul) {
605                 freq /= div;
606                 freq *= mul + 1;
607         } else
608                 freq = 0;
609 
610         return freq;
611 }
612 
613 static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
614 {
615         if (pll == &pllb && (reg & AT91_PMC_USB96M))
616                 return freq / 2;
617         else if (pll == &utmi_clk || cpu_is_at91sam9n12())
618                 return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
619         else
620                 return freq;
621 }
622 
623 static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
624 {
625         unsigned i, div = 0, mul = 0, diff = 1 << 30;
626         unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
627 
628         /* PLL output max 240 MHz (or 180 MHz per errata) */
629         if (out_freq > 240000000)
630                 goto fail;
631 
632         for (i = 1; i < 256; i++) {
633                 int diff1;
634                 unsigned input, mul1;
635 
636                 /*
637                  * PLL input between 1MHz and 32MHz per spec, but lower
638                  * frequences seem necessary in some cases so allow 100K.
639                  * Warning: some newer products need 2MHz min.
640                  */
641                 input = main_freq / i;
642                 if (cpu_is_at91sam9g20() && input < 2000000)
643                         continue;
644                 if (input < 100000)
645                         continue;
646                 if (input > 32000000)
647                         continue;
648 
649                 mul1 = out_freq / input;
650                 if (cpu_is_at91sam9g20() && mul > 63)
651                         continue;
652                 if (mul1 > 2048)
653                         continue;
654                 if (mul1 < 2)
655                         goto fail;
656 
657                 diff1 = out_freq - input * mul1;
658                 if (diff1 < 0)
659                         diff1 = -diff1;
660                 if (diff > diff1) {
661                         diff = diff1;
662                         div = i;
663                         mul = mul1;
664                         if (diff == 0)
665                                 break;
666                 }
667         }
668         if (i == 256 && diff > (out_freq >> 5))
669                 goto fail;
670         return ret | ((mul - 1) << 16) | div;
671 fail:
672         return 0;
673 }
674 
675 static struct clk *const standard_pmc_clocks[] __initconst = {
676         /* four primary clocks */
677         &clk32k,
678         &main_clk,
679         &plla,
680 
681         /* MCK */
682         &mck
683 };
684 
685 /* PLLB generated USB full speed clock init */
686 static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
687 {
688         unsigned int reg;
689 
690         /*
691          * USB clock init:  choose 48 MHz PLLB value,
692          * disable 48MHz clock during usb peripheral suspend.
693          *
694          * REVISIT:  assumes MCK doesn't derive from PLLB!
695          */
696         uhpck.parent = &pllb;
697 
698         reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
699         pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
700         if (cpu_is_at91rm9200()) {
701                 reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
702                 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
703                 udpck.pmc_mask = AT91RM9200_PMC_UDP;
704                 at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
705         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
706                    cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
707                    cpu_is_at91sam9g10()) {
708                 reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
709                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
710                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
711         } else if (cpu_is_at91sam9n12()) {
712                 /* Divider for USB clock is in USB clock register for 9n12 */
713                 reg = AT91_PMC_USBS_PLLB;
714 
715                 /* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
716                 reg |= AT91_PMC_OHCIUSBDIV_2;
717                 at91_pmc_write(AT91_PMC_USB, reg);
718 
719                 /* Still setup masks */
720                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
721                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
722         }
723         at91_pmc_write(AT91_CKGR_PLLBR, 0);
724 
725         udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
726         uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
727 }
728 
729 /* UPLL generated USB full speed clock init */
730 static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
731 {
732         /*
733          * USB clock init: choose 480 MHz from UPLL,
734          */
735         unsigned int usbr = AT91_PMC_USBS_UPLL;
736 
737         /* Setup divider by 10 to reach 48 MHz */
738         usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
739 
740         at91_pmc_write(AT91_PMC_USB, usbr);
741 
742         /* Now set uhpck values */
743         uhpck.parent = &utmi_clk;
744         uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
745         uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr);
746 }
747 
748 static int __init at91_pmc_init(unsigned long main_clock)
749 {
750         unsigned tmp, freq, mckr;
751         int i;
752         int pll_overclock = false;
753 
754         /*
755          * When the bootloader initialized the main oscillator correctly,
756          * there's no problem using the cycle counter.  But if it didn't,
757          * or when using oscillator bypass mode, we must be told the speed
758          * of the main clock.
759          */
760         if (!main_clock) {
761                 do {
762                         tmp = at91_pmc_read(AT91_CKGR_MCFR);
763                 } while (!(tmp & AT91_PMC_MAINRDY));
764                 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
765         }
766         main_clk.rate_hz = main_clock;
767 
768         /* report if PLLA is more than mildly overclocked */
769         plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
770         if (cpu_has_1056M_plla()) {
771                 if (plla.rate_hz > 1056000000)
772                         pll_overclock = true;
773         } else if (cpu_has_800M_plla()) {
774                 if (plla.rate_hz > 800000000)
775                         pll_overclock = true;
776         } else if (cpu_has_300M_plla()) {
777                 if (plla.rate_hz > 300000000)
778                         pll_overclock = true;
779         } else if (cpu_has_240M_plla()) {
780                 if (plla.rate_hz > 240000000)
781                         pll_overclock = true;
782         } else if (cpu_has_210M_plla()) {
783                 if (plla.rate_hz > 210000000)
784                         pll_overclock = true;
785         } else {
786                 if (plla.rate_hz > 209000000)
787                         pll_overclock = true;
788         }
789         if (pll_overclock)
790                 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
791 
792         if (cpu_has_plladiv2()) {
793                 mckr = at91_pmc_read(AT91_PMC_MCKR);
794                 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));      /* plla divisor by 2 */
795         }
796 
797         if (!cpu_has_pllb() && cpu_has_upll()) {
798                 /* setup UTMI clock as the fourth primary clock
799                  * (instead of pllb) */
800                 utmi_clk.type |= CLK_TYPE_PRIMARY;
801                 utmi_clk.id = 3;
802         }
803 
804 
805         /*
806          * USB HS clock init
807          */
808         if (cpu_has_utmi()) {
809                 /*
810                  * multiplier is hard-wired to 40
811                  * (obtain the USB High Speed 480 MHz when input is 12 MHz)
812                  */
813                 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
814 
815                 /* UTMI bias and PLL are managed at the same time */
816                 if (cpu_has_upll())
817                         utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
818         }
819 
820         /*
821          * USB FS clock init
822          */
823         if (cpu_has_pllb())
824                 at91_pllb_usbfs_clock_init(main_clock);
825         if (cpu_has_upll())
826                 /* assumes that we choose UPLL for USB and not PLLA */
827                 at91_upll_usbfs_clock_init(main_clock);
828 
829         /*
830          * MCK and CPU derive from one of those primary clocks.
831          * For now, assume this parentage won't change.
832          */
833         mckr = at91_pmc_read(AT91_PMC_MCKR);
834         mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
835         freq = mck.parent->rate_hz;
836         freq /= pmc_prescaler_divider(mckr);                                    /* prescale */
837         if (cpu_is_at91rm9200()) {
838                 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
839         } else if (cpu_is_at91sam9g20()) {
840                 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
841                         freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
842                 if (mckr & AT91_PMC_PDIV)
843                         freq /= 2;              /* processor clock division */
844         } else if (cpu_has_mdiv3()) {
845                 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
846                         freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
847         } else {
848                 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));              /* mdiv */
849         }
850 
851         if (cpu_has_alt_prescaler()) {
852                 /* Programmable clocks can use MCK */
853                 mck.type |= CLK_TYPE_PRIMARY;
854                 mck.id = 4;
855         }
856 
857         /* Register the PMC's standard clocks */
858         for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
859                 at91_clk_add(standard_pmc_clocks[i]);
860 
861         if (cpu_has_pllb())
862                 at91_clk_add(&pllb);
863 
864         if (cpu_has_uhp())
865                 at91_clk_add(&uhpck);
866 
867         if (cpu_has_udpfs())
868                 at91_clk_add(&udpck);
869 
870         if (cpu_has_utmi())
871                 at91_clk_add(&utmi_clk);
872 
873         /* MCK and CPU clock are "always on" */
874         clk_enable(&mck);
875 
876         printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
877                 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
878                 (unsigned) main_clock / 1000000,
879                 ((unsigned) main_clock % 1000000) / 1000);
880 
881         return 0;
882 }
883 
884 #if defined(CONFIG_OF)
885 static struct of_device_id pmc_ids[] = {
886         { .compatible = "atmel,at91rm9200-pmc" },
887         { /*sentinel*/ }
888 };
889 
890 static struct of_device_id osc_ids[] = {
891         { .compatible = "atmel,osc" },
892         { /*sentinel*/ }
893 };
894 
895 int __init at91_dt_clock_init(void)
896 {
897         struct device_node *np;
898         u32 main_clock = 0;
899 
900         np = of_find_matching_node(NULL, pmc_ids);
901         if (!np)
902                 panic("unable to find compatible pmc node in dtb\n");
903 
904         at91_pmc_base = of_iomap(np, 0);
905         if (!at91_pmc_base)
906                 panic("unable to map pmc cpu registers\n");
907 
908         of_node_put(np);
909 
910         /* retrieve the freqency of fixed clocks from device tree */
911         np = of_find_matching_node(NULL, osc_ids);
912         if (np) {
913                 u32 rate;
914                 if (!of_property_read_u32(np, "clock-frequency", &rate))
915                         main_clock = rate;
916         }
917 
918         of_node_put(np);
919 
920         return at91_pmc_init(main_clock);
921 }
922 #endif
923 
924 int __init at91_clock_init(unsigned long main_clock)
925 {
926         at91_pmc_base = ioremap(AT91_PMC, 256);
927         if (!at91_pmc_base)
928                 panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
929 
930         return at91_pmc_init(main_clock);
931 }
932 
933 /*
934  * Several unused clocks may be active.  Turn them off.
935  */
936 static int __init at91_clock_reset(void)
937 {
938         unsigned long pcdr = 0;
939         unsigned long pcdr1 = 0;
940         unsigned long scdr = 0;
941         struct clk *clk;
942 
943         list_for_each_entry(clk, &clocks, node) {
944                 if (clk->users > 0)
945                         continue;
946 
947                 if (clk->mode == pmc_periph_mode) {
948                         if (cpu_is_sama5d3()) {
949                                 u32 pmc_mask = 1 << (clk->pid % 32);
950 
951                                 if (clk->pid > 31)
952                                         pcdr1 |= pmc_mask;
953                                 else
954                                         pcdr |= pmc_mask;
955                         } else
956                                 pcdr |= clk->pmc_mask;
957                 }
958 
959                 if (clk->mode == pmc_sys_mode)
960                         scdr |= clk->pmc_mask;
961 
962                 pr_debug("Clocks: disable unused %s\n", clk->name);
963         }
964 
965         at91_pmc_write(AT91_PMC_SCDR, scdr);
966         at91_pmc_write(AT91_PMC_PCDR, pcdr);
967         if (cpu_is_sama5d3())
968                 at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
969 
970         return 0;
971 }
972 late_initcall(at91_clock_reset);
973 
974 void at91sam9_idle(void)
975 {
976         at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
977         cpu_do_idle();
978 }
979 

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