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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-at91/setup.c

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  1 /*
  2  * Copyright (C) 2007 Atmel Corporation.
  3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  4  *
  5  * Under GPLv2
  6  */
  7 
  8 #include <linux/module.h>
  9 #include <linux/io.h>
 10 #include <linux/mm.h>
 11 #include <linux/pm.h>
 12 #include <linux/of_address.h>
 13 #include <linux/pinctrl/machine.h>
 14 
 15 #include <asm/system_misc.h>
 16 #include <asm/mach/map.h>
 17 
 18 #include <mach/hardware.h>
 19 #include <mach/cpu.h>
 20 #include <mach/at91_dbgu.h>
 21 #include <mach/at91_pmc.h>
 22 
 23 #include "at91_shdwc.h"
 24 #include "soc.h"
 25 #include "generic.h"
 26 
 27 struct at91_init_soc __initdata at91_boot_soc;
 28 
 29 struct at91_socinfo at91_soc_initdata;
 30 EXPORT_SYMBOL(at91_soc_initdata);
 31 
 32 void __init at91rm9200_set_type(int type)
 33 {
 34         if (type == ARCH_REVISON_9200_PQFP)
 35                 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
 36         else
 37                 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
 38 
 39         pr_info("AT91: filled in soc subtype: %s\n",
 40                 at91_get_soc_subtype(&at91_soc_initdata));
 41 }
 42 
 43 void __init at91_init_irq_default(void)
 44 {
 45         at91_init_interrupts(at91_boot_soc.default_irq_priority);
 46 }
 47 
 48 void __init at91_init_interrupts(unsigned int *priority)
 49 {
 50         /* Initialize the AIC interrupt controller */
 51         at91_aic_init(priority, at91_extern_irq);
 52 
 53         /* Enable GPIO interrupts */
 54         at91_gpio_irq_setup();
 55 }
 56 
 57 void __iomem *at91_ramc_base[2];
 58 EXPORT_SYMBOL_GPL(at91_ramc_base);
 59 
 60 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
 61 {
 62         if (id < 0 || id > 1) {
 63                 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
 64                 BUG();
 65         }
 66         at91_ramc_base[id] = ioremap(addr, size);
 67         if (!at91_ramc_base[id])
 68                 panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
 69 }
 70 
 71 static struct map_desc sram_desc[2] __initdata;
 72 
 73 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
 74 {
 75         struct map_desc *desc = &sram_desc[bank];
 76 
 77         desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
 78         if (bank > 0)
 79                 desc->virtual -= sram_desc[bank - 1].length;
 80 
 81         desc->pfn = __phys_to_pfn(base);
 82         desc->length = length;
 83         desc->type = MT_DEVICE;
 84 
 85         pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
 86                 base, length, desc->virtual);
 87 
 88         iotable_init(desc, 1);
 89 }
 90 
 91 static struct map_desc at91_io_desc __initdata __maybe_unused = {
 92         .virtual        = (unsigned long)AT91_VA_BASE_SYS,
 93         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
 94         .length         = SZ_16K,
 95         .type           = MT_DEVICE,
 96 };
 97 
 98 static void __init soc_detect(u32 dbgu_base)
 99 {
100         u32 cidr, socid;
101 
102         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
103         socid = cidr & ~AT91_CIDR_VERSION;
104 
105         switch (socid) {
106         case ARCH_ID_AT91RM9200:
107                 at91_soc_initdata.type = AT91_SOC_RM9200;
108                 if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
109                         at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
110                 at91_boot_soc = at91rm9200_soc;
111                 break;
112 
113         case ARCH_ID_AT91SAM9260:
114                 at91_soc_initdata.type = AT91_SOC_SAM9260;
115                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
116                 at91_boot_soc = at91sam9260_soc;
117                 break;
118 
119         case ARCH_ID_AT91SAM9261:
120                 at91_soc_initdata.type = AT91_SOC_SAM9261;
121                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
122                 at91_boot_soc = at91sam9261_soc;
123                 break;
124 
125         case ARCH_ID_AT91SAM9263:
126                 at91_soc_initdata.type = AT91_SOC_SAM9263;
127                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
128                 at91_boot_soc = at91sam9263_soc;
129                 break;
130 
131         case ARCH_ID_AT91SAM9G20:
132                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
133                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
134                 at91_boot_soc = at91sam9260_soc;
135                 break;
136 
137         case ARCH_ID_AT91SAM9G45:
138                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
139                 if (cidr == ARCH_ID_AT91SAM9G45ES)
140                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
141                 at91_boot_soc = at91sam9g45_soc;
142                 break;
143 
144         case ARCH_ID_AT91SAM9RL64:
145                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
146                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
147                 at91_boot_soc = at91sam9rl_soc;
148                 break;
149 
150         case ARCH_ID_AT91SAM9X5:
151                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
152                 at91_boot_soc = at91sam9x5_soc;
153                 break;
154 
155         case ARCH_ID_AT91SAM9N12:
156                 at91_soc_initdata.type = AT91_SOC_SAM9N12;
157                 at91_boot_soc = at91sam9n12_soc;
158                 break;
159 
160         case ARCH_ID_SAMA5D3:
161                 at91_soc_initdata.type = AT91_SOC_SAMA5D3;
162                 at91_boot_soc = sama5d3_soc;
163                 break;
164         }
165 
166         /* at91sam9g10 */
167         if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
168                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
169                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
170                 at91_boot_soc = at91sam9261_soc;
171         }
172         /* at91sam9xe */
173         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
174                 at91_soc_initdata.type = AT91_SOC_SAM9260;
175                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
176                 at91_boot_soc = at91sam9260_soc;
177         }
178 
179         if (!at91_soc_is_detected())
180                 return;
181 
182         at91_soc_initdata.cidr = cidr;
183 
184         /* sub version of soc */
185         at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
186 
187         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
188                 switch (at91_soc_initdata.exid) {
189                 case ARCH_EXID_AT91SAM9M10:
190                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
191                         break;
192                 case ARCH_EXID_AT91SAM9G46:
193                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
194                         break;
195                 case ARCH_EXID_AT91SAM9M11:
196                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
197                         break;
198                 }
199         }
200 
201         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
202                 switch (at91_soc_initdata.exid) {
203                 case ARCH_EXID_AT91SAM9G15:
204                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
205                         break;
206                 case ARCH_EXID_AT91SAM9G35:
207                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
208                         break;
209                 case ARCH_EXID_AT91SAM9X35:
210                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
211                         break;
212                 case ARCH_EXID_AT91SAM9G25:
213                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
214                         break;
215                 case ARCH_EXID_AT91SAM9X25:
216                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
217                         break;
218                 }
219         }
220 
221         if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
222                 switch (at91_soc_initdata.exid) {
223                 case ARCH_EXID_SAMA5D31:
224                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
225                         break;
226                 case ARCH_EXID_SAMA5D33:
227                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
228                         break;
229                 case ARCH_EXID_SAMA5D34:
230                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
231                         break;
232                 case ARCH_EXID_SAMA5D35:
233                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
234                         break;
235                 }
236         }
237 }
238 
239 static const char *soc_name[] = {
240         [AT91_SOC_RM9200]       = "at91rm9200",
241         [AT91_SOC_SAM9260]      = "at91sam9260",
242         [AT91_SOC_SAM9261]      = "at91sam9261",
243         [AT91_SOC_SAM9263]      = "at91sam9263",
244         [AT91_SOC_SAM9G10]      = "at91sam9g10",
245         [AT91_SOC_SAM9G20]      = "at91sam9g20",
246         [AT91_SOC_SAM9G45]      = "at91sam9g45",
247         [AT91_SOC_SAM9RL]       = "at91sam9rl",
248         [AT91_SOC_SAM9X5]       = "at91sam9x5",
249         [AT91_SOC_SAM9N12]      = "at91sam9n12",
250         [AT91_SOC_SAMA5D3]      = "sama5d3",
251         [AT91_SOC_UNKNOWN]      = "Unknown",
252 };
253 
254 const char *at91_get_soc_type(struct at91_socinfo *c)
255 {
256         return soc_name[c->type];
257 }
258 EXPORT_SYMBOL(at91_get_soc_type);
259 
260 static const char *soc_subtype_name[] = {
261         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
262         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
263         [AT91_SOC_SAM9XE]       = "at91sam9xe",
264         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
265         [AT91_SOC_SAM9M10]      = "at91sam9m10",
266         [AT91_SOC_SAM9G46]      = "at91sam9g46",
267         [AT91_SOC_SAM9M11]      = "at91sam9m11",
268         [AT91_SOC_SAM9G15]      = "at91sam9g15",
269         [AT91_SOC_SAM9G35]      = "at91sam9g35",
270         [AT91_SOC_SAM9X35]      = "at91sam9x35",
271         [AT91_SOC_SAM9G25]      = "at91sam9g25",
272         [AT91_SOC_SAM9X25]      = "at91sam9x25",
273         [AT91_SOC_SAMA5D31]     = "sama5d31",
274         [AT91_SOC_SAMA5D33]     = "sama5d33",
275         [AT91_SOC_SAMA5D34]     = "sama5d34",
276         [AT91_SOC_SAMA5D35]     = "sama5d35",
277         [AT91_SOC_SUBTYPE_NONE] = "None",
278         [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
279 };
280 
281 const char *at91_get_soc_subtype(struct at91_socinfo *c)
282 {
283         return soc_subtype_name[c->subtype];
284 }
285 EXPORT_SYMBOL(at91_get_soc_subtype);
286 
287 void __init at91_map_io(void)
288 {
289         /* Map peripherals */
290         iotable_init(&at91_io_desc, 1);
291 
292         at91_soc_initdata.type = AT91_SOC_UNKNOWN;
293         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
294 
295         soc_detect(AT91_BASE_DBGU0);
296         if (!at91_soc_is_detected())
297                 soc_detect(AT91_BASE_DBGU1);
298 
299         if (!at91_soc_is_detected())
300                 panic("AT91: Impossible to detect the SOC type");
301 
302         pr_info("AT91: Detected soc type: %s\n",
303                 at91_get_soc_type(&at91_soc_initdata));
304         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
305                 pr_info("AT91: Detected soc subtype: %s\n",
306                         at91_get_soc_subtype(&at91_soc_initdata));
307 
308         if (!at91_soc_is_enabled())
309                 panic("AT91: Soc not enabled");
310 
311         if (at91_boot_soc.map_io)
312                 at91_boot_soc.map_io();
313 }
314 
315 void __iomem *at91_shdwc_base = NULL;
316 
317 static void at91sam9_poweroff(void)
318 {
319         at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
320 }
321 
322 void __init at91_ioremap_shdwc(u32 base_addr)
323 {
324         at91_shdwc_base = ioremap(base_addr, 16);
325         if (!at91_shdwc_base)
326                 panic("Impossible to ioremap at91_shdwc_base\n");
327         pm_power_off = at91sam9_poweroff;
328 }
329 
330 void __iomem *at91_rstc_base;
331 
332 void __init at91_ioremap_rstc(u32 base_addr)
333 {
334         at91_rstc_base = ioremap(base_addr, 16);
335         if (!at91_rstc_base)
336                 panic("Impossible to ioremap at91_rstc_base\n");
337 }
338 
339 void __iomem *at91_matrix_base;
340 EXPORT_SYMBOL_GPL(at91_matrix_base);
341 
342 void __init at91_ioremap_matrix(u32 base_addr)
343 {
344         at91_matrix_base = ioremap(base_addr, 512);
345         if (!at91_matrix_base)
346                 panic("Impossible to ioremap at91_matrix_base\n");
347 }
348 
349 #if defined(CONFIG_OF)
350 static struct of_device_id rstc_ids[] = {
351         { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
352         { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
353         { /*sentinel*/ }
354 };
355 
356 static void at91_dt_rstc(void)
357 {
358         struct device_node *np;
359         const struct of_device_id *of_id;
360 
361         np = of_find_matching_node(NULL, rstc_ids);
362         if (!np)
363                 panic("unable to find compatible rstc node in dtb\n");
364 
365         at91_rstc_base = of_iomap(np, 0);
366         if (!at91_rstc_base)
367                 panic("unable to map rstc cpu registers\n");
368 
369         of_id = of_match_node(rstc_ids, np);
370         if (!of_id)
371                 panic("AT91: rtsc no restart function available\n");
372 
373         arm_pm_restart = of_id->data;
374 
375         of_node_put(np);
376 }
377 
378 static struct of_device_id ramc_ids[] = {
379         { .compatible = "atmel,at91rm9200-sdramc" },
380         { .compatible = "atmel,at91sam9260-sdramc" },
381         { .compatible = "atmel,at91sam9g45-ddramc" },
382         { /*sentinel*/ }
383 };
384 
385 static void at91_dt_ramc(void)
386 {
387         struct device_node *np;
388 
389         np = of_find_matching_node(NULL, ramc_ids);
390         if (!np)
391                 panic("unable to find compatible ram controller node in dtb\n");
392 
393         at91_ramc_base[0] = of_iomap(np, 0);
394         if (!at91_ramc_base[0])
395                 panic("unable to map ramc[0] cpu registers\n");
396         /* the controller may have 2 banks */
397         at91_ramc_base[1] = of_iomap(np, 1);
398 
399         of_node_put(np);
400 }
401 
402 static struct of_device_id shdwc_ids[] = {
403         { .compatible = "atmel,at91sam9260-shdwc", },
404         { .compatible = "atmel,at91sam9rl-shdwc", },
405         { .compatible = "atmel,at91sam9x5-shdwc", },
406         { /*sentinel*/ }
407 };
408 
409 static const char *shdwc_wakeup_modes[] = {
410         [AT91_SHDW_WKMODE0_NONE]        = "none",
411         [AT91_SHDW_WKMODE0_HIGH]        = "high",
412         [AT91_SHDW_WKMODE0_LOW]         = "low",
413         [AT91_SHDW_WKMODE0_ANYLEVEL]    = "any",
414 };
415 
416 const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
417 {
418         const char *pm;
419         int err, i;
420 
421         err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
422         if (err < 0)
423                 return AT91_SHDW_WKMODE0_ANYLEVEL;
424 
425         for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
426                 if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
427                         return i;
428 
429         return -ENODEV;
430 }
431 
432 static void at91_dt_shdwc(void)
433 {
434         struct device_node *np;
435         int wakeup_mode;
436         u32 reg;
437         u32 mode = 0;
438 
439         np = of_find_matching_node(NULL, shdwc_ids);
440         if (!np) {
441                 pr_debug("AT91: unable to find compatible shutdown (shdwc) controller node in dtb\n");
442                 return;
443         }
444 
445         at91_shdwc_base = of_iomap(np, 0);
446         if (!at91_shdwc_base)
447                 panic("AT91: unable to map shdwc cpu registers\n");
448 
449         wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
450         if (wakeup_mode < 0) {
451                 pr_warn("AT91: shdwc unknown wakeup mode\n");
452                 goto end;
453         }
454 
455         if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
456                 if (reg > AT91_SHDW_CPTWK0_MAX) {
457                         pr_warn("AT91: shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
458                                 reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
459                         reg = AT91_SHDW_CPTWK0_MAX;
460                 }
461                 mode |= AT91_SHDW_CPTWK0_(reg);
462         }
463 
464         if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
465                         mode |= AT91_SHDW_RTCWKEN;
466 
467         if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
468                         mode |= AT91_SHDW_RTTWKEN;
469 
470         at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
471 
472 end:
473         pm_power_off = at91sam9_poweroff;
474 
475         of_node_put(np);
476 }
477 
478 void __init at91rm9200_dt_initialize(void)
479 {
480         at91_dt_ramc();
481 
482         /* Init clock subsystem */
483         at91_dt_clock_init();
484 
485         /* Register the processor-specific clocks */
486         at91_boot_soc.register_clocks();
487 
488         at91_boot_soc.init();
489 }
490 
491 void __init at91_dt_initialize(void)
492 {
493         at91_dt_rstc();
494         at91_dt_ramc();
495         at91_dt_shdwc();
496 
497         /* Init clock subsystem */
498         at91_dt_clock_init();
499 
500         /* Register the processor-specific clocks */
501         at91_boot_soc.register_clocks();
502 
503         if (at91_boot_soc.init)
504                 at91_boot_soc.init();
505 }
506 #endif
507 
508 void __init at91_initialize(unsigned long main_clock)
509 {
510         at91_boot_soc.ioremap_registers();
511 
512         /* Init clock subsystem */
513         at91_clock_init(main_clock);
514 
515         /* Register the processor-specific clocks */
516         at91_boot_soc.register_clocks();
517 
518         at91_boot_soc.init();
519 
520         pinctrl_provide_dummies();
521 }
522 

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