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Linux/arch/arm/mach-cns3xxx/devices.c

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  1 /*
  2  * CNS3xxx common devices
  3  *
  4  * Copyright 2008 Cavium Networks
  5  *                Scott Shu
  6  * Copyright 2010 MontaVista Software, LLC.
  7  *                Anton Vorontsov <avorontsov@mvista.com>
  8  *
  9  * This file is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License, Version 2, as
 11  * published by the Free Software Foundation.
 12  */
 13 
 14 #include <linux/io.h>
 15 #include <linux/init.h>
 16 #include <linux/compiler.h>
 17 #include <linux/dma-mapping.h>
 18 #include <linux/platform_device.h>
 19 #include "cns3xxx.h"
 20 #include "pm.h"
 21 #include "core.h"
 22 #include "devices.h"
 23 
 24 /*
 25  * AHCI
 26  */
 27 static struct resource cns3xxx_ahci_resource[] = {
 28         [0] = {
 29                 .start  = CNS3XXX_SATA2_BASE,
 30                 .end    = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
 31                 .flags  = IORESOURCE_MEM,
 32         },
 33         [1] = {
 34                 .start  = IRQ_CNS3XXX_SATA,
 35                 .end    = IRQ_CNS3XXX_SATA,
 36                 .flags  = IORESOURCE_IRQ,
 37         },
 38 };
 39 
 40 static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
 41 
 42 static struct platform_device cns3xxx_ahci_pdev = {
 43         .name           = "ahci",
 44         .id             = 0,
 45         .resource       = cns3xxx_ahci_resource,
 46         .num_resources  = ARRAY_SIZE(cns3xxx_ahci_resource),
 47         .dev            = {
 48                 .dma_mask               = &cns3xxx_ahci_dmamask,
 49                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 50         },
 51 };
 52 
 53 void __init cns3xxx_ahci_init(void)
 54 {
 55         u32 tmp;
 56 
 57         tmp = __raw_readl(MISC_SATA_POWER_MODE);
 58         tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
 59         tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
 60         __raw_writel(tmp, MISC_SATA_POWER_MODE);
 61 
 62         /* Enable SATA PHY */
 63         cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
 64         cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
 65 
 66         /* Enable SATA Clock */
 67         cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
 68 
 69         /* De-Asscer SATA Reset */
 70         cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
 71 
 72         platform_device_register(&cns3xxx_ahci_pdev);
 73 }
 74 
 75 /*
 76  * SDHCI
 77  */
 78 static struct resource cns3xxx_sdhci_resources[] = {
 79         [0] = {
 80                 .start = CNS3XXX_SDIO_BASE,
 81                 .end   = CNS3XXX_SDIO_BASE + SZ_4K - 1,
 82                 .flags = IORESOURCE_MEM,
 83         },
 84         [1] = {
 85                 .start = IRQ_CNS3XXX_SDIO,
 86                 .end   = IRQ_CNS3XXX_SDIO,
 87                 .flags = IORESOURCE_IRQ,
 88         },
 89 };
 90 
 91 static struct platform_device cns3xxx_sdhci_pdev = {
 92         .name           = "sdhci-cns3xxx",
 93         .id             = 0,
 94         .num_resources  = ARRAY_SIZE(cns3xxx_sdhci_resources),
 95         .resource       = cns3xxx_sdhci_resources,
 96 };
 97 
 98 void __init cns3xxx_sdhci_init(void)
 99 {
100         u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
101         u32 gpioa_pins = __raw_readl(gpioa);
102 
103         /* MMC/SD pins share with GPIOA */
104         gpioa_pins |= 0x1fff0004;
105         __raw_writel(gpioa_pins, gpioa);
106 
107         cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
108         cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
109 
110         platform_device_register(&cns3xxx_sdhci_pdev);
111 }
112 

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