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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-davinci/board-dm365-evm.c

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  1 /*
  2  * TI DaVinci DM365 EVM board support
  3  *
  4  * Copyright (C) 2009 Texas Instruments Incorporated
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License as
  8  * published by the Free Software Foundation version 2.
  9  *
 10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 11  * kind, whether express or implied; without even the implied warranty
 12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 #include <linux/kernel.h>
 16 #include <linux/init.h>
 17 #include <linux/err.h>
 18 #include <linux/i2c.h>
 19 #include <linux/io.h>
 20 #include <linux/clk.h>
 21 #include <linux/platform_data/at24.h>
 22 #include <linux/leds.h>
 23 #include <linux/mtd/mtd.h>
 24 #include <linux/mtd/partitions.h>
 25 #include <linux/slab.h>
 26 #include <linux/mtd/nand.h>
 27 #include <linux/input.h>
 28 #include <linux/spi/spi.h>
 29 #include <linux/spi/eeprom.h>
 30 #include <linux/v4l2-dv-timings.h>
 31 
 32 #include <asm/mach-types.h>
 33 #include <asm/mach/arch.h>
 34 
 35 #include <mach/mux.h>
 36 #include <mach/common.h>
 37 #include <linux/platform_data/i2c-davinci.h>
 38 #include <mach/serial.h>
 39 #include <linux/platform_data/mmc-davinci.h>
 40 #include <linux/platform_data/mtd-davinci.h>
 41 #include <linux/platform_data/keyscan-davinci.h>
 42 
 43 #include <media/i2c/ths7303.h>
 44 #include <media/i2c/tvp514x.h>
 45 
 46 #include "davinci.h"
 47 
 48 static inline int have_imager(void)
 49 {
 50         /* REVISIT when it's supported, trigger via Kconfig */
 51         return 0;
 52 }
 53 
 54 static inline int have_tvp7002(void)
 55 {
 56         /* REVISIT when it's supported, trigger via Kconfig */
 57         return 0;
 58 }
 59 
 60 #define DM365_EVM_PHY_ID                "davinci_mdio-0:01"
 61 /*
 62  * A MAX-II CPLD is used for various board control functions.
 63  */
 64 #define CPLD_OFFSET(a13a8,a2a1)         (((a13a8) << 10) + ((a2a1) << 3))
 65 
 66 #define CPLD_VERSION    CPLD_OFFSET(0,0)        /* r/o */
 67 #define CPLD_TEST       CPLD_OFFSET(0,1)
 68 #define CPLD_LEDS       CPLD_OFFSET(0,2)
 69 #define CPLD_MUX        CPLD_OFFSET(0,3)
 70 #define CPLD_SWITCH     CPLD_OFFSET(1,0)        /* r/o */
 71 #define CPLD_POWER      CPLD_OFFSET(1,1)
 72 #define CPLD_VIDEO      CPLD_OFFSET(1,2)
 73 #define CPLD_CARDSTAT   CPLD_OFFSET(1,3)        /* r/o */
 74 
 75 #define CPLD_DILC_OUT   CPLD_OFFSET(2,0)
 76 #define CPLD_DILC_IN    CPLD_OFFSET(2,1)        /* r/o */
 77 
 78 #define CPLD_IMG_DIR0   CPLD_OFFSET(2,2)
 79 #define CPLD_IMG_MUX0   CPLD_OFFSET(2,3)
 80 #define CPLD_IMG_MUX1   CPLD_OFFSET(3,0)
 81 #define CPLD_IMG_DIR1   CPLD_OFFSET(3,1)
 82 #define CPLD_IMG_MUX2   CPLD_OFFSET(3,2)
 83 #define CPLD_IMG_MUX3   CPLD_OFFSET(3,3)
 84 #define CPLD_IMG_DIR2   CPLD_OFFSET(4,0)
 85 #define CPLD_IMG_MUX4   CPLD_OFFSET(4,1)
 86 #define CPLD_IMG_MUX5   CPLD_OFFSET(4,2)
 87 
 88 #define CPLD_RESETS     CPLD_OFFSET(4,3)
 89 
 90 #define CPLD_CCD_DIR1   CPLD_OFFSET(0x3e,0)
 91 #define CPLD_CCD_IO1    CPLD_OFFSET(0x3e,1)
 92 #define CPLD_CCD_DIR2   CPLD_OFFSET(0x3e,2)
 93 #define CPLD_CCD_IO2    CPLD_OFFSET(0x3e,3)
 94 #define CPLD_CCD_DIR3   CPLD_OFFSET(0x3f,0)
 95 #define CPLD_CCD_IO3    CPLD_OFFSET(0x3f,1)
 96 
 97 static void __iomem *cpld;
 98 
 99 
100 /* NOTE:  this is geared for the standard config, with a socketed
101  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
102  * swap chips with a different block size, partitioning will
103  * need to be changed. This NAND chip MT29F16G08FAA is the default
104  * NAND shipped with the Spectrum Digital DM365 EVM
105  */
106 #define NAND_BLOCK_SIZE         SZ_128K
107 
108 static struct mtd_partition davinci_nand_partitions[] = {
109         {
110                 /* UBL (a few copies) plus U-Boot */
111                 .name           = "bootloader",
112                 .offset         = 0,
113                 .size           = 30 * NAND_BLOCK_SIZE,
114                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
115         }, {
116                 /* U-Boot environment */
117                 .name           = "params",
118                 .offset         = MTDPART_OFS_APPEND,
119                 .size           = 2 * NAND_BLOCK_SIZE,
120                 .mask_flags     = 0,
121         }, {
122                 .name           = "kernel",
123                 .offset         = MTDPART_OFS_APPEND,
124                 .size           = SZ_4M,
125                 .mask_flags     = 0,
126         }, {
127                 .name           = "filesystem1",
128                 .offset         = MTDPART_OFS_APPEND,
129                 .size           = SZ_512M,
130                 .mask_flags     = 0,
131         }, {
132                 .name           = "filesystem2",
133                 .offset         = MTDPART_OFS_APPEND,
134                 .size           = MTDPART_SIZ_FULL,
135                 .mask_flags     = 0,
136         }
137         /* two blocks with bad block table (and mirror) at the end */
138 };
139 
140 static struct davinci_nand_pdata davinci_nand_data = {
141         .mask_chipsel           = BIT(14),
142         .parts                  = davinci_nand_partitions,
143         .nr_parts               = ARRAY_SIZE(davinci_nand_partitions),
144         .ecc_mode               = NAND_ECC_HW,
145         .bbt_options            = NAND_BBT_USE_FLASH,
146         .ecc_bits               = 4,
147 };
148 
149 static struct resource davinci_nand_resources[] = {
150         {
151                 .start          = DM365_ASYNC_EMIF_DATA_CE0_BASE,
152                 .end            = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
153                 .flags          = IORESOURCE_MEM,
154         }, {
155                 .start          = DM365_ASYNC_EMIF_CONTROL_BASE,
156                 .end            = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
157                 .flags          = IORESOURCE_MEM,
158         },
159 };
160 
161 static struct platform_device davinci_nand_device = {
162         .name                   = "davinci_nand",
163         .id                     = 0,
164         .num_resources          = ARRAY_SIZE(davinci_nand_resources),
165         .resource               = davinci_nand_resources,
166         .dev                    = {
167                 .platform_data  = &davinci_nand_data,
168         },
169 };
170 
171 static struct at24_platform_data eeprom_info = {
172         .byte_len       = (256*1024) / 8,
173         .page_size      = 64,
174         .flags          = AT24_FLAG_ADDR16,
175         .setup          = davinci_get_mac_addr,
176         .context        = (void *)0x7f00,
177 };
178 
179 static struct i2c_board_info i2c_info[] = {
180         {
181                 I2C_BOARD_INFO("24c256", 0x50),
182                 .platform_data  = &eeprom_info,
183         },
184         {
185                 I2C_BOARD_INFO("tlv320aic3x", 0x18),
186         },
187 };
188 
189 static struct davinci_i2c_platform_data i2c_pdata = {
190         .bus_freq       = 400   /* kHz */,
191         .bus_delay      = 0     /* usec */,
192 };
193 
194 static int dm365evm_keyscan_enable(struct device *dev)
195 {
196         return davinci_cfg_reg(DM365_KEYSCAN);
197 }
198 
199 static unsigned short dm365evm_keymap[] = {
200         KEY_KP2,
201         KEY_LEFT,
202         KEY_EXIT,
203         KEY_DOWN,
204         KEY_ENTER,
205         KEY_UP,
206         KEY_KP1,
207         KEY_RIGHT,
208         KEY_MENU,
209         KEY_RECORD,
210         KEY_REWIND,
211         KEY_KPMINUS,
212         KEY_STOP,
213         KEY_FASTFORWARD,
214         KEY_KPPLUS,
215         KEY_PLAYPAUSE,
216         0
217 };
218 
219 static struct davinci_ks_platform_data dm365evm_ks_data = {
220         .device_enable  = dm365evm_keyscan_enable,
221         .keymap         = dm365evm_keymap,
222         .keymapsize     = ARRAY_SIZE(dm365evm_keymap),
223         .rep            = 1,
224         /* Scan period = strobe + interval */
225         .strobe         = 0x5,
226         .interval       = 0x2,
227         .matrix_type    = DAVINCI_KEYSCAN_MATRIX_4X4,
228 };
229 
230 static int cpld_mmc_get_cd(int module)
231 {
232         if (!cpld)
233                 return -ENXIO;
234 
235         /* low == card present */
236         return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
237 }
238 
239 static int cpld_mmc_get_ro(int module)
240 {
241         if (!cpld)
242                 return -ENXIO;
243 
244         /* high == card's write protect switch active */
245         return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
246 }
247 
248 static struct davinci_mmc_config dm365evm_mmc_config = {
249         .get_cd         = cpld_mmc_get_cd,
250         .get_ro         = cpld_mmc_get_ro,
251         .wires          = 4,
252         .max_freq       = 50000000,
253         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
254 };
255 
256 static void dm365evm_emac_configure(void)
257 {
258         /*
259          * EMAC pins are multiplexed with GPIO and UART
260          * Further details are available at the DM365 ARM
261          * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
262          */
263         davinci_cfg_reg(DM365_EMAC_TX_EN);
264         davinci_cfg_reg(DM365_EMAC_TX_CLK);
265         davinci_cfg_reg(DM365_EMAC_COL);
266         davinci_cfg_reg(DM365_EMAC_TXD3);
267         davinci_cfg_reg(DM365_EMAC_TXD2);
268         davinci_cfg_reg(DM365_EMAC_TXD1);
269         davinci_cfg_reg(DM365_EMAC_TXD0);
270         davinci_cfg_reg(DM365_EMAC_RXD3);
271         davinci_cfg_reg(DM365_EMAC_RXD2);
272         davinci_cfg_reg(DM365_EMAC_RXD1);
273         davinci_cfg_reg(DM365_EMAC_RXD0);
274         davinci_cfg_reg(DM365_EMAC_RX_CLK);
275         davinci_cfg_reg(DM365_EMAC_RX_DV);
276         davinci_cfg_reg(DM365_EMAC_RX_ER);
277         davinci_cfg_reg(DM365_EMAC_CRS);
278         davinci_cfg_reg(DM365_EMAC_MDIO);
279         davinci_cfg_reg(DM365_EMAC_MDCLK);
280 
281         /*
282          * EMAC interrupts are multiplexed with GPIO interrupts
283          * Details are available at the DM365 ARM
284          * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
285          */
286         davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
287         davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
288         davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
289         davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
290 }
291 
292 static void dm365evm_mmc_configure(void)
293 {
294         /*
295          * MMC/SD pins are multiplexed with GPIO and EMIF
296          * Further details are available at the DM365 ARM
297          * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
298          */
299         davinci_cfg_reg(DM365_SD1_CLK);
300         davinci_cfg_reg(DM365_SD1_CMD);
301         davinci_cfg_reg(DM365_SD1_DATA3);
302         davinci_cfg_reg(DM365_SD1_DATA2);
303         davinci_cfg_reg(DM365_SD1_DATA1);
304         davinci_cfg_reg(DM365_SD1_DATA0);
305 }
306 
307 static struct tvp514x_platform_data tvp5146_pdata = {
308         .clk_polarity = 0,
309         .hs_polarity = 1,
310         .vs_polarity = 1
311 };
312 
313 #define TVP514X_STD_ALL        (V4L2_STD_NTSC | V4L2_STD_PAL)
314 /* Inputs available at the TVP5146 */
315 static struct v4l2_input tvp5146_inputs[] = {
316         {
317                 .index = 0,
318                 .name = "Composite",
319                 .type = V4L2_INPUT_TYPE_CAMERA,
320                 .std = TVP514X_STD_ALL,
321         },
322         {
323                 .index = 1,
324                 .name = "S-Video",
325                 .type = V4L2_INPUT_TYPE_CAMERA,
326                 .std = TVP514X_STD_ALL,
327         },
328 };
329 
330 /*
331  * this is the route info for connecting each input to decoder
332  * ouput that goes to vpfe. There is a one to one correspondence
333  * with tvp5146_inputs
334  */
335 static struct vpfe_route tvp5146_routes[] = {
336         {
337                 .input = INPUT_CVBS_VI2B,
338                 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
339         },
340 {
341                 .input = INPUT_SVIDEO_VI2C_VI1C,
342                 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
343         },
344 };
345 
346 static struct vpfe_subdev_info vpfe_sub_devs[] = {
347         {
348                 .name = "tvp5146",
349                 .grp_id = 0,
350                 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
351                 .inputs = tvp5146_inputs,
352                 .routes = tvp5146_routes,
353                 .can_route = 1,
354                 .ccdc_if_params = {
355                         .if_type = VPFE_BT656,
356                         .hdpol = VPFE_PINPOL_POSITIVE,
357                         .vdpol = VPFE_PINPOL_POSITIVE,
358                 },
359                 .board_info = {
360                         I2C_BOARD_INFO("tvp5146", 0x5d),
361                         .platform_data = &tvp5146_pdata,
362                 },
363         },
364 };
365 
366 static struct vpfe_config vpfe_cfg = {
367         .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
368         .sub_devs = vpfe_sub_devs,
369         .i2c_adapter_id = 1,
370         .card_name = "DM365 EVM",
371         .ccdc = "ISIF",
372 };
373 
374 /* venc standards timings */
375 static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
376         {
377                 .name           = "ntsc",
378                 .timings_type   = VPBE_ENC_STD,
379                 .std_id         = V4L2_STD_NTSC,
380                 .interlaced     = 1,
381                 .xres           = 720,
382                 .yres           = 480,
383                 .aspect         = {11, 10},
384                 .fps            = {30000, 1001},
385                 .left_margin    = 0x79,
386                 .upper_margin   = 0x10,
387         },
388         {
389                 .name           = "pal",
390                 .timings_type   = VPBE_ENC_STD,
391                 .std_id         = V4L2_STD_PAL,
392                 .interlaced     = 1,
393                 .xres           = 720,
394                 .yres           = 576,
395                 .aspect         = {54, 59},
396                 .fps            = {25, 1},
397                 .left_margin    = 0x7E,
398                 .upper_margin   = 0x16,
399         },
400 };
401 
402 /* venc dv timings */
403 static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
404         {
405                 .name           = "480p59_94",
406                 .timings_type   = VPBE_ENC_DV_TIMINGS,
407                 .dv_timings     = V4L2_DV_BT_CEA_720X480P59_94,
408                 .interlaced     = 0,
409                 .xres           = 720,
410                 .yres           = 480,
411                 .aspect         = {1, 1},
412                 .fps            = {5994, 100},
413                 .left_margin    = 0x8F,
414                 .upper_margin   = 0x2D,
415         },
416         {
417                 .name           = "576p50",
418                 .timings_type   = VPBE_ENC_DV_TIMINGS,
419                 .dv_timings     = V4L2_DV_BT_CEA_720X576P50,
420                 .interlaced     = 0,
421                 .xres           = 720,
422                 .yres           = 576,
423                 .aspect         = {1, 1},
424                 .fps            = {50, 1},
425                 .left_margin    = 0x8C,
426                 .upper_margin   = 0x36,
427         },
428         {
429                 .name           = "720p60",
430                 .timings_type   = VPBE_ENC_DV_TIMINGS,
431                 .dv_timings     = V4L2_DV_BT_CEA_1280X720P60,
432                 .interlaced     = 0,
433                 .xres           = 1280,
434                 .yres           = 720,
435                 .aspect         = {1, 1},
436                 .fps            = {60, 1},
437                 .left_margin    = 0x117,
438                 .right_margin   = 70,
439                 .upper_margin   = 38,
440                 .lower_margin   = 3,
441                 .hsync_len      = 80,
442                 .vsync_len      = 5,
443         },
444         {
445                 .name           = "1080i60",
446                 .timings_type   = VPBE_ENC_DV_TIMINGS,
447                 .dv_timings     = V4L2_DV_BT_CEA_1920X1080I60,
448                 .interlaced     = 1,
449                 .xres           = 1920,
450                 .yres           = 1080,
451                 .aspect         = {1, 1},
452                 .fps            = {30, 1},
453                 .left_margin    = 0xc9,
454                 .right_margin   = 80,
455                 .upper_margin   = 30,
456                 .lower_margin   = 3,
457                 .hsync_len      = 88,
458                 .vsync_len      = 5,
459         },
460 };
461 
462 #define VENC_STD_ALL    (V4L2_STD_NTSC | V4L2_STD_PAL)
463 
464 /*
465  * The outputs available from VPBE + ecnoders. Keep the
466  * the order same as that of encoders. First those from venc followed by that
467  * from encoders. Index in the output refers to index on a particular
468  * encoder.Driver uses this index to pass it to encoder when it supports more
469  * than one output. Application uses index of the array to set an output.
470  */
471 static struct vpbe_output dm365evm_vpbe_outputs[] = {
472         {
473                 .output         = {
474                         .index          = 0,
475                         .name           = "Composite",
476                         .type           = V4L2_OUTPUT_TYPE_ANALOG,
477                         .std            = VENC_STD_ALL,
478                         .capabilities   = V4L2_OUT_CAP_STD,
479                 },
480                 .subdev_name    = DM365_VPBE_VENC_SUBDEV_NAME,
481                 .default_mode   = "ntsc",
482                 .num_modes      = ARRAY_SIZE(dm365evm_enc_std_timing),
483                 .modes          = dm365evm_enc_std_timing,
484                 .if_params      = MEDIA_BUS_FMT_FIXED,
485         },
486         {
487                 .output         = {
488                         .index          = 1,
489                         .name           = "Component",
490                         .type           = V4L2_OUTPUT_TYPE_ANALOG,
491                         .capabilities   = V4L2_OUT_CAP_DV_TIMINGS,
492                 },
493                 .subdev_name    = DM365_VPBE_VENC_SUBDEV_NAME,
494                 .default_mode   = "480p59_94",
495                 .num_modes      = ARRAY_SIZE(dm365evm_enc_preset_timing),
496                 .modes          = dm365evm_enc_preset_timing,
497                 .if_params      = MEDIA_BUS_FMT_FIXED,
498         },
499 };
500 
501 /*
502  * Amplifiers on the board
503  */
504 static struct ths7303_platform_data ths7303_pdata = {
505         .ch_1 = 3,
506         .ch_2 = 3,
507         .ch_3 = 3,
508 };
509 
510 static struct amp_config_info vpbe_amp = {
511         .module_name    = "ths7303",
512         .is_i2c         = 1,
513         .board_info     = {
514                 I2C_BOARD_INFO("ths7303", 0x2c),
515                 .platform_data = &ths7303_pdata,
516         }
517 };
518 
519 static struct vpbe_config dm365evm_display_cfg = {
520         .module_name    = "dm365-vpbe-display",
521         .i2c_adapter_id = 1,
522         .amp            = &vpbe_amp,
523         .osd            = {
524                 .module_name    = DM365_VPBE_OSD_SUBDEV_NAME,
525         },
526         .venc           = {
527                 .module_name    = DM365_VPBE_VENC_SUBDEV_NAME,
528         },
529         .num_outputs    = ARRAY_SIZE(dm365evm_vpbe_outputs),
530         .outputs        = dm365evm_vpbe_outputs,
531 };
532 
533 static void __init evm_init_i2c(void)
534 {
535         davinci_init_i2c(&i2c_pdata);
536         i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
537 }
538 
539 static struct platform_device *dm365_evm_nand_devices[] __initdata = {
540         &davinci_nand_device,
541 };
542 
543 static inline int have_leds(void)
544 {
545 #ifdef CONFIG_LEDS_CLASS
546         return 1;
547 #else
548         return 0;
549 #endif
550 }
551 
552 struct cpld_led {
553         struct led_classdev     cdev;
554         u8                      mask;
555 };
556 
557 static const struct {
558         const char *name;
559         const char *trigger;
560 } cpld_leds[] = {
561         { "dm365evm::ds2", },
562         { "dm365evm::ds3", },
563         { "dm365evm::ds4", },
564         { "dm365evm::ds5", },
565         { "dm365evm::ds6", "nand-disk", },
566         { "dm365evm::ds7", "mmc1", },
567         { "dm365evm::ds8", "mmc0", },
568         { "dm365evm::ds9", "heartbeat", },
569 };
570 
571 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
572 {
573         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
574         u8 reg = __raw_readb(cpld + CPLD_LEDS);
575 
576         if (b != LED_OFF)
577                 reg &= ~led->mask;
578         else
579                 reg |= led->mask;
580         __raw_writeb(reg, cpld + CPLD_LEDS);
581 }
582 
583 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
584 {
585         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
586         u8 reg = __raw_readb(cpld + CPLD_LEDS);
587 
588         return (reg & led->mask) ? LED_OFF : LED_FULL;
589 }
590 
591 static int __init cpld_leds_init(void)
592 {
593         int     i;
594 
595         if (!have_leds() ||  !cpld)
596                 return 0;
597 
598         /* setup LEDs */
599         __raw_writeb(0xff, cpld + CPLD_LEDS);
600         for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
601                 struct cpld_led *led;
602 
603                 led = kzalloc(sizeof(*led), GFP_KERNEL);
604                 if (!led)
605                         break;
606 
607                 led->cdev.name = cpld_leds[i].name;
608                 led->cdev.brightness_set = cpld_led_set;
609                 led->cdev.brightness_get = cpld_led_get;
610                 led->cdev.default_trigger = cpld_leds[i].trigger;
611                 led->mask = BIT(i);
612 
613                 if (led_classdev_register(NULL, &led->cdev) < 0) {
614                         kfree(led);
615                         break;
616                 }
617         }
618 
619         return 0;
620 }
621 /* run after subsys_initcall() for LEDs */
622 fs_initcall(cpld_leds_init);
623 
624 
625 static void __init evm_init_cpld(void)
626 {
627         u8 mux, resets;
628         const char *label;
629         struct clk *aemif_clk;
630 
631         /* Make sure we can configure the CPLD through CS1.  Then
632          * leave it on for later access to MMC and LED registers.
633          */
634         aemif_clk = clk_get(NULL, "aemif");
635         if (IS_ERR(aemif_clk))
636                 return;
637         clk_prepare_enable(aemif_clk);
638 
639         if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
640                         "cpld") == NULL)
641                 goto fail;
642         cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
643         if (!cpld) {
644                 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
645                                 SECTION_SIZE);
646 fail:
647                 pr_err("ERROR: can't map CPLD\n");
648                 clk_disable_unprepare(aemif_clk);
649                 return;
650         }
651 
652         /* External muxing for some signals */
653         mux = 0;
654 
655         /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
656          * NOTE:  SW4 bus width setting must match!
657          */
658         if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
659                 /* external keypad mux */
660                 mux |= BIT(7);
661 
662                 platform_add_devices(dm365_evm_nand_devices,
663                                 ARRAY_SIZE(dm365_evm_nand_devices));
664         } else {
665                 /* no OneNAND support yet */
666         }
667 
668         /* Leave external chips in reset when unused. */
669         resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
670 
671         /* Static video input config with SN74CBT16214 1-of-3 mux:
672          *  - port b1 == tvp7002 (mux lowbits == 1 or 6)
673          *  - port b2 == imager (mux lowbits == 2 or 7)
674          *  - port b3 == tvp5146 (mux lowbits == 5)
675          *
676          * Runtime switching could work too, with limitations.
677          */
678         if (have_imager()) {
679                 label = "HD imager";
680                 mux |= 2;
681 
682                 /* externally mux MMC1/ENET/AIC33 to imager */
683                 mux |= BIT(6) | BIT(5) | BIT(3);
684         } else {
685                 struct davinci_soc_info *soc_info = &davinci_soc_info;
686 
687                 /* we can use MMC1 ... */
688                 dm365evm_mmc_configure();
689                 davinci_setup_mmc(1, &dm365evm_mmc_config);
690 
691                 /* ... and ENET ... */
692                 dm365evm_emac_configure();
693                 soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
694                 resets &= ~BIT(3);
695 
696                 /* ... and AIC33 */
697                 resets &= ~BIT(1);
698 
699                 if (have_tvp7002()) {
700                         mux |= 1;
701                         resets &= ~BIT(2);
702                         label = "tvp7002 HD";
703                 } else {
704                         /* default to tvp5146 */
705                         mux |= 5;
706                         resets &= ~BIT(0);
707                         label = "tvp5146 SD";
708                 }
709         }
710         __raw_writeb(mux, cpld + CPLD_MUX);
711         __raw_writeb(resets, cpld + CPLD_RESETS);
712         pr_info("EVM: %s video input\n", label);
713 
714         /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
715 }
716 
717 static void __init dm365_evm_map_io(void)
718 {
719         dm365_init();
720 }
721 
722 static struct spi_eeprom at25640 = {
723         .byte_len       = SZ_64K / 8,
724         .name           = "at25640",
725         .page_size      = 32,
726         .flags          = EE_ADDR2,
727 };
728 
729 static struct spi_board_info dm365_evm_spi_info[] __initconst = {
730         {
731                 .modalias       = "at25",
732                 .platform_data  = &at25640,
733                 .max_speed_hz   = 10 * 1000 * 1000,
734                 .bus_num        = 0,
735                 .chip_select    = 0,
736                 .mode           = SPI_MODE_0,
737         },
738 };
739 
740 static __init void dm365_evm_init(void)
741 {
742         int ret;
743 
744         ret = dm365_gpio_register();
745         if (ret)
746                 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
747 
748         evm_init_i2c();
749         davinci_serial_init(dm365_serial_device);
750 
751         dm365evm_emac_configure();
752         dm365evm_mmc_configure();
753 
754         davinci_setup_mmc(0, &dm365evm_mmc_config);
755 
756         dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
757 
758         /* maybe setup mmc1/etc ... _after_ mmc0 */
759         evm_init_cpld();
760 
761 #ifdef CONFIG_SND_DM365_AIC3X_CODEC
762         dm365_init_asp();
763 #elif defined(CONFIG_SND_DM365_VOICE_CODEC)
764         dm365_init_vc();
765 #endif
766         dm365_init_rtc();
767         dm365_init_ks(&dm365evm_ks_data);
768 
769         dm365_init_spi0(BIT(0), dm365_evm_spi_info,
770                         ARRAY_SIZE(dm365_evm_spi_info));
771 }
772 
773 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
774         .atag_offset    = 0x100,
775         .map_io         = dm365_evm_map_io,
776         .init_irq       = davinci_irq_init,
777         .init_time      = davinci_timer_init,
778         .init_machine   = dm365_evm_init,
779         .init_late      = davinci_init_late,
780         .dma_zone_size  = SZ_128M,
781         .restart        = davinci_restart,
782 MACHINE_END
783 
784 

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