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Linux/arch/arm/mach-davinci/board-mityomapl138.c

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  1 /*
  2  * Critical Link MityOMAP-L138 SoM
  3  *
  4  * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
  5  *
  6  * This file is licensed under the terms of the GNU General Public License
  7  * version 2. This program is licensed "as is" without any warranty of
  8  * any kind, whether express or implied.
  9  */
 10 
 11 #include <linux/kernel.h>
 12 #include <linux/init.h>
 13 #include <linux/console.h>
 14 #include <linux/platform_device.h>
 15 #include <linux/mtd/partitions.h>
 16 #include <linux/regulator/machine.h>
 17 #include <linux/i2c.h>
 18 #include <linux/i2c/at24.h>
 19 #include <linux/etherdevice.h>
 20 #include <linux/spi/spi.h>
 21 #include <linux/spi/flash.h>
 22 
 23 #include <asm/io.h>
 24 #include <asm/mach-types.h>
 25 #include <asm/mach/arch.h>
 26 #include <mach/common.h>
 27 #include <mach/cp_intc.h>
 28 #include <mach/da8xx.h>
 29 #include <mach/nand.h>
 30 #include <mach/mux.h>
 31 #include <mach/spi.h>
 32 
 33 #define MITYOMAPL138_PHY_ID             ""
 34 
 35 #define FACTORY_CONFIG_MAGIC    0x012C0138
 36 #define FACTORY_CONFIG_VERSION  0x00010001
 37 
 38 /* Data Held in On-Board I2C device */
 39 struct factory_config {
 40         u32     magic;
 41         u32     version;
 42         u8      mac[6];
 43         u32     fpga_type;
 44         u32     spare;
 45         u32     serialnumber;
 46         char    partnum[32];
 47 };
 48 
 49 static struct factory_config factory_config;
 50 
 51 struct part_no_info {
 52         const char      *part_no;       /* part number string of interest */
 53         int             max_freq;       /* khz */
 54 };
 55 
 56 static struct part_no_info mityomapl138_pn_info[] = {
 57         {
 58                 .part_no        = "L138-C",
 59                 .max_freq       = 300000,
 60         },
 61         {
 62                 .part_no        = "L138-D",
 63                 .max_freq       = 375000,
 64         },
 65         {
 66                 .part_no        = "L138-F",
 67                 .max_freq       = 456000,
 68         },
 69         {
 70                 .part_no        = "1808-C",
 71                 .max_freq       = 300000,
 72         },
 73         {
 74                 .part_no        = "1808-D",
 75                 .max_freq       = 375000,
 76         },
 77         {
 78                 .part_no        = "1808-F",
 79                 .max_freq       = 456000,
 80         },
 81         {
 82                 .part_no        = "1810-D",
 83                 .max_freq       = 375000,
 84         },
 85 };
 86 
 87 #ifdef CONFIG_CPU_FREQ
 88 static void mityomapl138_cpufreq_init(const char *partnum)
 89 {
 90         int i, ret;
 91 
 92         for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
 93                 /*
 94                  * the part number has additional characters beyond what is
 95                  * stored in the table.  This information is not needed for
 96                  * determining the speed grade, and would require several
 97                  * more table entries.  Only check the first N characters
 98                  * for a match.
 99                  */
100                 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
101                              strlen(mityomapl138_pn_info[i].part_no))) {
102                         da850_max_speed = mityomapl138_pn_info[i].max_freq;
103                         break;
104                 }
105         }
106 
107         ret = da850_register_cpufreq("pll0_sysclk3");
108         if (ret)
109                 pr_warning("cpufreq registration failed: %d\n", ret);
110 }
111 #else
112 static void mityomapl138_cpufreq_init(const char *partnum) { }
113 #endif
114 
115 static void read_factory_config(struct memory_accessor *a, void *context)
116 {
117         int ret;
118         const char *partnum = NULL;
119         struct davinci_soc_info *soc_info = &davinci_soc_info;
120 
121         ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
122         if (ret != sizeof(struct factory_config)) {
123                 pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
124                                 ret);
125                 goto bad_config;
126         }
127 
128         if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
129                 pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
130                                 factory_config.magic);
131                 goto bad_config;
132         }
133 
134         if (factory_config.version != FACTORY_CONFIG_VERSION) {
135                 pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
136                                 factory_config.version);
137                 goto bad_config;
138         }
139 
140         pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
141         if (is_valid_ether_addr(factory_config.mac))
142                 memcpy(soc_info->emac_pdata->mac_addr,
143                         factory_config.mac, ETH_ALEN);
144         else
145                 pr_warning("MityOMAPL138: Invalid MAC found "
146                                 "in factory config block\n");
147 
148         partnum = factory_config.partnum;
149         pr_info("MityOMAPL138: Part Number = %s\n", partnum);
150 
151 bad_config:
152         /* default maximum speed is valid for all platforms */
153         mityomapl138_cpufreq_init(partnum);
154 }
155 
156 static struct at24_platform_data mityomapl138_fd_chip = {
157         .byte_len       = 256,
158         .page_size      = 8,
159         .flags          = AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
160         .setup          = read_factory_config,
161         .context        = NULL,
162 };
163 
164 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
165         .bus_freq       = 100,  /* kHz */
166         .bus_delay      = 0,    /* usec */
167 };
168 
169 /* TPS65023 voltage regulator support */
170 /* 1.2V Core */
171 static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
172         {
173                 .supply = "cvdd",
174         },
175 };
176 
177 /* 1.8V */
178 static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
179         {
180                 .supply = "usb0_vdda18",
181         },
182         {
183                 .supply = "usb1_vdda18",
184         },
185         {
186                 .supply = "ddr_dvdd18",
187         },
188         {
189                 .supply = "sata_vddr",
190         },
191 };
192 
193 /* 1.2V */
194 static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
195         {
196                 .supply = "sata_vdd",
197         },
198         {
199                 .supply = "usb_cvdd",
200         },
201         {
202                 .supply = "pll0_vdda",
203         },
204         {
205                 .supply = "pll1_vdda",
206         },
207 };
208 
209 /* 1.8V Aux LDO, not used */
210 static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
211         {
212                 .supply = "1.8v_aux",
213         },
214 };
215 
216 /* FPGA VCC Aux (2.5 or 3.3) LDO */
217 static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
218         {
219                 .supply = "vccaux",
220         },
221 };
222 
223 static struct regulator_init_data tps65023_regulator_data[] = {
224         /* dcdc1 */
225         {
226                 .constraints = {
227                         .min_uV = 1150000,
228                         .max_uV = 1350000,
229                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
230                                           REGULATOR_CHANGE_STATUS,
231                         .boot_on = 1,
232                 },
233                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
234                 .consumer_supplies = tps65023_dcdc1_consumers,
235         },
236         /* dcdc2 */
237         {
238                 .constraints = {
239                         .min_uV = 1800000,
240                         .max_uV = 1800000,
241                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
242                         .boot_on = 1,
243                 },
244                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
245                 .consumer_supplies = tps65023_dcdc2_consumers,
246         },
247         /* dcdc3 */
248         {
249                 .constraints = {
250                         .min_uV = 1200000,
251                         .max_uV = 1200000,
252                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
253                         .boot_on = 1,
254                 },
255                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
256                 .consumer_supplies = tps65023_dcdc3_consumers,
257         },
258         /* ldo1 */
259         {
260                 .constraints = {
261                         .min_uV = 1800000,
262                         .max_uV = 1800000,
263                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
264                         .boot_on = 1,
265                 },
266                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
267                 .consumer_supplies = tps65023_ldo1_consumers,
268         },
269         /* ldo2 */
270         {
271                 .constraints = {
272                         .min_uV = 2500000,
273                         .max_uV = 3300000,
274                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
275                                           REGULATOR_CHANGE_STATUS,
276                         .boot_on = 1,
277                 },
278                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
279                 .consumer_supplies = tps65023_ldo2_consumers,
280         },
281 };
282 
283 static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
284         {
285                 I2C_BOARD_INFO("tps65023", 0x48),
286                 .platform_data = &tps65023_regulator_data[0],
287         },
288         {
289                 I2C_BOARD_INFO("24c02", 0x50),
290                 .platform_data = &mityomapl138_fd_chip,
291         },
292 };
293 
294 static int __init pmic_tps65023_init(void)
295 {
296         return i2c_register_board_info(1, mityomap_tps65023_info,
297                                         ARRAY_SIZE(mityomap_tps65023_info));
298 }
299 
300 /*
301  * SPI Devices:
302  *      SPI1_CS0: 8M Flash ST-M25P64-VME6G
303  */
304 static struct mtd_partition spi_flash_partitions[] = {
305         [0] = {
306                 .name           = "ubl",
307                 .offset         = 0,
308                 .size           = SZ_64K,
309                 .mask_flags     = MTD_WRITEABLE,
310         },
311         [1] = {
312                 .name           = "u-boot",
313                 .offset         = MTDPART_OFS_APPEND,
314                 .size           = SZ_512K,
315                 .mask_flags     = MTD_WRITEABLE,
316         },
317         [2] = {
318                 .name           = "u-boot-env",
319                 .offset         = MTDPART_OFS_APPEND,
320                 .size           = SZ_64K,
321                 .mask_flags     = MTD_WRITEABLE,
322         },
323         [3] = {
324                 .name           = "periph-config",
325                 .offset         = MTDPART_OFS_APPEND,
326                 .size           = SZ_64K,
327                 .mask_flags     = MTD_WRITEABLE,
328         },
329         [4] = {
330                 .name           = "reserved",
331                 .offset         = MTDPART_OFS_APPEND,
332                 .size           = SZ_256K + SZ_64K,
333         },
334         [5] = {
335                 .name           = "kernel",
336                 .offset         = MTDPART_OFS_APPEND,
337                 .size           = SZ_2M + SZ_1M,
338         },
339         [6] = {
340                 .name           = "fpga",
341                 .offset         = MTDPART_OFS_APPEND,
342                 .size           = SZ_2M,
343         },
344         [7] = {
345                 .name           = "spare",
346                 .offset         = MTDPART_OFS_APPEND,
347                 .size           = MTDPART_SIZ_FULL,
348         },
349 };
350 
351 static struct flash_platform_data mityomapl138_spi_flash_data = {
352         .name           = "m25p80",
353         .parts          = spi_flash_partitions,
354         .nr_parts       = ARRAY_SIZE(spi_flash_partitions),
355         .type           = "m24p64",
356 };
357 
358 static struct davinci_spi_config spi_eprom_config = {
359         .io_type        = SPI_IO_TYPE_DMA,
360         .c2tdelay       = 8,
361         .t2cdelay       = 8,
362 };
363 
364 static struct spi_board_info mityomapl138_spi_flash_info[] = {
365         {
366                 .modalias               = "m25p80",
367                 .platform_data          = &mityomapl138_spi_flash_data,
368                 .controller_data        = &spi_eprom_config,
369                 .mode                   = SPI_MODE_0,
370                 .max_speed_hz           = 30000000,
371                 .bus_num                = 1,
372                 .chip_select            = 0,
373         },
374 };
375 
376 /*
377  * MityDSP-L138 includes a 256 MByte large-page NAND flash
378  * (128K blocks).
379  */
380 static struct mtd_partition mityomapl138_nandflash_partition[] = {
381         {
382                 .name           = "rootfs",
383                 .offset         = 0,
384                 .size           = SZ_128M,
385                 .mask_flags     = 0, /* MTD_WRITEABLE, */
386         },
387         {
388                 .name           = "homefs",
389                 .offset         = MTDPART_OFS_APPEND,
390                 .size           = MTDPART_SIZ_FULL,
391                 .mask_flags     = 0,
392         },
393 };
394 
395 static struct davinci_nand_pdata mityomapl138_nandflash_data = {
396         .parts          = mityomapl138_nandflash_partition,
397         .nr_parts       = ARRAY_SIZE(mityomapl138_nandflash_partition),
398         .ecc_mode       = NAND_ECC_HW,
399         .bbt_options    = NAND_BBT_USE_FLASH,
400         .options        = NAND_BUSWIDTH_16,
401         .ecc_bits       = 1, /* 4 bit mode is not supported with 16 bit NAND */
402 };
403 
404 static struct resource mityomapl138_nandflash_resource[] = {
405         {
406                 .start  = DA8XX_AEMIF_CS3_BASE,
407                 .end    = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
408                 .flags  = IORESOURCE_MEM,
409         },
410         {
411                 .start  = DA8XX_AEMIF_CTL_BASE,
412                 .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
413                 .flags  = IORESOURCE_MEM,
414         },
415 };
416 
417 static struct platform_device mityomapl138_nandflash_device = {
418         .name           = "davinci_nand",
419         .id             = 1,
420         .dev            = {
421                 .platform_data  = &mityomapl138_nandflash_data,
422         },
423         .num_resources  = ARRAY_SIZE(mityomapl138_nandflash_resource),
424         .resource       = mityomapl138_nandflash_resource,
425 };
426 
427 static struct platform_device *mityomapl138_devices[] __initdata = {
428         &mityomapl138_nandflash_device,
429 };
430 
431 static void __init mityomapl138_setup_nand(void)
432 {
433         platform_add_devices(mityomapl138_devices,
434                                  ARRAY_SIZE(mityomapl138_devices));
435 }
436 
437 static struct davinci_uart_config mityomapl138_uart_config __initdata = {
438         .enabled_uarts = 0x7,
439 };
440 
441 static const short mityomap_mii_pins[] = {
442         DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
443         DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
444         DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
445         DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
446         DA850_MDIO_D,
447         -1
448 };
449 
450 static const short mityomap_rmii_pins[] = {
451         DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
452         DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
453         DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
454         DA850_MDIO_D,
455         -1
456 };
457 
458 static void __init mityomapl138_config_emac(void)
459 {
460         void __iomem *cfg_chip3_base;
461         int ret;
462         u32 val;
463         struct davinci_soc_info *soc_info = &davinci_soc_info;
464 
465         soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
466 
467         cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
468         val = __raw_readl(cfg_chip3_base);
469 
470         if (soc_info->emac_pdata->rmii_en) {
471                 val |= BIT(8);
472                 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
473                 pr_info("RMII PHY configured\n");
474         } else {
475                 val &= ~BIT(8);
476                 ret = davinci_cfg_reg_list(mityomap_mii_pins);
477                 pr_info("MII PHY configured\n");
478         }
479 
480         if (ret) {
481                 pr_warning("mii/rmii mux setup failed: %d\n", ret);
482                 return;
483         }
484 
485         /* configure the CFGCHIP3 register for RMII or MII */
486         __raw_writel(val, cfg_chip3_base);
487 
488         soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
489 
490         ret = da8xx_register_emac();
491         if (ret)
492                 pr_warning("emac registration failed: %d\n", ret);
493 }
494 
495 static struct davinci_pm_config da850_pm_pdata = {
496         .sleepcount = 128,
497 };
498 
499 static struct platform_device da850_pm_device = {
500         .name   = "pm-davinci",
501         .dev = {
502                 .platform_data  = &da850_pm_pdata,
503         },
504         .id     = -1,
505 };
506 
507 static void __init mityomapl138_init(void)
508 {
509         int ret;
510 
511         /* for now, no special EDMA channels are reserved */
512         ret = da850_register_edma(NULL);
513         if (ret)
514                 pr_warning("edma registration failed: %d\n", ret);
515 
516         ret = da8xx_register_watchdog();
517         if (ret)
518                 pr_warning("watchdog registration failed: %d\n", ret);
519 
520         davinci_serial_init(&mityomapl138_uart_config);
521 
522         ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
523         if (ret)
524                 pr_warning("i2c0 registration failed: %d\n", ret);
525 
526         ret = pmic_tps65023_init();
527         if (ret)
528                 pr_warning("TPS65023 PMIC init failed: %d\n", ret);
529 
530         mityomapl138_setup_nand();
531 
532         ret = da8xx_register_spi(1, mityomapl138_spi_flash_info,
533                                ARRAY_SIZE(mityomapl138_spi_flash_info));
534         if (ret)
535                 pr_warning("spi 1 registration failed: %d\n", ret);
536 
537         mityomapl138_config_emac();
538 
539         ret = da8xx_register_rtc();
540         if (ret)
541                 pr_warning("rtc setup failed: %d\n", ret);
542 
543         ret = da8xx_register_cpuidle();
544         if (ret)
545                 pr_warning("cpuidle registration failed: %d\n", ret);
546 
547         ret = da850_register_pm(&da850_pm_device);
548         if (ret)
549                 pr_warning("da850_evm_init: suspend registration failed: %d\n",
550                                 ret);
551 }
552 
553 #ifdef CONFIG_SERIAL_8250_CONSOLE
554 static int __init mityomapl138_console_init(void)
555 {
556         if (!machine_is_mityomapl138())
557                 return 0;
558 
559         return add_preferred_console("ttyS", 1, "115200");
560 }
561 console_initcall(mityomapl138_console_init);
562 #endif
563 
564 static void __init mityomapl138_map_io(void)
565 {
566         da850_init();
567 }
568 
569 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
570         .atag_offset    = 0x100,
571         .map_io         = mityomapl138_map_io,
572         .init_irq       = cp_intc_init,
573         .timer          = &davinci_timer,
574         .init_machine   = mityomapl138_init,
575         .init_late      = davinci_init_late,
576         .dma_zone_size  = SZ_128M,
577         .restart        = da8xx_restart,
578 MACHINE_END
579 

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