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Linux/arch/arm/mach-davinci/board-mityomapl138.c

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  1 /*
  2  * Critical Link MityOMAP-L138 SoM
  3  *
  4  * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
  5  *
  6  * This file is licensed under the terms of the GNU General Public License
  7  * version 2. This program is licensed "as is" without any warranty of
  8  * any kind, whether express or implied.
  9  */
 10 
 11 #define pr_fmt(fmt) "MityOMAPL138: " fmt
 12 
 13 #include <linux/kernel.h>
 14 #include <linux/init.h>
 15 #include <linux/console.h>
 16 #include <linux/platform_device.h>
 17 #include <linux/mtd/partitions.h>
 18 #include <linux/regulator/machine.h>
 19 #include <linux/i2c.h>
 20 #include <linux/platform_data/at24.h>
 21 #include <linux/etherdevice.h>
 22 #include <linux/spi/spi.h>
 23 #include <linux/spi/flash.h>
 24 
 25 #include <asm/io.h>
 26 #include <asm/mach-types.h>
 27 #include <asm/mach/arch.h>
 28 #include <mach/common.h>
 29 #include "cp_intc.h"
 30 #include <mach/da8xx.h>
 31 #include <linux/platform_data/mtd-davinci.h>
 32 #include <linux/platform_data/mtd-davinci-aemif.h>
 33 #include <mach/mux.h>
 34 #include <linux/platform_data/spi-davinci.h>
 35 
 36 #define MITYOMAPL138_PHY_ID             ""
 37 
 38 #define FACTORY_CONFIG_MAGIC    0x012C0138
 39 #define FACTORY_CONFIG_VERSION  0x00010001
 40 
 41 /* Data Held in On-Board I2C device */
 42 struct factory_config {
 43         u32     magic;
 44         u32     version;
 45         u8      mac[6];
 46         u32     fpga_type;
 47         u32     spare;
 48         u32     serialnumber;
 49         char    partnum[32];
 50 };
 51 
 52 static struct factory_config factory_config;
 53 
 54 #ifdef CONFIG_CPU_FREQ
 55 struct part_no_info {
 56         const char      *part_no;       /* part number string of interest */
 57         int             max_freq;       /* khz */
 58 };
 59 
 60 static struct part_no_info mityomapl138_pn_info[] = {
 61         {
 62                 .part_no        = "L138-C",
 63                 .max_freq       = 300000,
 64         },
 65         {
 66                 .part_no        = "L138-D",
 67                 .max_freq       = 375000,
 68         },
 69         {
 70                 .part_no        = "L138-F",
 71                 .max_freq       = 456000,
 72         },
 73         {
 74                 .part_no        = "1808-C",
 75                 .max_freq       = 300000,
 76         },
 77         {
 78                 .part_no        = "1808-D",
 79                 .max_freq       = 375000,
 80         },
 81         {
 82                 .part_no        = "1808-F",
 83                 .max_freq       = 456000,
 84         },
 85         {
 86                 .part_no        = "1810-D",
 87                 .max_freq       = 375000,
 88         },
 89 };
 90 
 91 static void mityomapl138_cpufreq_init(const char *partnum)
 92 {
 93         int i, ret;
 94 
 95         for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
 96                 /*
 97                  * the part number has additional characters beyond what is
 98                  * stored in the table.  This information is not needed for
 99                  * determining the speed grade, and would require several
100                  * more table entries.  Only check the first N characters
101                  * for a match.
102                  */
103                 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
104                              strlen(mityomapl138_pn_info[i].part_no))) {
105                         da850_max_speed = mityomapl138_pn_info[i].max_freq;
106                         break;
107                 }
108         }
109 
110         ret = da850_register_cpufreq("pll0_sysclk3");
111         if (ret)
112                 pr_warn("cpufreq registration failed: %d\n", ret);
113 }
114 #else
115 static void mityomapl138_cpufreq_init(const char *partnum) { }
116 #endif
117 
118 static void read_factory_config(struct nvmem_device *nvmem, void *context)
119 {
120         int ret;
121         const char *partnum = NULL;
122         struct davinci_soc_info *soc_info = &davinci_soc_info;
123 
124         if (!IS_BUILTIN(CONFIG_NVMEM)) {
125                 pr_warn("Factory Config not available without CONFIG_NVMEM\n");
126                 goto bad_config;
127         }
128 
129         ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
130                                 &factory_config);
131         if (ret != sizeof(struct factory_config)) {
132                 pr_warn("Read Factory Config Failed: %d\n", ret);
133                 goto bad_config;
134         }
135 
136         if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
137                 pr_warn("Factory Config Magic Wrong (%X)\n",
138                         factory_config.magic);
139                 goto bad_config;
140         }
141 
142         if (factory_config.version != FACTORY_CONFIG_VERSION) {
143                 pr_warn("Factory Config Version Wrong (%X)\n",
144                         factory_config.version);
145                 goto bad_config;
146         }
147 
148         pr_info("Found MAC = %pM\n", factory_config.mac);
149         if (is_valid_ether_addr(factory_config.mac))
150                 memcpy(soc_info->emac_pdata->mac_addr,
151                         factory_config.mac, ETH_ALEN);
152         else
153                 pr_warn("Invalid MAC found in factory config block\n");
154 
155         partnum = factory_config.partnum;
156         pr_info("Part Number = %s\n", partnum);
157 
158 bad_config:
159         /* default maximum speed is valid for all platforms */
160         mityomapl138_cpufreq_init(partnum);
161 }
162 
163 static struct at24_platform_data mityomapl138_fd_chip = {
164         .byte_len       = 256,
165         .page_size      = 8,
166         .flags          = AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
167         .setup          = read_factory_config,
168         .context        = NULL,
169 };
170 
171 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
172         .bus_freq       = 100,  /* kHz */
173         .bus_delay      = 0,    /* usec */
174 };
175 
176 /* TPS65023 voltage regulator support */
177 /* 1.2V Core */
178 static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
179         {
180                 .supply = "cvdd",
181         },
182 };
183 
184 /* 1.8V */
185 static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
186         {
187                 .supply = "usb0_vdda18",
188         },
189         {
190                 .supply = "usb1_vdda18",
191         },
192         {
193                 .supply = "ddr_dvdd18",
194         },
195         {
196                 .supply = "sata_vddr",
197         },
198 };
199 
200 /* 1.2V */
201 static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
202         {
203                 .supply = "sata_vdd",
204         },
205         {
206                 .supply = "usb_cvdd",
207         },
208         {
209                 .supply = "pll0_vdda",
210         },
211         {
212                 .supply = "pll1_vdda",
213         },
214 };
215 
216 /* 1.8V Aux LDO, not used */
217 static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
218         {
219                 .supply = "1.8v_aux",
220         },
221 };
222 
223 /* FPGA VCC Aux (2.5 or 3.3) LDO */
224 static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
225         {
226                 .supply = "vccaux",
227         },
228 };
229 
230 static struct regulator_init_data tps65023_regulator_data[] = {
231         /* dcdc1 */
232         {
233                 .constraints = {
234                         .min_uV = 1150000,
235                         .max_uV = 1350000,
236                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
237                                           REGULATOR_CHANGE_STATUS,
238                         .boot_on = 1,
239                 },
240                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
241                 .consumer_supplies = tps65023_dcdc1_consumers,
242         },
243         /* dcdc2 */
244         {
245                 .constraints = {
246                         .min_uV = 1800000,
247                         .max_uV = 1800000,
248                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
249                         .boot_on = 1,
250                 },
251                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
252                 .consumer_supplies = tps65023_dcdc2_consumers,
253         },
254         /* dcdc3 */
255         {
256                 .constraints = {
257                         .min_uV = 1200000,
258                         .max_uV = 1200000,
259                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
260                         .boot_on = 1,
261                 },
262                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
263                 .consumer_supplies = tps65023_dcdc3_consumers,
264         },
265         /* ldo1 */
266         {
267                 .constraints = {
268                         .min_uV = 1800000,
269                         .max_uV = 1800000,
270                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
271                         .boot_on = 1,
272                 },
273                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
274                 .consumer_supplies = tps65023_ldo1_consumers,
275         },
276         /* ldo2 */
277         {
278                 .constraints = {
279                         .min_uV = 2500000,
280                         .max_uV = 3300000,
281                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
282                                           REGULATOR_CHANGE_STATUS,
283                         .boot_on = 1,
284                 },
285                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
286                 .consumer_supplies = tps65023_ldo2_consumers,
287         },
288 };
289 
290 static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
291         {
292                 I2C_BOARD_INFO("tps65023", 0x48),
293                 .platform_data = &tps65023_regulator_data[0],
294         },
295         {
296                 I2C_BOARD_INFO("24c02", 0x50),
297                 .platform_data = &mityomapl138_fd_chip,
298         },
299 };
300 
301 static int __init pmic_tps65023_init(void)
302 {
303         return i2c_register_board_info(1, mityomap_tps65023_info,
304                                         ARRAY_SIZE(mityomap_tps65023_info));
305 }
306 
307 /*
308  * SPI Devices:
309  *      SPI1_CS0: 8M Flash ST-M25P64-VME6G
310  */
311 static struct mtd_partition spi_flash_partitions[] = {
312         [0] = {
313                 .name           = "ubl",
314                 .offset         = 0,
315                 .size           = SZ_64K,
316                 .mask_flags     = MTD_WRITEABLE,
317         },
318         [1] = {
319                 .name           = "u-boot",
320                 .offset         = MTDPART_OFS_APPEND,
321                 .size           = SZ_512K,
322                 .mask_flags     = MTD_WRITEABLE,
323         },
324         [2] = {
325                 .name           = "u-boot-env",
326                 .offset         = MTDPART_OFS_APPEND,
327                 .size           = SZ_64K,
328                 .mask_flags     = MTD_WRITEABLE,
329         },
330         [3] = {
331                 .name           = "periph-config",
332                 .offset         = MTDPART_OFS_APPEND,
333                 .size           = SZ_64K,
334                 .mask_flags     = MTD_WRITEABLE,
335         },
336         [4] = {
337                 .name           = "reserved",
338                 .offset         = MTDPART_OFS_APPEND,
339                 .size           = SZ_256K + SZ_64K,
340         },
341         [5] = {
342                 .name           = "kernel",
343                 .offset         = MTDPART_OFS_APPEND,
344                 .size           = SZ_2M + SZ_1M,
345         },
346         [6] = {
347                 .name           = "fpga",
348                 .offset         = MTDPART_OFS_APPEND,
349                 .size           = SZ_2M,
350         },
351         [7] = {
352                 .name           = "spare",
353                 .offset         = MTDPART_OFS_APPEND,
354                 .size           = MTDPART_SIZ_FULL,
355         },
356 };
357 
358 static struct flash_platform_data mityomapl138_spi_flash_data = {
359         .name           = "m25p80",
360         .parts          = spi_flash_partitions,
361         .nr_parts       = ARRAY_SIZE(spi_flash_partitions),
362         .type           = "m24p64",
363 };
364 
365 static struct davinci_spi_config spi_eprom_config = {
366         .io_type        = SPI_IO_TYPE_DMA,
367         .c2tdelay       = 8,
368         .t2cdelay       = 8,
369 };
370 
371 static struct spi_board_info mityomapl138_spi_flash_info[] = {
372         {
373                 .modalias               = "m25p80",
374                 .platform_data          = &mityomapl138_spi_flash_data,
375                 .controller_data        = &spi_eprom_config,
376                 .mode                   = SPI_MODE_0,
377                 .max_speed_hz           = 30000000,
378                 .bus_num                = 1,
379                 .chip_select            = 0,
380         },
381 };
382 
383 /*
384  * MityDSP-L138 includes a 256 MByte large-page NAND flash
385  * (128K blocks).
386  */
387 static struct mtd_partition mityomapl138_nandflash_partition[] = {
388         {
389                 .name           = "rootfs",
390                 .offset         = 0,
391                 .size           = SZ_128M,
392                 .mask_flags     = 0, /* MTD_WRITEABLE, */
393         },
394         {
395                 .name           = "homefs",
396                 .offset         = MTDPART_OFS_APPEND,
397                 .size           = MTDPART_SIZ_FULL,
398                 .mask_flags     = 0,
399         },
400 };
401 
402 static struct davinci_nand_pdata mityomapl138_nandflash_data = {
403         .parts          = mityomapl138_nandflash_partition,
404         .nr_parts       = ARRAY_SIZE(mityomapl138_nandflash_partition),
405         .ecc_mode       = NAND_ECC_HW,
406         .bbt_options    = NAND_BBT_USE_FLASH,
407         .options        = NAND_BUSWIDTH_16,
408         .ecc_bits       = 1, /* 4 bit mode is not supported with 16 bit NAND */
409 };
410 
411 static struct resource mityomapl138_nandflash_resource[] = {
412         {
413                 .start  = DA8XX_AEMIF_CS3_BASE,
414                 .end    = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
415                 .flags  = IORESOURCE_MEM,
416         },
417         {
418                 .start  = DA8XX_AEMIF_CTL_BASE,
419                 .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
420                 .flags  = IORESOURCE_MEM,
421         },
422 };
423 
424 static struct platform_device mityomapl138_nandflash_device = {
425         .name           = "davinci_nand",
426         .id             = 1,
427         .dev            = {
428                 .platform_data  = &mityomapl138_nandflash_data,
429         },
430         .num_resources  = ARRAY_SIZE(mityomapl138_nandflash_resource),
431         .resource       = mityomapl138_nandflash_resource,
432 };
433 
434 static struct platform_device *mityomapl138_devices[] __initdata = {
435         &mityomapl138_nandflash_device,
436 };
437 
438 static void __init mityomapl138_setup_nand(void)
439 {
440         platform_add_devices(mityomapl138_devices,
441                                  ARRAY_SIZE(mityomapl138_devices));
442 
443         if (davinci_aemif_setup(&mityomapl138_nandflash_device))
444                 pr_warn("%s: Cannot configure AEMIF\n", __func__);
445 }
446 
447 static const short mityomap_mii_pins[] = {
448         DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
449         DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
450         DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
451         DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
452         DA850_MDIO_D,
453         -1
454 };
455 
456 static const short mityomap_rmii_pins[] = {
457         DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
458         DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
459         DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
460         DA850_MDIO_D,
461         -1
462 };
463 
464 static void __init mityomapl138_config_emac(void)
465 {
466         void __iomem *cfg_chip3_base;
467         int ret;
468         u32 val;
469         struct davinci_soc_info *soc_info = &davinci_soc_info;
470 
471         soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
472 
473         cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
474         val = __raw_readl(cfg_chip3_base);
475 
476         if (soc_info->emac_pdata->rmii_en) {
477                 val |= BIT(8);
478                 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
479                 pr_info("RMII PHY configured\n");
480         } else {
481                 val &= ~BIT(8);
482                 ret = davinci_cfg_reg_list(mityomap_mii_pins);
483                 pr_info("MII PHY configured\n");
484         }
485 
486         if (ret) {
487                 pr_warn("mii/rmii mux setup failed: %d\n", ret);
488                 return;
489         }
490 
491         /* configure the CFGCHIP3 register for RMII or MII */
492         __raw_writel(val, cfg_chip3_base);
493 
494         soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
495 
496         ret = da8xx_register_emac();
497         if (ret)
498                 pr_warn("emac registration failed: %d\n", ret);
499 }
500 
501 static void __init mityomapl138_init(void)
502 {
503         int ret;
504 
505         ret = da8xx_register_cfgchip();
506         if (ret)
507                 pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
508 
509         /* for now, no special EDMA channels are reserved */
510         ret = da850_register_edma(NULL);
511         if (ret)
512                 pr_warn("edma registration failed: %d\n", ret);
513 
514         ret = da8xx_register_watchdog();
515         if (ret)
516                 pr_warn("watchdog registration failed: %d\n", ret);
517 
518         davinci_serial_init(da8xx_serial_device);
519 
520         ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
521         if (ret)
522                 pr_warn("i2c0 registration failed: %d\n", ret);
523 
524         ret = pmic_tps65023_init();
525         if (ret)
526                 pr_warn("TPS65023 PMIC init failed: %d\n", ret);
527 
528         mityomapl138_setup_nand();
529 
530         ret = spi_register_board_info(mityomapl138_spi_flash_info,
531                                       ARRAY_SIZE(mityomapl138_spi_flash_info));
532         if (ret)
533                 pr_warn("spi info registration failed: %d\n", ret);
534 
535         ret = da8xx_register_spi_bus(1,
536                                      ARRAY_SIZE(mityomapl138_spi_flash_info));
537         if (ret)
538                 pr_warn("spi 1 registration failed: %d\n", ret);
539 
540         mityomapl138_config_emac();
541 
542         ret = da8xx_register_rtc();
543         if (ret)
544                 pr_warn("rtc setup failed: %d\n", ret);
545 
546         ret = da8xx_register_cpuidle();
547         if (ret)
548                 pr_warn("cpuidle registration failed: %d\n", ret);
549 
550         davinci_pm_init();
551 }
552 
553 #ifdef CONFIG_SERIAL_8250_CONSOLE
554 static int __init mityomapl138_console_init(void)
555 {
556         if (!machine_is_mityomapl138())
557                 return 0;
558 
559         return add_preferred_console("ttyS", 1, "115200");
560 }
561 console_initcall(mityomapl138_console_init);
562 #endif
563 
564 static void __init mityomapl138_map_io(void)
565 {
566         da850_init();
567 }
568 
569 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
570         .atag_offset    = 0x100,
571         .map_io         = mityomapl138_map_io,
572         .init_irq       = cp_intc_init,
573         .init_time      = davinci_timer_init,
574         .init_machine   = mityomapl138_init,
575         .init_late      = davinci_init_late,
576         .dma_zone_size  = SZ_128M,
577         .restart        = da8xx_restart,
578 MACHINE_END
579 

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