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Linux/arch/arm/mach-davinci/board-neuros-osd2.c

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  1 /*
  2  * Neuros Technologies OSD2 board support
  3  *
  4  * Modified from original 644X-EVM board support.
  5  * 2008 (c) Neuros Technology, LLC.
  6  * 2009 (c) Jorge Luis Zapata Muga <jorgeluis.zapata@gmail.com>
  7  * 2009 (c) Andrey A. Porodko <Andrey.Porodko@gmail.com>
  8  *
  9  * The Neuros OSD 2.0 is the hardware component of the Neuros Open
 10  * Internet Television Platform. Hardware is very close to TI
 11  * DM644X-EVM board. It has:
 12  *      DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
 13  *      USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
 14  *      Additionally realtime clock, IR remote control receiver,
 15  *      IR Blaster based on MSP430 (firmware although is different
 16  *      from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
 17  *      with PATA interface, two muxed red-green leds.
 18  *
 19  * For more information please refer to
 20  *              http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
 21  *
 22  * This file is licensed under the terms of the GNU General Public
 23  * License version 2. This program is licensed "as is" without any
 24  * warranty of any kind, whether express or implied.
 25  */
 26 #include <linux/platform_device.h>
 27 #include <linux/gpio.h>
 28 #include <linux/mtd/partitions.h>
 29 #include <linux/platform_data/gpio-davinci.h>
 30 #include <linux/platform_data/i2c-davinci.h>
 31 #include <linux/platform_data/mmc-davinci.h>
 32 #include <linux/platform_data/mtd-davinci.h>
 33 #include <linux/platform_data/usb-davinci.h>
 34 
 35 #include <asm/mach-types.h>
 36 #include <asm/mach/arch.h>
 37 
 38 #include <mach/common.h>
 39 #include <mach/serial.h>
 40 #include <mach/mux.h>
 41 
 42 #include "davinci.h"
 43 
 44 #define NEUROS_OSD2_PHY_ID              "davinci_mdio-0:01"
 45 #define LXT971_PHY_ID                   0x001378e2
 46 #define LXT971_PHY_MASK                 0xfffffff0
 47 
 48 #define NTOSD2_AUDIOSOC_I2C_ADDR        0x18
 49 #define NTOSD2_MSP430_I2C_ADDR          0x59
 50 #define NTOSD2_MSP430_IRQ               2
 51 
 52 /* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
 53  * 2048 blocks in the device, 64 pages per block, 2048 bytes per
 54  * page.
 55  */
 56 
 57 #define NAND_BLOCK_SIZE         SZ_128K
 58 
 59 static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
 60         {
 61                 /* UBL (a few copies) plus U-Boot */
 62                 .name           = "bootloader",
 63                 .offset         = 0,
 64                 .size           = 15 * NAND_BLOCK_SIZE,
 65                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 66         }, {
 67                 /* U-Boot environment */
 68                 .name           = "params",
 69                 .offset         = MTDPART_OFS_APPEND,
 70                 .size           = 1 * NAND_BLOCK_SIZE,
 71                 .mask_flags     = 0,
 72         }, {
 73                 /* Kernel */
 74                 .name           = "kernel",
 75                 .offset         = MTDPART_OFS_APPEND,
 76                 .size           = SZ_4M,
 77                 .mask_flags     = 0,
 78         }, {
 79                 /* File System */
 80                 .name           = "filesystem",
 81                 .offset         = MTDPART_OFS_APPEND,
 82                 .size           = MTDPART_SIZ_FULL,
 83                 .mask_flags     = 0,
 84         }
 85         /* A few blocks at end hold a flash Bad Block Table. */
 86 };
 87 
 88 static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
 89         .parts          = davinci_ntosd2_nandflash_partition,
 90         .nr_parts       = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
 91         .ecc_mode       = NAND_ECC_HW,
 92         .ecc_bits       = 1,
 93         .bbt_options    = NAND_BBT_USE_FLASH,
 94 };
 95 
 96 static struct resource davinci_ntosd2_nandflash_resource[] = {
 97         {
 98                 .start          = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
 99                 .end            = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
100                 .flags          = IORESOURCE_MEM,
101         }, {
102                 .start          = DM644X_ASYNC_EMIF_CONTROL_BASE,
103                 .end            = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
104                 .flags          = IORESOURCE_MEM,
105         },
106 };
107 
108 static struct platform_device davinci_ntosd2_nandflash_device = {
109         .name           = "davinci_nand",
110         .id             = 0,
111         .dev            = {
112                 .platform_data  = &davinci_ntosd2_nandflash_data,
113         },
114         .num_resources  = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
115         .resource       = davinci_ntosd2_nandflash_resource,
116 };
117 
118 static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
119 
120 static struct platform_device davinci_fb_device = {
121         .name           = "davincifb",
122         .id             = -1,
123         .dev = {
124                 .dma_mask               = &davinci_fb_dma_mask,
125                 .coherent_dma_mask      = DMA_BIT_MASK(32),
126         },
127         .num_resources = 0,
128 };
129 
130 static struct snd_platform_data dm644x_ntosd2_snd_data;
131 
132 static struct gpio_led ntosd2_leds[] = {
133         { .name = "led1_green", .gpio = GPIO(10), },
134         { .name = "led1_red",   .gpio = GPIO(11), },
135         { .name = "led2_green", .gpio = GPIO(12), },
136         { .name = "led2_red",   .gpio = GPIO(13), },
137 };
138 
139 static struct gpio_led_platform_data ntosd2_leds_data = {
140         .num_leds       = ARRAY_SIZE(ntosd2_leds),
141         .leds           = ntosd2_leds,
142 };
143 
144 static struct platform_device ntosd2_leds_dev = {
145         .name = "leds-gpio",
146         .id   = -1,
147         .dev = {
148                 .platform_data          = &ntosd2_leds_data,
149         },
150 };
151 
152 
153 static struct platform_device *davinci_ntosd2_devices[] __initdata = {
154         &davinci_fb_device,
155         &ntosd2_leds_dev,
156 };
157 
158 static void __init davinci_ntosd2_map_io(void)
159 {
160         dm644x_init();
161 }
162 
163 static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
164         .wires          = 4,
165 };
166 
167 #define HAS_ATA         IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
168 
169 #define HAS_NAND        IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
170 
171 static __init void davinci_ntosd2_init(void)
172 {
173         int ret;
174         struct clk *aemif_clk;
175         struct davinci_soc_info *soc_info = &davinci_soc_info;
176 
177         ret = dm644x_gpio_register();
178         if (ret)
179                 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
180 
181         aemif_clk = clk_get(NULL, "aemif");
182         clk_prepare_enable(aemif_clk);
183 
184         if (HAS_ATA) {
185                 if (HAS_NAND)
186                         pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
187                                 "\tDisable IDE for NAND/NOR support\n");
188                 davinci_init_ide();
189         } else if (HAS_NAND) {
190                 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
191                 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
192 
193                 /* only one device will be jumpered and detected */
194                 if (HAS_NAND)
195                         platform_device_register(
196                                         &davinci_ntosd2_nandflash_device);
197         }
198 
199         platform_add_devices(davinci_ntosd2_devices,
200                                 ARRAY_SIZE(davinci_ntosd2_devices));
201 
202         davinci_serial_init(dm644x_serial_device);
203         dm644x_init_asp(&dm644x_ntosd2_snd_data);
204 
205         soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID;
206 
207         davinci_setup_usb(1000, 8);
208         /*
209          * Mux the pins to be GPIOs, VLYNQEN is already done at startup.
210          * The AEAWx are five new AEAW pins that can be muxed by separately.
211          * They are a bitmask for GPIO management. According TI
212          * documentation (http://www.ti.com/lit/gpn/tms320dm6446) to employ
213          * gpio(10,11,12,13) for leds any combination of bits works except
214          * four last. So we are to reset all five.
215          */
216         davinci_cfg_reg(DM644X_AEAW0);
217         davinci_cfg_reg(DM644X_AEAW1);
218         davinci_cfg_reg(DM644X_AEAW2);
219         davinci_cfg_reg(DM644X_AEAW3);
220         davinci_cfg_reg(DM644X_AEAW4);
221 
222         davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
223 }
224 
225 MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
226         /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
227         .atag_offset    = 0x100,
228         .map_io          = davinci_ntosd2_map_io,
229         .init_irq       = davinci_irq_init,
230         .init_time      = davinci_timer_init,
231         .init_machine = davinci_ntosd2_init,
232         .init_late      = davinci_init_late,
233         .dma_zone_size  = SZ_128M,
234         .restart        = davinci_restart,
235 MACHINE_END
236 

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