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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-davinci/dm365.c

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  1 /*
  2  * TI DaVinci DM365 chip specific setup
  3  *
  4  * Copyright (C) 2009 Texas Instruments
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License as
  8  * published by the Free Software Foundation version 2.
  9  *
 10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 11  * kind, whether express or implied; without even the implied warranty
 12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 #include <linux/init.h>
 16 #include <linux/clk.h>
 17 #include <linux/serial_8250.h>
 18 #include <linux/platform_device.h>
 19 #include <linux/dma-mapping.h>
 20 #include <linux/dmaengine.h>
 21 #include <linux/spi/spi.h>
 22 #include <linux/platform_data/edma.h>
 23 #include <linux/platform_data/gpio-davinci.h>
 24 #include <linux/platform_data/keyscan-davinci.h>
 25 #include <linux/platform_data/spi-davinci.h>
 26 
 27 #include <asm/mach/map.h>
 28 
 29 #include <mach/cputype.h>
 30 #include "psc.h"
 31 #include <mach/mux.h>
 32 #include <mach/irqs.h>
 33 #include <mach/time.h>
 34 #include <mach/serial.h>
 35 #include <mach/common.h>
 36 
 37 #include "davinci.h"
 38 #include "clock.h"
 39 #include "mux.h"
 40 #include "asp.h"
 41 
 42 #define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
 43 #define DM365_RTC_BASE                  0x01c69000
 44 #define DM365_KEYSCAN_BASE              0x01c69400
 45 #define DM365_OSD_BASE                  0x01c71c00
 46 #define DM365_VENC_BASE                 0x01c71e00
 47 #define DAVINCI_DM365_VC_BASE           0x01d0c000
 48 #define DAVINCI_DMA_VC_TX               2
 49 #define DAVINCI_DMA_VC_RX               3
 50 #define DM365_EMAC_BASE                 0x01d07000
 51 #define DM365_EMAC_MDIO_BASE            (DM365_EMAC_BASE + 0x4000)
 52 #define DM365_EMAC_CNTRL_OFFSET         0x0000
 53 #define DM365_EMAC_CNTRL_MOD_OFFSET     0x3000
 54 #define DM365_EMAC_CNTRL_RAM_OFFSET     0x1000
 55 #define DM365_EMAC_CNTRL_RAM_SIZE       0x2000
 56 
 57 static struct pll_data pll1_data = {
 58         .num            = 1,
 59         .phys_base      = DAVINCI_PLL1_BASE,
 60         .flags          = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
 61 };
 62 
 63 static struct pll_data pll2_data = {
 64         .num            = 2,
 65         .phys_base      = DAVINCI_PLL2_BASE,
 66         .flags          = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
 67 };
 68 
 69 static struct clk ref_clk = {
 70         .name           = "ref_clk",
 71         .rate           = DM365_REF_FREQ,
 72 };
 73 
 74 static struct clk pll1_clk = {
 75         .name           = "pll1",
 76         .parent         = &ref_clk,
 77         .flags          = CLK_PLL,
 78         .pll_data       = &pll1_data,
 79 };
 80 
 81 static struct clk pll1_aux_clk = {
 82         .name           = "pll1_aux_clk",
 83         .parent         = &pll1_clk,
 84         .flags          = CLK_PLL | PRE_PLL,
 85 };
 86 
 87 static struct clk pll1_sysclkbp = {
 88         .name           = "pll1_sysclkbp",
 89         .parent         = &pll1_clk,
 90         .flags          = CLK_PLL | PRE_PLL,
 91         .div_reg        = BPDIV
 92 };
 93 
 94 static struct clk clkout0_clk = {
 95         .name           = "clkout0",
 96         .parent         = &pll1_clk,
 97         .flags          = CLK_PLL | PRE_PLL,
 98 };
 99 
100 static struct clk pll1_sysclk1 = {
101         .name           = "pll1_sysclk1",
102         .parent         = &pll1_clk,
103         .flags          = CLK_PLL,
104         .div_reg        = PLLDIV1,
105 };
106 
107 static struct clk pll1_sysclk2 = {
108         .name           = "pll1_sysclk2",
109         .parent         = &pll1_clk,
110         .flags          = CLK_PLL,
111         .div_reg        = PLLDIV2,
112 };
113 
114 static struct clk pll1_sysclk3 = {
115         .name           = "pll1_sysclk3",
116         .parent         = &pll1_clk,
117         .flags          = CLK_PLL,
118         .div_reg        = PLLDIV3,
119 };
120 
121 static struct clk pll1_sysclk4 = {
122         .name           = "pll1_sysclk4",
123         .parent         = &pll1_clk,
124         .flags          = CLK_PLL,
125         .div_reg        = PLLDIV4,
126 };
127 
128 static struct clk pll1_sysclk5 = {
129         .name           = "pll1_sysclk5",
130         .parent         = &pll1_clk,
131         .flags          = CLK_PLL,
132         .div_reg        = PLLDIV5,
133 };
134 
135 static struct clk pll1_sysclk6 = {
136         .name           = "pll1_sysclk6",
137         .parent         = &pll1_clk,
138         .flags          = CLK_PLL,
139         .div_reg        = PLLDIV6,
140 };
141 
142 static struct clk pll1_sysclk7 = {
143         .name           = "pll1_sysclk7",
144         .parent         = &pll1_clk,
145         .flags          = CLK_PLL,
146         .div_reg        = PLLDIV7,
147 };
148 
149 static struct clk pll1_sysclk8 = {
150         .name           = "pll1_sysclk8",
151         .parent         = &pll1_clk,
152         .flags          = CLK_PLL,
153         .div_reg        = PLLDIV8,
154 };
155 
156 static struct clk pll1_sysclk9 = {
157         .name           = "pll1_sysclk9",
158         .parent         = &pll1_clk,
159         .flags          = CLK_PLL,
160         .div_reg        = PLLDIV9,
161 };
162 
163 static struct clk pll2_clk = {
164         .name           = "pll2",
165         .parent         = &ref_clk,
166         .flags          = CLK_PLL,
167         .pll_data       = &pll2_data,
168 };
169 
170 static struct clk pll2_aux_clk = {
171         .name           = "pll2_aux_clk",
172         .parent         = &pll2_clk,
173         .flags          = CLK_PLL | PRE_PLL,
174 };
175 
176 static struct clk clkout1_clk = {
177         .name           = "clkout1",
178         .parent         = &pll2_clk,
179         .flags          = CLK_PLL | PRE_PLL,
180 };
181 
182 static struct clk pll2_sysclk1 = {
183         .name           = "pll2_sysclk1",
184         .parent         = &pll2_clk,
185         .flags          = CLK_PLL,
186         .div_reg        = PLLDIV1,
187 };
188 
189 static struct clk pll2_sysclk2 = {
190         .name           = "pll2_sysclk2",
191         .parent         = &pll2_clk,
192         .flags          = CLK_PLL,
193         .div_reg        = PLLDIV2,
194 };
195 
196 static struct clk pll2_sysclk3 = {
197         .name           = "pll2_sysclk3",
198         .parent         = &pll2_clk,
199         .flags          = CLK_PLL,
200         .div_reg        = PLLDIV3,
201 };
202 
203 static struct clk pll2_sysclk4 = {
204         .name           = "pll2_sysclk4",
205         .parent         = &pll2_clk,
206         .flags          = CLK_PLL,
207         .div_reg        = PLLDIV4,
208 };
209 
210 static struct clk pll2_sysclk5 = {
211         .name           = "pll2_sysclk5",
212         .parent         = &pll2_clk,
213         .flags          = CLK_PLL,
214         .div_reg        = PLLDIV5,
215 };
216 
217 static struct clk pll2_sysclk6 = {
218         .name           = "pll2_sysclk6",
219         .parent         = &pll2_clk,
220         .flags          = CLK_PLL,
221         .div_reg        = PLLDIV6,
222 };
223 
224 static struct clk pll2_sysclk7 = {
225         .name           = "pll2_sysclk7",
226         .parent         = &pll2_clk,
227         .flags          = CLK_PLL,
228         .div_reg        = PLLDIV7,
229 };
230 
231 static struct clk pll2_sysclk8 = {
232         .name           = "pll2_sysclk8",
233         .parent         = &pll2_clk,
234         .flags          = CLK_PLL,
235         .div_reg        = PLLDIV8,
236 };
237 
238 static struct clk pll2_sysclk9 = {
239         .name           = "pll2_sysclk9",
240         .parent         = &pll2_clk,
241         .flags          = CLK_PLL,
242         .div_reg        = PLLDIV9,
243 };
244 
245 static struct clk vpss_dac_clk = {
246         .name           = "vpss_dac",
247         .parent         = &pll1_sysclk3,
248         .lpsc           = DM365_LPSC_DAC_CLK,
249 };
250 
251 static struct clk vpss_master_clk = {
252         .name           = "vpss_master",
253         .parent         = &pll1_sysclk5,
254         .lpsc           = DM365_LPSC_VPSSMSTR,
255         .flags          = CLK_PSC,
256 };
257 
258 static struct clk vpss_slave_clk = {
259         .name           = "vpss_slave",
260         .parent         = &pll1_sysclk5,
261         .lpsc           = DAVINCI_LPSC_VPSSSLV,
262 };
263 
264 static struct clk arm_clk = {
265         .name           = "arm_clk",
266         .parent         = &pll2_sysclk2,
267         .lpsc           = DAVINCI_LPSC_ARM,
268         .flags          = ALWAYS_ENABLED,
269 };
270 
271 static struct clk uart0_clk = {
272         .name           = "uart0",
273         .parent         = &pll1_aux_clk,
274         .lpsc           = DAVINCI_LPSC_UART0,
275 };
276 
277 static struct clk uart1_clk = {
278         .name           = "uart1",
279         .parent         = &pll1_sysclk4,
280         .lpsc           = DAVINCI_LPSC_UART1,
281 };
282 
283 static struct clk i2c_clk = {
284         .name           = "i2c",
285         .parent         = &pll1_aux_clk,
286         .lpsc           = DAVINCI_LPSC_I2C,
287 };
288 
289 static struct clk mmcsd0_clk = {
290         .name           = "mmcsd0",
291         .parent         = &pll1_sysclk8,
292         .lpsc           = DAVINCI_LPSC_MMC_SD,
293 };
294 
295 static struct clk mmcsd1_clk = {
296         .name           = "mmcsd1",
297         .parent         = &pll1_sysclk4,
298         .lpsc           = DM365_LPSC_MMC_SD1,
299 };
300 
301 static struct clk spi0_clk = {
302         .name           = "spi0",
303         .parent         = &pll1_sysclk4,
304         .lpsc           = DAVINCI_LPSC_SPI,
305 };
306 
307 static struct clk spi1_clk = {
308         .name           = "spi1",
309         .parent         = &pll1_sysclk4,
310         .lpsc           = DM365_LPSC_SPI1,
311 };
312 
313 static struct clk spi2_clk = {
314         .name           = "spi2",
315         .parent         = &pll1_sysclk4,
316         .lpsc           = DM365_LPSC_SPI2,
317 };
318 
319 static struct clk spi3_clk = {
320         .name           = "spi3",
321         .parent         = &pll1_sysclk4,
322         .lpsc           = DM365_LPSC_SPI3,
323 };
324 
325 static struct clk spi4_clk = {
326         .name           = "spi4",
327         .parent         = &pll1_aux_clk,
328         .lpsc           = DM365_LPSC_SPI4,
329 };
330 
331 static struct clk gpio_clk = {
332         .name           = "gpio",
333         .parent         = &pll1_sysclk4,
334         .lpsc           = DAVINCI_LPSC_GPIO,
335 };
336 
337 static struct clk aemif_clk = {
338         .name           = "aemif",
339         .parent         = &pll1_sysclk4,
340         .lpsc           = DAVINCI_LPSC_AEMIF,
341 };
342 
343 static struct clk pwm0_clk = {
344         .name           = "pwm0",
345         .parent         = &pll1_aux_clk,
346         .lpsc           = DAVINCI_LPSC_PWM0,
347 };
348 
349 static struct clk pwm1_clk = {
350         .name           = "pwm1",
351         .parent         = &pll1_aux_clk,
352         .lpsc           = DAVINCI_LPSC_PWM1,
353 };
354 
355 static struct clk pwm2_clk = {
356         .name           = "pwm2",
357         .parent         = &pll1_aux_clk,
358         .lpsc           = DAVINCI_LPSC_PWM2,
359 };
360 
361 static struct clk pwm3_clk = {
362         .name           = "pwm3",
363         .parent         = &ref_clk,
364         .lpsc           = DM365_LPSC_PWM3,
365 };
366 
367 static struct clk timer0_clk = {
368         .name           = "timer0",
369         .parent         = &pll1_aux_clk,
370         .lpsc           = DAVINCI_LPSC_TIMER0,
371 };
372 
373 static struct clk timer1_clk = {
374         .name           = "timer1",
375         .parent         = &pll1_aux_clk,
376         .lpsc           = DAVINCI_LPSC_TIMER1,
377 };
378 
379 static struct clk timer2_clk = {
380         .name           = "timer2",
381         .parent         = &pll1_aux_clk,
382         .lpsc           = DAVINCI_LPSC_TIMER2,
383         .usecount       = 1,
384 };
385 
386 static struct clk timer3_clk = {
387         .name           = "timer3",
388         .parent         = &pll1_aux_clk,
389         .lpsc           = DM365_LPSC_TIMER3,
390 };
391 
392 static struct clk usb_clk = {
393         .name           = "usb",
394         .parent         = &pll1_aux_clk,
395         .lpsc           = DAVINCI_LPSC_USB,
396 };
397 
398 static struct clk emac_clk = {
399         .name           = "emac",
400         .parent         = &pll1_sysclk4,
401         .lpsc           = DM365_LPSC_EMAC,
402 };
403 
404 static struct clk voicecodec_clk = {
405         .name           = "voice_codec",
406         .parent         = &pll2_sysclk4,
407         .lpsc           = DM365_LPSC_VOICE_CODEC,
408 };
409 
410 static struct clk asp0_clk = {
411         .name           = "asp0",
412         .parent         = &pll1_sysclk4,
413         .lpsc           = DM365_LPSC_McBSP1,
414 };
415 
416 static struct clk rto_clk = {
417         .name           = "rto",
418         .parent         = &pll1_sysclk4,
419         .lpsc           = DM365_LPSC_RTO,
420 };
421 
422 static struct clk mjcp_clk = {
423         .name           = "mjcp",
424         .parent         = &pll1_sysclk3,
425         .lpsc           = DM365_LPSC_MJCP,
426 };
427 
428 static struct clk_lookup dm365_clks[] = {
429         CLK(NULL, "ref", &ref_clk),
430         CLK(NULL, "pll1", &pll1_clk),
431         CLK(NULL, "pll1_aux", &pll1_aux_clk),
432         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
433         CLK(NULL, "clkout0", &clkout0_clk),
434         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
435         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
436         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
437         CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
438         CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
439         CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
440         CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
441         CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
442         CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
443         CLK(NULL, "pll2", &pll2_clk),
444         CLK(NULL, "pll2_aux", &pll2_aux_clk),
445         CLK(NULL, "clkout1", &clkout1_clk),
446         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
447         CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
448         CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
449         CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
450         CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
451         CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
452         CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
453         CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
454         CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
455         CLK(NULL, "vpss_dac", &vpss_dac_clk),
456         CLK("vpss", "master", &vpss_master_clk),
457         CLK("vpss", "slave", &vpss_slave_clk),
458         CLK(NULL, "arm", &arm_clk),
459         CLK("serial8250.0", NULL, &uart0_clk),
460         CLK("serial8250.1", NULL, &uart1_clk),
461         CLK("i2c_davinci.1", NULL, &i2c_clk),
462         CLK("da830-mmc.0", NULL, &mmcsd0_clk),
463         CLK("da830-mmc.1", NULL, &mmcsd1_clk),
464         CLK("spi_davinci.0", NULL, &spi0_clk),
465         CLK("spi_davinci.1", NULL, &spi1_clk),
466         CLK("spi_davinci.2", NULL, &spi2_clk),
467         CLK("spi_davinci.3", NULL, &spi3_clk),
468         CLK("spi_davinci.4", NULL, &spi4_clk),
469         CLK(NULL, "gpio", &gpio_clk),
470         CLK(NULL, "aemif", &aemif_clk),
471         CLK(NULL, "pwm0", &pwm0_clk),
472         CLK(NULL, "pwm1", &pwm1_clk),
473         CLK(NULL, "pwm2", &pwm2_clk),
474         CLK(NULL, "pwm3", &pwm3_clk),
475         CLK(NULL, "timer0", &timer0_clk),
476         CLK(NULL, "timer1", &timer1_clk),
477         CLK("davinci-wdt", NULL, &timer2_clk),
478         CLK(NULL, "timer3", &timer3_clk),
479         CLK(NULL, "usb", &usb_clk),
480         CLK("davinci_emac.1", NULL, &emac_clk),
481         CLK("davinci_mdio.0", "fck", &emac_clk),
482         CLK("davinci_voicecodec", NULL, &voicecodec_clk),
483         CLK("davinci-mcbsp", NULL, &asp0_clk),
484         CLK(NULL, "rto", &rto_clk),
485         CLK(NULL, "mjcp", &mjcp_clk),
486         CLK(NULL, NULL, NULL),
487 };
488 
489 /*----------------------------------------------------------------------*/
490 
491 #define INTMUX          0x18
492 #define EVTMUX          0x1c
493 
494 
495 static const struct mux_config dm365_pins[] = {
496 #ifdef CONFIG_DAVINCI_MUX
497 MUX_CFG(DM365,  MMCSD0,         0,   24,     1,   0,     false)
498 
499 MUX_CFG(DM365,  SD1_CLK,        0,   16,    3,    1,     false)
500 MUX_CFG(DM365,  SD1_CMD,        4,   30,    3,    1,     false)
501 MUX_CFG(DM365,  SD1_DATA3,      4,   28,    3,    1,     false)
502 MUX_CFG(DM365,  SD1_DATA2,      4,   26,    3,    1,     false)
503 MUX_CFG(DM365,  SD1_DATA1,      4,   24,    3,    1,     false)
504 MUX_CFG(DM365,  SD1_DATA0,      4,   22,    3,    1,     false)
505 
506 MUX_CFG(DM365,  I2C_SDA,        3,   23,    3,    2,     false)
507 MUX_CFG(DM365,  I2C_SCL,        3,   21,    3,    2,     false)
508 
509 MUX_CFG(DM365,  AEMIF_AR_A14,   2,   0,     3,    1,     false)
510 MUX_CFG(DM365,  AEMIF_AR_BA0,   2,   0,     3,    2,     false)
511 MUX_CFG(DM365,  AEMIF_A3,       2,   2,     3,    1,     false)
512 MUX_CFG(DM365,  AEMIF_A7,       2,   4,     3,    1,     false)
513 MUX_CFG(DM365,  AEMIF_D15_8,    2,   6,     1,    1,     false)
514 MUX_CFG(DM365,  AEMIF_CE0,      2,   7,     1,    0,     false)
515 MUX_CFG(DM365,  AEMIF_CE1,      2,   8,     1,    0,     false)
516 MUX_CFG(DM365,  AEMIF_WE_OE,    2,   9,     1,    0,     false)
517 
518 MUX_CFG(DM365,  MCBSP0_BDX,     0,   23,    1,    1,     false)
519 MUX_CFG(DM365,  MCBSP0_X,       0,   22,    1,    1,     false)
520 MUX_CFG(DM365,  MCBSP0_BFSX,    0,   21,    1,    1,     false)
521 MUX_CFG(DM365,  MCBSP0_BDR,     0,   20,    1,    1,     false)
522 MUX_CFG(DM365,  MCBSP0_R,       0,   19,    1,    1,     false)
523 MUX_CFG(DM365,  MCBSP0_BFSR,    0,   18,    1,    1,     false)
524 
525 MUX_CFG(DM365,  SPI0_SCLK,      3,   28,    1,    1,     false)
526 MUX_CFG(DM365,  SPI0_SDI,       3,   26,    3,    1,     false)
527 MUX_CFG(DM365,  SPI0_SDO,       3,   25,    1,    1,     false)
528 MUX_CFG(DM365,  SPI0_SDENA0,    3,   29,    3,    1,     false)
529 MUX_CFG(DM365,  SPI0_SDENA1,    3,   26,    3,    2,     false)
530 
531 MUX_CFG(DM365,  UART0_RXD,      3,   20,    1,    1,     false)
532 MUX_CFG(DM365,  UART0_TXD,      3,   19,    1,    1,     false)
533 MUX_CFG(DM365,  UART1_RXD,      3,   17,    3,    2,     false)
534 MUX_CFG(DM365,  UART1_TXD,      3,   15,    3,    2,     false)
535 MUX_CFG(DM365,  UART1_RTS,      3,   23,    3,    1,     false)
536 MUX_CFG(DM365,  UART1_CTS,      3,   21,    3,    1,     false)
537 
538 MUX_CFG(DM365,  EMAC_TX_EN,     3,   17,    3,    1,     false)
539 MUX_CFG(DM365,  EMAC_TX_CLK,    3,   15,    3,    1,     false)
540 MUX_CFG(DM365,  EMAC_COL,       3,   14,    1,    1,     false)
541 MUX_CFG(DM365,  EMAC_TXD3,      3,   13,    1,    1,     false)
542 MUX_CFG(DM365,  EMAC_TXD2,      3,   12,    1,    1,     false)
543 MUX_CFG(DM365,  EMAC_TXD1,      3,   11,    1,    1,     false)
544 MUX_CFG(DM365,  EMAC_TXD0,      3,   10,    1,    1,     false)
545 MUX_CFG(DM365,  EMAC_RXD3,      3,   9,     1,    1,     false)
546 MUX_CFG(DM365,  EMAC_RXD2,      3,   8,     1,    1,     false)
547 MUX_CFG(DM365,  EMAC_RXD1,      3,   7,     1,    1,     false)
548 MUX_CFG(DM365,  EMAC_RXD0,      3,   6,     1,    1,     false)
549 MUX_CFG(DM365,  EMAC_RX_CLK,    3,   5,     1,    1,     false)
550 MUX_CFG(DM365,  EMAC_RX_DV,     3,   4,     1,    1,     false)
551 MUX_CFG(DM365,  EMAC_RX_ER,     3,   3,     1,    1,     false)
552 MUX_CFG(DM365,  EMAC_CRS,       3,   2,     1,    1,     false)
553 MUX_CFG(DM365,  EMAC_MDIO,      3,   1,     1,    1,     false)
554 MUX_CFG(DM365,  EMAC_MDCLK,     3,   0,     1,    1,     false)
555 
556 MUX_CFG(DM365,  KEYSCAN,        2,   0,     0x3f, 0x3f,  false)
557 
558 MUX_CFG(DM365,  PWM0,           1,   0,     3,    2,     false)
559 MUX_CFG(DM365,  PWM0_G23,       3,   26,    3,    3,     false)
560 MUX_CFG(DM365,  PWM1,           1,   2,     3,    2,     false)
561 MUX_CFG(DM365,  PWM1_G25,       3,   29,    3,    2,     false)
562 MUX_CFG(DM365,  PWM2_G87,       1,   10,    3,    2,     false)
563 MUX_CFG(DM365,  PWM2_G88,       1,   8,     3,    2,     false)
564 MUX_CFG(DM365,  PWM2_G89,       1,   6,     3,    2,     false)
565 MUX_CFG(DM365,  PWM2_G90,       1,   4,     3,    2,     false)
566 MUX_CFG(DM365,  PWM3_G80,       1,   20,    3,    3,     false)
567 MUX_CFG(DM365,  PWM3_G81,       1,   18,    3,    3,     false)
568 MUX_CFG(DM365,  PWM3_G85,       1,   14,    3,    2,     false)
569 MUX_CFG(DM365,  PWM3_G86,       1,   12,    3,    2,     false)
570 
571 MUX_CFG(DM365,  SPI1_SCLK,      4,   2,     3,    1,     false)
572 MUX_CFG(DM365,  SPI1_SDI,       3,   31,    1,    1,     false)
573 MUX_CFG(DM365,  SPI1_SDO,       4,   0,     3,    1,     false)
574 MUX_CFG(DM365,  SPI1_SDENA0,    4,   4,     3,    1,     false)
575 MUX_CFG(DM365,  SPI1_SDENA1,    4,   0,     3,    2,     false)
576 
577 MUX_CFG(DM365,  SPI2_SCLK,      4,   10,    3,    1,     false)
578 MUX_CFG(DM365,  SPI2_SDI,       4,   6,     3,    1,     false)
579 MUX_CFG(DM365,  SPI2_SDO,       4,   8,     3,    1,     false)
580 MUX_CFG(DM365,  SPI2_SDENA0,    4,   12,    3,    1,     false)
581 MUX_CFG(DM365,  SPI2_SDENA1,    4,   8,     3,    2,     false)
582 
583 MUX_CFG(DM365,  SPI3_SCLK,      0,   0,     3,    2,     false)
584 MUX_CFG(DM365,  SPI3_SDI,       0,   2,     3,    2,     false)
585 MUX_CFG(DM365,  SPI3_SDO,       0,   6,     3,    2,     false)
586 MUX_CFG(DM365,  SPI3_SDENA0,    0,   4,     3,    2,     false)
587 MUX_CFG(DM365,  SPI3_SDENA1,    0,   6,     3,    3,     false)
588 
589 MUX_CFG(DM365,  SPI4_SCLK,      4,   18,    3,    1,     false)
590 MUX_CFG(DM365,  SPI4_SDI,       4,   14,    3,    1,     false)
591 MUX_CFG(DM365,  SPI4_SDO,       4,   16,    3,    1,     false)
592 MUX_CFG(DM365,  SPI4_SDENA0,    4,   20,    3,    1,     false)
593 MUX_CFG(DM365,  SPI4_SDENA1,    4,   16,    3,    2,     false)
594 
595 MUX_CFG(DM365,  CLKOUT0,        4,   20,    3,    3,     false)
596 MUX_CFG(DM365,  CLKOUT1,        4,   16,    3,    3,     false)
597 MUX_CFG(DM365,  CLKOUT2,        4,   8,     3,    3,     false)
598 
599 MUX_CFG(DM365,  GPIO20,         3,   21,    3,    0,     false)
600 MUX_CFG(DM365,  GPIO30,         4,   6,     3,    0,     false)
601 MUX_CFG(DM365,  GPIO31,         4,   8,     3,    0,     false)
602 MUX_CFG(DM365,  GPIO32,         4,   10,    3,    0,     false)
603 MUX_CFG(DM365,  GPIO33,         4,   12,    3,    0,     false)
604 MUX_CFG(DM365,  GPIO40,         4,   26,    3,    0,     false)
605 MUX_CFG(DM365,  GPIO64_57,      2,   6,     1,    0,     false)
606 
607 MUX_CFG(DM365,  VOUT_FIELD,     1,   18,    3,    1,     false)
608 MUX_CFG(DM365,  VOUT_FIELD_G81, 1,   18,    3,    0,     false)
609 MUX_CFG(DM365,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
610 MUX_CFG(DM365,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
611 MUX_CFG(DM365,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
612 MUX_CFG(DM365,  VIN_CAM_WEN,    0,   14,    3,    0,     false)
613 MUX_CFG(DM365,  VIN_CAM_VD,     0,   13,    1,    0,     false)
614 MUX_CFG(DM365,  VIN_CAM_HD,     0,   12,    1,    0,     false)
615 MUX_CFG(DM365,  VIN_YIN4_7_EN,  0,   0,     0xff, 0,     false)
616 MUX_CFG(DM365,  VIN_YIN0_3_EN,  0,   8,     0xf,  0,     false)
617 
618 INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
619 INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
620 INT_CFG(DM365,  INT_EDMA_TC1_ERR,    4,     1,    1,     false)
621 INT_CFG(DM365,  INT_EDMA_TC2_ERR,    22,    1,    1,     false)
622 INT_CFG(DM365,  INT_EDMA_TC3_ERR,    23,    1,    1,     false)
623 INT_CFG(DM365,  INT_PRTCSS,          10,    1,    1,     false)
624 INT_CFG(DM365,  INT_EMAC_RXTHRESH,   14,    1,    1,     false)
625 INT_CFG(DM365,  INT_EMAC_RXPULSE,    15,    1,    1,     false)
626 INT_CFG(DM365,  INT_EMAC_TXPULSE,    16,    1,    1,     false)
627 INT_CFG(DM365,  INT_EMAC_MISCPULSE,  17,    1,    1,     false)
628 INT_CFG(DM365,  INT_IMX0_ENABLE,     0,     1,    0,     false)
629 INT_CFG(DM365,  INT_IMX0_DISABLE,    0,     1,    1,     false)
630 INT_CFG(DM365,  INT_HDVICP_ENABLE,   0,     1,    1,     false)
631 INT_CFG(DM365,  INT_HDVICP_DISABLE,  0,     1,    0,     false)
632 INT_CFG(DM365,  INT_IMX1_ENABLE,     24,    1,    1,     false)
633 INT_CFG(DM365,  INT_IMX1_DISABLE,    24,    1,    0,     false)
634 INT_CFG(DM365,  INT_NSF_ENABLE,      25,    1,    1,     false)
635 INT_CFG(DM365,  INT_NSF_DISABLE,     25,    1,    0,     false)
636 
637 EVT_CFG(DM365,  EVT2_ASP_TX,         0,     1,    0,     false)
638 EVT_CFG(DM365,  EVT3_ASP_RX,         1,     1,    0,     false)
639 EVT_CFG(DM365,  EVT2_VC_TX,          0,     1,    1,     false)
640 EVT_CFG(DM365,  EVT3_VC_RX,          1,     1,    1,     false)
641 #endif
642 };
643 
644 static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
645 
646 static struct davinci_spi_platform_data dm365_spi0_pdata = {
647         .version        = SPI_VERSION_1,
648         .num_chipselect = 2,
649         .dma_event_q    = EVENTQ_3,
650         .prescaler_limit = 1,
651 };
652 
653 static struct resource dm365_spi0_resources[] = {
654         {
655                 .start = 0x01c66000,
656                 .end   = 0x01c667ff,
657                 .flags = IORESOURCE_MEM,
658         },
659         {
660                 .start = IRQ_DM365_SPIINT0_0,
661                 .flags = IORESOURCE_IRQ,
662         },
663 };
664 
665 static struct platform_device dm365_spi0_device = {
666         .name = "spi_davinci",
667         .id = 0,
668         .dev = {
669                 .dma_mask = &dm365_spi0_dma_mask,
670                 .coherent_dma_mask = DMA_BIT_MASK(32),
671                 .platform_data = &dm365_spi0_pdata,
672         },
673         .num_resources = ARRAY_SIZE(dm365_spi0_resources),
674         .resource = dm365_spi0_resources,
675 };
676 
677 void __init dm365_init_spi0(unsigned chipselect_mask,
678                 const struct spi_board_info *info, unsigned len)
679 {
680         davinci_cfg_reg(DM365_SPI0_SCLK);
681         davinci_cfg_reg(DM365_SPI0_SDI);
682         davinci_cfg_reg(DM365_SPI0_SDO);
683 
684         /* not all slaves will be wired up */
685         if (chipselect_mask & BIT(0))
686                 davinci_cfg_reg(DM365_SPI0_SDENA0);
687         if (chipselect_mask & BIT(1))
688                 davinci_cfg_reg(DM365_SPI0_SDENA1);
689 
690         spi_register_board_info(info, len);
691 
692         platform_device_register(&dm365_spi0_device);
693 }
694 
695 static struct resource dm365_gpio_resources[] = {
696         {       /* registers */
697                 .start  = DAVINCI_GPIO_BASE,
698                 .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
699                 .flags  = IORESOURCE_MEM,
700         },
701         {       /* interrupt */
702                 .start  = IRQ_DM365_GPIO0,
703                 .end    = IRQ_DM365_GPIO7,
704                 .flags  = IORESOURCE_IRQ,
705         },
706 };
707 
708 static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
709         .ngpio          = 104,
710         .gpio_unbanked  = 8,
711 };
712 
713 int __init dm365_gpio_register(void)
714 {
715         return davinci_gpio_register(dm365_gpio_resources,
716                                      ARRAY_SIZE(dm365_gpio_resources),
717                                      &dm365_gpio_platform_data);
718 }
719 
720 static struct emac_platform_data dm365_emac_pdata = {
721         .ctrl_reg_offset        = DM365_EMAC_CNTRL_OFFSET,
722         .ctrl_mod_reg_offset    = DM365_EMAC_CNTRL_MOD_OFFSET,
723         .ctrl_ram_offset        = DM365_EMAC_CNTRL_RAM_OFFSET,
724         .ctrl_ram_size          = DM365_EMAC_CNTRL_RAM_SIZE,
725         .version                = EMAC_VERSION_2,
726 };
727 
728 static struct resource dm365_emac_resources[] = {
729         {
730                 .start  = DM365_EMAC_BASE,
731                 .end    = DM365_EMAC_BASE + SZ_16K - 1,
732                 .flags  = IORESOURCE_MEM,
733         },
734         {
735                 .start  = IRQ_DM365_EMAC_RXTHRESH,
736                 .end    = IRQ_DM365_EMAC_RXTHRESH,
737                 .flags  = IORESOURCE_IRQ,
738         },
739         {
740                 .start  = IRQ_DM365_EMAC_RXPULSE,
741                 .end    = IRQ_DM365_EMAC_RXPULSE,
742                 .flags  = IORESOURCE_IRQ,
743         },
744         {
745                 .start  = IRQ_DM365_EMAC_TXPULSE,
746                 .end    = IRQ_DM365_EMAC_TXPULSE,
747                 .flags  = IORESOURCE_IRQ,
748         },
749         {
750                 .start  = IRQ_DM365_EMAC_MISCPULSE,
751                 .end    = IRQ_DM365_EMAC_MISCPULSE,
752                 .flags  = IORESOURCE_IRQ,
753         },
754 };
755 
756 static struct platform_device dm365_emac_device = {
757         .name           = "davinci_emac",
758         .id             = 1,
759         .dev = {
760                 .platform_data  = &dm365_emac_pdata,
761         },
762         .num_resources  = ARRAY_SIZE(dm365_emac_resources),
763         .resource       = dm365_emac_resources,
764 };
765 
766 static struct resource dm365_mdio_resources[] = {
767         {
768                 .start  = DM365_EMAC_MDIO_BASE,
769                 .end    = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
770                 .flags  = IORESOURCE_MEM,
771         },
772 };
773 
774 static struct platform_device dm365_mdio_device = {
775         .name           = "davinci_mdio",
776         .id             = 0,
777         .num_resources  = ARRAY_SIZE(dm365_mdio_resources),
778         .resource       = dm365_mdio_resources,
779 };
780 
781 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
782         [IRQ_VDINT0]                    = 2,
783         [IRQ_VDINT1]                    = 6,
784         [IRQ_VDINT2]                    = 6,
785         [IRQ_HISTINT]                   = 6,
786         [IRQ_H3AINT]                    = 6,
787         [IRQ_PRVUINT]                   = 6,
788         [IRQ_RSZINT]                    = 6,
789         [IRQ_DM365_INSFINT]             = 7,
790         [IRQ_VENCINT]                   = 6,
791         [IRQ_ASQINT]                    = 6,
792         [IRQ_IMXINT]                    = 6,
793         [IRQ_DM365_IMCOPINT]            = 4,
794         [IRQ_USBINT]                    = 4,
795         [IRQ_DM365_RTOINT]              = 7,
796         [IRQ_DM365_TINT5]               = 7,
797         [IRQ_DM365_TINT6]               = 5,
798         [IRQ_CCINT0]                    = 5,
799         [IRQ_CCERRINT]                  = 5,
800         [IRQ_TCERRINT0]                 = 5,
801         [IRQ_TCERRINT]                  = 7,
802         [IRQ_PSCIN]                     = 4,
803         [IRQ_DM365_SPINT2_1]            = 7,
804         [IRQ_DM365_TINT7]               = 7,
805         [IRQ_DM365_SDIOINT0]            = 7,
806         [IRQ_MBXINT]                    = 7,
807         [IRQ_MBRINT]                    = 7,
808         [IRQ_MMCINT]                    = 7,
809         [IRQ_DM365_MMCINT1]             = 7,
810         [IRQ_DM365_PWMINT3]             = 7,
811         [IRQ_AEMIFINT]                  = 2,
812         [IRQ_DM365_SDIOINT1]            = 2,
813         [IRQ_TINT0_TINT12]              = 7,
814         [IRQ_TINT0_TINT34]              = 7,
815         [IRQ_TINT1_TINT12]              = 7,
816         [IRQ_TINT1_TINT34]              = 7,
817         [IRQ_PWMINT0]                   = 7,
818         [IRQ_PWMINT1]                   = 3,
819         [IRQ_PWMINT2]                   = 3,
820         [IRQ_I2C]                       = 3,
821         [IRQ_UARTINT0]                  = 3,
822         [IRQ_UARTINT1]                  = 3,
823         [IRQ_DM365_RTCINT]              = 3,
824         [IRQ_DM365_SPIINT0_0]           = 3,
825         [IRQ_DM365_SPIINT3_0]           = 3,
826         [IRQ_DM365_GPIO0]               = 3,
827         [IRQ_DM365_GPIO1]               = 7,
828         [IRQ_DM365_GPIO2]               = 4,
829         [IRQ_DM365_GPIO3]               = 4,
830         [IRQ_DM365_GPIO4]               = 7,
831         [IRQ_DM365_GPIO5]               = 7,
832         [IRQ_DM365_GPIO6]               = 7,
833         [IRQ_DM365_GPIO7]               = 7,
834         [IRQ_DM365_EMAC_RXTHRESH]       = 7,
835         [IRQ_DM365_EMAC_RXPULSE]        = 7,
836         [IRQ_DM365_EMAC_TXPULSE]        = 7,
837         [IRQ_DM365_EMAC_MISCPULSE]      = 7,
838         [IRQ_DM365_GPIO12]              = 7,
839         [IRQ_DM365_GPIO13]              = 7,
840         [IRQ_DM365_GPIO14]              = 7,
841         [IRQ_DM365_GPIO15]              = 7,
842         [IRQ_DM365_KEYINT]              = 7,
843         [IRQ_DM365_TCERRINT2]           = 7,
844         [IRQ_DM365_TCERRINT3]           = 7,
845         [IRQ_DM365_EMUINT]              = 7,
846 };
847 
848 /* Four Transfer Controllers on DM365 */
849 static s8 dm365_queue_priority_mapping[][2] = {
850         /* {event queue no, Priority} */
851         {0, 7},
852         {1, 7},
853         {2, 7},
854         {3, 0},
855         {-1, -1},
856 };
857 
858 static const struct dma_slave_map dm365_edma_map[] = {
859         { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
860         { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
861         { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
862         { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
863         { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
864         { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
865         { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
866         { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
867         { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
868         { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
869         { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
870         { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
871         { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
872         { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
873         { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
874         { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
875 };
876 
877 static struct edma_soc_info dm365_edma_pdata = {
878         .queue_priority_mapping = dm365_queue_priority_mapping,
879         .default_queue          = EVENTQ_3,
880         .slave_map              = dm365_edma_map,
881         .slavecnt               = ARRAY_SIZE(dm365_edma_map),
882 };
883 
884 static struct resource edma_resources[] = {
885         {
886                 .name   = "edma3_cc",
887                 .start  = 0x01c00000,
888                 .end    = 0x01c00000 + SZ_64K - 1,
889                 .flags  = IORESOURCE_MEM,
890         },
891         {
892                 .name   = "edma3_tc0",
893                 .start  = 0x01c10000,
894                 .end    = 0x01c10000 + SZ_1K - 1,
895                 .flags  = IORESOURCE_MEM,
896         },
897         {
898                 .name   = "edma3_tc1",
899                 .start  = 0x01c10400,
900                 .end    = 0x01c10400 + SZ_1K - 1,
901                 .flags  = IORESOURCE_MEM,
902         },
903         {
904                 .name   = "edma3_tc2",
905                 .start  = 0x01c10800,
906                 .end    = 0x01c10800 + SZ_1K - 1,
907                 .flags  = IORESOURCE_MEM,
908         },
909         {
910                 .name   = "edma3_tc3",
911                 .start  = 0x01c10c00,
912                 .end    = 0x01c10c00 + SZ_1K - 1,
913                 .flags  = IORESOURCE_MEM,
914         },
915         {
916                 .name   = "edma3_ccint",
917                 .start  = IRQ_CCINT0,
918                 .flags  = IORESOURCE_IRQ,
919         },
920         {
921                 .name   = "edma3_ccerrint",
922                 .start  = IRQ_CCERRINT,
923                 .flags  = IORESOURCE_IRQ,
924         },
925         /* not using TC*_ERR */
926 };
927 
928 static const struct platform_device_info dm365_edma_device __initconst = {
929         .name           = "edma",
930         .id             = 0,
931         .dma_mask       = DMA_BIT_MASK(32),
932         .res            = edma_resources,
933         .num_res        = ARRAY_SIZE(edma_resources),
934         .data           = &dm365_edma_pdata,
935         .size_data      = sizeof(dm365_edma_pdata),
936 };
937 
938 static struct resource dm365_asp_resources[] = {
939         {
940                 .name   = "mpu",
941                 .start  = DAVINCI_DM365_ASP0_BASE,
942                 .end    = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
943                 .flags  = IORESOURCE_MEM,
944         },
945         {
946                 .start  = DAVINCI_DMA_ASP0_TX,
947                 .end    = DAVINCI_DMA_ASP0_TX,
948                 .flags  = IORESOURCE_DMA,
949         },
950         {
951                 .start  = DAVINCI_DMA_ASP0_RX,
952                 .end    = DAVINCI_DMA_ASP0_RX,
953                 .flags  = IORESOURCE_DMA,
954         },
955 };
956 
957 static struct platform_device dm365_asp_device = {
958         .name           = "davinci-mcbsp",
959         .id             = -1,
960         .num_resources  = ARRAY_SIZE(dm365_asp_resources),
961         .resource       = dm365_asp_resources,
962 };
963 
964 static struct resource dm365_vc_resources[] = {
965         {
966                 .start  = DAVINCI_DM365_VC_BASE,
967                 .end    = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
968                 .flags  = IORESOURCE_MEM,
969         },
970         {
971                 .start  = DAVINCI_DMA_VC_TX,
972                 .end    = DAVINCI_DMA_VC_TX,
973                 .flags  = IORESOURCE_DMA,
974         },
975         {
976                 .start  = DAVINCI_DMA_VC_RX,
977                 .end    = DAVINCI_DMA_VC_RX,
978                 .flags  = IORESOURCE_DMA,
979         },
980 };
981 
982 static struct platform_device dm365_vc_device = {
983         .name           = "davinci_voicecodec",
984         .id             = -1,
985         .num_resources  = ARRAY_SIZE(dm365_vc_resources),
986         .resource       = dm365_vc_resources,
987 };
988 
989 static struct resource dm365_rtc_resources[] = {
990         {
991                 .start = DM365_RTC_BASE,
992                 .end = DM365_RTC_BASE + SZ_1K - 1,
993                 .flags = IORESOURCE_MEM,
994         },
995         {
996                 .start = IRQ_DM365_RTCINT,
997                 .flags = IORESOURCE_IRQ,
998         },
999 };
1000 
1001 static struct platform_device dm365_rtc_device = {
1002         .name = "rtc_davinci",
1003         .id = 0,
1004         .num_resources = ARRAY_SIZE(dm365_rtc_resources),
1005         .resource = dm365_rtc_resources,
1006 };
1007 
1008 static struct map_desc dm365_io_desc[] = {
1009         {
1010                 .virtual        = IO_VIRT,
1011                 .pfn            = __phys_to_pfn(IO_PHYS),
1012                 .length         = IO_SIZE,
1013                 .type           = MT_DEVICE
1014         },
1015 };
1016 
1017 static struct resource dm365_ks_resources[] = {
1018         {
1019                 /* registers */
1020                 .start = DM365_KEYSCAN_BASE,
1021                 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
1022                 .flags = IORESOURCE_MEM,
1023         },
1024         {
1025                 /* interrupt */
1026                 .start = IRQ_DM365_KEYINT,
1027                 .end = IRQ_DM365_KEYINT,
1028                 .flags = IORESOURCE_IRQ,
1029         },
1030 };
1031 
1032 static struct platform_device dm365_ks_device = {
1033         .name           = "davinci_keyscan",
1034         .id             = 0,
1035         .num_resources  = ARRAY_SIZE(dm365_ks_resources),
1036         .resource       = dm365_ks_resources,
1037 };
1038 
1039 /* Contents of JTAG ID register used to identify exact cpu type */
1040 static struct davinci_id dm365_ids[] = {
1041         {
1042                 .variant        = 0x0,
1043                 .part_no        = 0xb83e,
1044                 .manufacturer   = 0x017,
1045                 .cpu_id         = DAVINCI_CPU_ID_DM365,
1046                 .name           = "dm365_rev1.1",
1047         },
1048         {
1049                 .variant        = 0x8,
1050                 .part_no        = 0xb83e,
1051                 .manufacturer   = 0x017,
1052                 .cpu_id         = DAVINCI_CPU_ID_DM365,
1053                 .name           = "dm365_rev1.2",
1054         },
1055 };
1056 
1057 static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
1058 
1059 static struct davinci_timer_info dm365_timer_info = {
1060         .timers         = davinci_timer_instance,
1061         .clockevent_id  = T0_BOT,
1062         .clocksource_id = T0_TOP,
1063 };
1064 
1065 #define DM365_UART1_BASE        (IO_PHYS + 0x106000)
1066 
1067 static struct plat_serial8250_port dm365_serial0_platform_data[] = {
1068         {
1069                 .mapbase        = DAVINCI_UART0_BASE,
1070                 .irq            = IRQ_UARTINT0,
1071                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1072                                   UPF_IOREMAP,
1073                 .iotype         = UPIO_MEM,
1074                 .regshift       = 2,
1075         },
1076         {
1077                 .flags  = 0,
1078         }
1079 };
1080 static struct plat_serial8250_port dm365_serial1_platform_data[] = {
1081         {
1082                 .mapbase        = DM365_UART1_BASE,
1083                 .irq            = IRQ_UARTINT1,
1084                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1085                                   UPF_IOREMAP,
1086                 .iotype         = UPIO_MEM,
1087                 .regshift       = 2,
1088         },
1089         {
1090                 .flags  = 0,
1091         }
1092 };
1093 
1094 struct platform_device dm365_serial_device[] = {
1095         {
1096                 .name                   = "serial8250",
1097                 .id                     = PLAT8250_DEV_PLATFORM,
1098                 .dev                    = {
1099                         .platform_data  = dm365_serial0_platform_data,
1100                 }
1101         },
1102         {
1103                 .name                   = "serial8250",
1104                 .id                     = PLAT8250_DEV_PLATFORM1,
1105                 .dev                    = {
1106                         .platform_data  = dm365_serial1_platform_data,
1107                 }
1108         },
1109         {
1110         }
1111 };
1112 
1113 static const struct davinci_soc_info davinci_soc_info_dm365 = {
1114         .io_desc                = dm365_io_desc,
1115         .io_desc_num            = ARRAY_SIZE(dm365_io_desc),
1116         .jtag_id_reg            = 0x01c40028,
1117         .ids                    = dm365_ids,
1118         .ids_num                = ARRAY_SIZE(dm365_ids),
1119         .cpu_clks               = dm365_clks,
1120         .psc_bases              = dm365_psc_bases,
1121         .psc_bases_num          = ARRAY_SIZE(dm365_psc_bases),
1122         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
1123         .pinmux_pins            = dm365_pins,
1124         .pinmux_pins_num        = ARRAY_SIZE(dm365_pins),
1125         .intc_base              = DAVINCI_ARM_INTC_BASE,
1126         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
1127         .intc_irq_prios         = dm365_default_priorities,
1128         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
1129         .timer_info             = &dm365_timer_info,
1130         .emac_pdata             = &dm365_emac_pdata,
1131         .sram_dma               = 0x00010000,
1132         .sram_len               = SZ_32K,
1133 };
1134 
1135 void __init dm365_init_asp(void)
1136 {
1137         davinci_cfg_reg(DM365_MCBSP0_BDX);
1138         davinci_cfg_reg(DM365_MCBSP0_X);
1139         davinci_cfg_reg(DM365_MCBSP0_BFSX);
1140         davinci_cfg_reg(DM365_MCBSP0_BDR);
1141         davinci_cfg_reg(DM365_MCBSP0_R);
1142         davinci_cfg_reg(DM365_MCBSP0_BFSR);
1143         davinci_cfg_reg(DM365_EVT2_ASP_TX);
1144         davinci_cfg_reg(DM365_EVT3_ASP_RX);
1145         platform_device_register(&dm365_asp_device);
1146 }
1147 
1148 void __init dm365_init_vc(void)
1149 {
1150         davinci_cfg_reg(DM365_EVT2_VC_TX);
1151         davinci_cfg_reg(DM365_EVT3_VC_RX);
1152         platform_device_register(&dm365_vc_device);
1153 }
1154 
1155 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
1156 {
1157         dm365_ks_device.dev.platform_data = pdata;
1158         platform_device_register(&dm365_ks_device);
1159 }
1160 
1161 void __init dm365_init_rtc(void)
1162 {
1163         davinci_cfg_reg(DM365_INT_PRTCSS);
1164         platform_device_register(&dm365_rtc_device);
1165 }
1166 
1167 void __init dm365_init(void)
1168 {
1169         davinci_common_init(&davinci_soc_info_dm365);
1170         davinci_map_sysmod();
1171         davinci_clk_init(davinci_soc_info_dm365.cpu_clks);
1172 }
1173 
1174 static struct resource dm365_vpss_resources[] = {
1175         {
1176                 /* VPSS ISP5 Base address */
1177                 .name           = "isp5",
1178                 .start          = 0x01c70000,
1179                 .end            = 0x01c70000 + 0xff,
1180                 .flags          = IORESOURCE_MEM,
1181         },
1182         {
1183                 /* VPSS CLK Base address */
1184                 .name           = "vpss",
1185                 .start          = 0x01c70200,
1186                 .end            = 0x01c70200 + 0xff,
1187                 .flags          = IORESOURCE_MEM,
1188         },
1189 };
1190 
1191 static struct platform_device dm365_vpss_device = {
1192        .name                   = "vpss",
1193        .id                     = -1,
1194        .dev.platform_data      = "dm365_vpss",
1195        .num_resources          = ARRAY_SIZE(dm365_vpss_resources),
1196        .resource               = dm365_vpss_resources,
1197 };
1198 
1199 static struct resource vpfe_resources[] = {
1200         {
1201                 .start          = IRQ_VDINT0,
1202                 .end            = IRQ_VDINT0,
1203                 .flags          = IORESOURCE_IRQ,
1204         },
1205         {
1206                 .start          = IRQ_VDINT1,
1207                 .end            = IRQ_VDINT1,
1208                 .flags          = IORESOURCE_IRQ,
1209         },
1210 };
1211 
1212 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
1213 static struct platform_device vpfe_capture_dev = {
1214         .name           = CAPTURE_DRV_NAME,
1215         .id             = -1,
1216         .num_resources  = ARRAY_SIZE(vpfe_resources),
1217         .resource       = vpfe_resources,
1218         .dev = {
1219                 .dma_mask               = &vpfe_capture_dma_mask,
1220                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1221         },
1222 };
1223 
1224 static void dm365_isif_setup_pinmux(void)
1225 {
1226         davinci_cfg_reg(DM365_VIN_CAM_WEN);
1227         davinci_cfg_reg(DM365_VIN_CAM_VD);
1228         davinci_cfg_reg(DM365_VIN_CAM_HD);
1229         davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
1230         davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
1231 }
1232 
1233 static struct resource isif_resource[] = {
1234         /* ISIF Base address */
1235         {
1236                 .start          = 0x01c71000,
1237                 .end            = 0x01c71000 + 0x1ff,
1238                 .flags          = IORESOURCE_MEM,
1239         },
1240         /* ISIF Linearization table 0 */
1241         {
1242                 .start          = 0x1C7C000,
1243                 .end            = 0x1C7C000 + 0x2ff,
1244                 .flags          = IORESOURCE_MEM,
1245         },
1246         /* ISIF Linearization table 1 */
1247         {
1248                 .start          = 0x1C7C400,
1249                 .end            = 0x1C7C400 + 0x2ff,
1250                 .flags          = IORESOURCE_MEM,
1251         },
1252 };
1253 static struct platform_device dm365_isif_dev = {
1254         .name           = "isif",
1255         .id             = -1,
1256         .num_resources  = ARRAY_SIZE(isif_resource),
1257         .resource       = isif_resource,
1258         .dev = {
1259                 .dma_mask               = &vpfe_capture_dma_mask,
1260                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1261                 .platform_data          = dm365_isif_setup_pinmux,
1262         },
1263 };
1264 
1265 static struct resource dm365_osd_resources[] = {
1266         {
1267                 .start = DM365_OSD_BASE,
1268                 .end   = DM365_OSD_BASE + 0xff,
1269                 .flags = IORESOURCE_MEM,
1270         },
1271 };
1272 
1273 static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
1274 
1275 static struct platform_device dm365_osd_dev = {
1276         .name           = DM365_VPBE_OSD_SUBDEV_NAME,
1277         .id             = -1,
1278         .num_resources  = ARRAY_SIZE(dm365_osd_resources),
1279         .resource       = dm365_osd_resources,
1280         .dev            = {
1281                 .dma_mask               = &dm365_video_dma_mask,
1282                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1283         },
1284 };
1285 
1286 static struct resource dm365_venc_resources[] = {
1287         {
1288                 .start = IRQ_VENCINT,
1289                 .end   = IRQ_VENCINT,
1290                 .flags = IORESOURCE_IRQ,
1291         },
1292         /* venc registers io space */
1293         {
1294                 .start = DM365_VENC_BASE,
1295                 .end   = DM365_VENC_BASE + 0x177,
1296                 .flags = IORESOURCE_MEM,
1297         },
1298         /* vdaccfg registers io space */
1299         {
1300                 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
1301                 .end   = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
1302                 .flags = IORESOURCE_MEM,
1303         },
1304 };
1305 
1306 static struct resource dm365_v4l2_disp_resources[] = {
1307         {
1308                 .start = IRQ_VENCINT,
1309                 .end   = IRQ_VENCINT,
1310                 .flags = IORESOURCE_IRQ,
1311         },
1312         /* venc registers io space */
1313         {
1314                 .start = DM365_VENC_BASE,
1315                 .end   = DM365_VENC_BASE + 0x177,
1316                 .flags = IORESOURCE_MEM,
1317         },
1318 };
1319 
1320 static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
1321 {
1322         switch (if_type) {
1323         case MEDIA_BUS_FMT_SGRBG8_1X8:
1324                 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1325                 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1326                 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1327                 break;
1328         case MEDIA_BUS_FMT_YUYV10_1X20:
1329                 if (field)
1330                         davinci_cfg_reg(DM365_VOUT_FIELD);
1331                 else
1332                         davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1333                 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1334                 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1335                 break;
1336         default:
1337                 return -EINVAL;
1338         }
1339 
1340         return 0;
1341 }
1342 
1343 static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
1344                                   unsigned int pclock)
1345 {
1346         void __iomem *vpss_clkctl_reg;
1347         u32 val;
1348 
1349         vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
1350 
1351         switch (type) {
1352         case VPBE_ENC_STD:
1353                 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1354                 break;
1355         case VPBE_ENC_DV_TIMINGS:
1356                 if (pclock <= 27000000) {
1357                         val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1358                 } else {
1359                         /* set sysclk4 to output 74.25 MHz from pll1 */
1360                         val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
1361                               VPSS_VENCCLKEN_ENABLE;
1362                 }
1363                 break;
1364         default:
1365                 return -EINVAL;
1366         }
1367         writel(val, vpss_clkctl_reg);
1368 
1369         return 0;
1370 }
1371 
1372 static struct platform_device dm365_vpbe_display = {
1373         .name           = "vpbe-v4l2",
1374         .id             = -1,
1375         .num_resources  = ARRAY_SIZE(dm365_v4l2_disp_resources),
1376         .resource       = dm365_v4l2_disp_resources,
1377         .dev            = {
1378                 .dma_mask               = &dm365_video_dma_mask,
1379                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1380         },
1381 };
1382 
1383 static struct venc_platform_data dm365_venc_pdata = {
1384         .setup_pinmux   = dm365_vpbe_setup_pinmux,
1385         .setup_clock    = dm365_venc_setup_clock,
1386 };
1387 
1388 static struct platform_device dm365_venc_dev = {
1389         .name           = DM365_VPBE_VENC_SUBDEV_NAME,
1390         .id             = -1,
1391         .num_resources  = ARRAY_SIZE(dm365_venc_resources),
1392         .resource       = dm365_venc_resources,
1393         .dev            = {
1394                 .dma_mask               = &dm365_video_dma_mask,
1395                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1396                 .platform_data          = (void *)&dm365_venc_pdata,
1397         },
1398 };
1399 
1400 static struct platform_device dm365_vpbe_dev = {
1401         .name           = "vpbe_controller",
1402         .id             = -1,
1403         .dev            = {
1404                 .dma_mask               = &dm365_video_dma_mask,
1405                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1406         },
1407 };
1408 
1409 int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1410                                 struct vpbe_config *vpbe_cfg)
1411 {
1412         if (vpfe_cfg || vpbe_cfg)
1413                 platform_device_register(&dm365_vpss_device);
1414 
1415         if (vpfe_cfg) {
1416                 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1417                 platform_device_register(&dm365_isif_dev);
1418                 platform_device_register(&vpfe_capture_dev);
1419         }
1420         if (vpbe_cfg) {
1421                 dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1422                 platform_device_register(&dm365_osd_dev);
1423                 platform_device_register(&dm365_venc_dev);
1424                 platform_device_register(&dm365_vpbe_dev);
1425                 platform_device_register(&dm365_vpbe_display);
1426         }
1427 
1428         return 0;
1429 }
1430 
1431 static int __init dm365_init_devices(void)
1432 {
1433         struct platform_device *edma_pdev;
1434         int ret = 0;
1435 
1436         if (!cpu_is_davinci_dm365())
1437                 return 0;
1438 
1439         davinci_cfg_reg(DM365_INT_EDMA_CC);
1440         edma_pdev = platform_device_register_full(&dm365_edma_device);
1441         if (IS_ERR(edma_pdev)) {
1442                 pr_warn("%s: Failed to register eDMA\n", __func__);
1443                 return PTR_ERR(edma_pdev);
1444         }
1445 
1446         platform_device_register(&dm365_mdio_device);
1447         platform_device_register(&dm365_emac_device);
1448 
1449         ret = davinci_init_wdt();
1450         if (ret)
1451                 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1452 
1453         return ret;
1454 }
1455 postcore_initcall(dm365_init_devices);
1456 

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