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Linux/arch/arm/mach-davinci/gpio.c

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  1 /*
  2  * TI DaVinci GPIO Support
  3  *
  4  * Copyright (c) 2006-2007 David Brownell
  5  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  */
 12 
 13 #include <linux/errno.h>
 14 #include <linux/kernel.h>
 15 #include <linux/list.h>
 16 #include <linux/module.h>
 17 #include <linux/clk.h>
 18 #include <linux/err.h>
 19 #include <linux/io.h>
 20 #include <linux/irq.h>
 21 #include <linux/bitops.h>
 22 
 23 #include <mach/cputype.h>
 24 #include <mach/irqs.h>
 25 #include <mach/hardware.h>
 26 #include <mach/common.h>
 27 #include <mach/gpio.h>
 28 
 29 #include <asm/mach/irq.h>
 30 
 31 
 32 static DEFINE_SPINLOCK(gpio_lock);
 33 
 34 struct davinci_gpio {
 35         struct gpio_chip        chip;
 36         struct gpio_controller  *__iomem regs;
 37         int                     irq_base;
 38 };
 39 
 40 static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
 41 
 42 /* create a non-inlined version */
 43 static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
 44 {
 45         return __gpio_to_controller(gpio);
 46 }
 47 
 48 static int __init davinci_gpio_irq_setup(void);
 49 
 50 /*--------------------------------------------------------------------------*/
 51 
 52 /*
 53  * board setup code *MUST* set PINMUX0 and PINMUX1 as
 54  * needed, and enable the GPIO clock.
 55  */
 56 
 57 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
 58 {
 59         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
 60         struct gpio_controller *__iomem g = d->regs;
 61         u32 temp;
 62 
 63         spin_lock(&gpio_lock);
 64         temp = __raw_readl(&g->dir);
 65         temp |= (1 << offset);
 66         __raw_writel(temp, &g->dir);
 67         spin_unlock(&gpio_lock);
 68 
 69         return 0;
 70 }
 71 
 72 /*
 73  * Read the pin's value (works even if it's set up as output);
 74  * returns zero/nonzero.
 75  *
 76  * Note that changes are synched to the GPIO clock, so reading values back
 77  * right after you've set them may give old values.
 78  */
 79 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 80 {
 81         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
 82         struct gpio_controller *__iomem g = d->regs;
 83 
 84         return (1 << offset) & __raw_readl(&g->in_data);
 85 }
 86 
 87 static int
 88 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
 89 {
 90         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
 91         struct gpio_controller *__iomem g = d->regs;
 92         u32 temp;
 93         u32 mask = 1 << offset;
 94 
 95         spin_lock(&gpio_lock);
 96         temp = __raw_readl(&g->dir);
 97         temp &= ~mask;
 98         __raw_writel(mask, value ? &g->set_data : &g->clr_data);
 99         __raw_writel(temp, &g->dir);
100         spin_unlock(&gpio_lock);
101         return 0;
102 }
103 
104 /*
105  * Assuming the pin is muxed as a gpio output, set its output value.
106  */
107 static void
108 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
109 {
110         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
111         struct gpio_controller *__iomem g = d->regs;
112 
113         __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
114 }
115 
116 static int __init davinci_gpio_setup(void)
117 {
118         int i, base;
119         unsigned ngpio;
120         struct davinci_soc_info *soc_info = &davinci_soc_info;
121 
122         /*
123          * The gpio banks conceptually expose a segmented bitmap,
124          * and "ngpio" is one more than the largest zero-based
125          * bit index that's valid.
126          */
127         ngpio = soc_info->gpio_num;
128         if (ngpio == 0) {
129                 pr_err("GPIO setup:  how many GPIOs?\n");
130                 return -EINVAL;
131         }
132 
133         if (WARN_ON(DAVINCI_N_GPIO < ngpio))
134                 ngpio = DAVINCI_N_GPIO;
135 
136         for (i = 0, base = 0; base < ngpio; i++, base += 32) {
137                 chips[i].chip.label = "DaVinci";
138 
139                 chips[i].chip.direction_input = davinci_direction_in;
140                 chips[i].chip.get = davinci_gpio_get;
141                 chips[i].chip.direction_output = davinci_direction_out;
142                 chips[i].chip.set = davinci_gpio_set;
143 
144                 chips[i].chip.base = base;
145                 chips[i].chip.ngpio = ngpio - base;
146                 if (chips[i].chip.ngpio > 32)
147                         chips[i].chip.ngpio = 32;
148 
149                 chips[i].regs = gpio2controller(base);
150 
151                 gpiochip_add(&chips[i].chip);
152         }
153 
154         davinci_gpio_irq_setup();
155         return 0;
156 }
157 pure_initcall(davinci_gpio_setup);
158 
159 /*--------------------------------------------------------------------------*/
160 /*
161  * We expect irqs will normally be set up as input pins, but they can also be
162  * used as output pins ... which is convenient for testing.
163  *
164  * NOTE:  The first few GPIOs also have direct INTC hookups in addition
165  * to their GPIOBNK0 irq, with a bit less overhead.
166  *
167  * All those INTC hookups (direct, plus several IRQ banks) can also
168  * serve as EDMA event triggers.
169  */
170 
171 static void gpio_irq_disable(unsigned irq)
172 {
173         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
174         u32 mask = (u32) get_irq_data(irq);
175 
176         __raw_writel(mask, &g->clr_falling);
177         __raw_writel(mask, &g->clr_rising);
178 }
179 
180 static void gpio_irq_enable(unsigned irq)
181 {
182         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
183         u32 mask = (u32) get_irq_data(irq);
184         unsigned status = irq_desc[irq].status;
185 
186         status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
187         if (!status)
188                 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
189 
190         if (status & IRQ_TYPE_EDGE_FALLING)
191                 __raw_writel(mask, &g->set_falling);
192         if (status & IRQ_TYPE_EDGE_RISING)
193                 __raw_writel(mask, &g->set_rising);
194 }
195 
196 static int gpio_irq_type(unsigned irq, unsigned trigger)
197 {
198         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
199         u32 mask = (u32) get_irq_data(irq);
200 
201         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
202                 return -EINVAL;
203 
204         irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
205         irq_desc[irq].status |= trigger;
206 
207         /* don't enable the IRQ if it's currently disabled */
208         if (irq_desc[irq].depth == 0) {
209                 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
210                              ? &g->set_falling : &g->clr_falling);
211                 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
212                              ? &g->set_rising : &g->clr_rising);
213         }
214         return 0;
215 }
216 
217 static struct irq_chip gpio_irqchip = {
218         .name           = "GPIO",
219         .enable         = gpio_irq_enable,
220         .disable        = gpio_irq_disable,
221         .set_type       = gpio_irq_type,
222 };
223 
224 static void
225 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
226 {
227         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
228         u32 mask = 0xffff;
229 
230         /* we only care about one bank */
231         if (irq & 1)
232                 mask <<= 16;
233 
234         /* temporarily mask (level sensitive) parent IRQ */
235         desc->chip->mask(irq);
236         desc->chip->ack(irq);
237         while (1) {
238                 u32             status;
239                 int             n;
240                 int             res;
241 
242                 /* ack any irqs */
243                 status = __raw_readl(&g->intstat) & mask;
244                 if (!status)
245                         break;
246                 __raw_writel(status, &g->intstat);
247                 if (irq & 1)
248                         status >>= 16;
249 
250                 /* now demux them to the right lowlevel handler */
251                 n = (int)get_irq_data(irq);
252                 while (status) {
253                         res = ffs(status);
254                         n += res;
255                         generic_handle_irq(n - 1);
256                         status >>= res;
257                 }
258         }
259         desc->chip->unmask(irq);
260         /* now it may re-trigger */
261 }
262 
263 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
264 {
265         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
266 
267         if (d->irq_base >= 0)
268                 return d->irq_base + offset;
269         else
270                 return -ENODEV;
271 }
272 
273 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
274 {
275         struct davinci_soc_info *soc_info = &davinci_soc_info;
276 
277         /* NOTE:  we assume for now that only irqs in the first gpio_chip
278          * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
279          */
280         if (offset < soc_info->gpio_unbanked)
281                 return soc_info->gpio_irq + offset;
282         else
283                 return -ENODEV;
284 }
285 
286 static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
287 {
288         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
289         u32 mask = (u32) get_irq_data(irq);
290 
291         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
292                 return -EINVAL;
293 
294         __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
295                      ? &g->set_falling : &g->clr_falling);
296         __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
297                      ? &g->set_rising : &g->clr_rising);
298 
299         return 0;
300 }
301 
302 /*
303  * NOTE:  for suspend/resume, probably best to make a platform_device with
304  * suspend_late/resume_resume calls hooking into results of the set_wake()
305  * calls ... so if no gpios are wakeup events the clock can be disabled,
306  * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
307  * (dm6446) can be set appropriately for GPIOV33 pins.
308  */
309 
310 static int __init davinci_gpio_irq_setup(void)
311 {
312         unsigned        gpio, irq, bank;
313         struct clk      *clk;
314         u32             binten = 0;
315         unsigned        ngpio, bank_irq;
316         struct davinci_soc_info *soc_info = &davinci_soc_info;
317         struct gpio_controller  *__iomem g;
318 
319         ngpio = soc_info->gpio_num;
320 
321         bank_irq = soc_info->gpio_irq;
322         if (bank_irq == 0) {
323                 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
324                 return -EINVAL;
325         }
326 
327         clk = clk_get(NULL, "gpio");
328         if (IS_ERR(clk)) {
329                 printk(KERN_ERR "Error %ld getting gpio clock?\n",
330                        PTR_ERR(clk));
331                 return PTR_ERR(clk);
332         }
333         clk_enable(clk);
334 
335         /* Arrange gpio_to_irq() support, handling either direct IRQs or
336          * banked IRQs.  Having GPIOs in the first GPIO bank use direct
337          * IRQs, while the others use banked IRQs, would need some setup
338          * tweaks to recognize hardware which can do that.
339          */
340         for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
341                 chips[bank].chip.to_irq = gpio_to_irq_banked;
342                 chips[bank].irq_base = soc_info->gpio_unbanked
343                         ? -EINVAL
344                         : (soc_info->intc_irq_num + gpio);
345         }
346 
347         /*
348          * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
349          * controller only handling trigger modes.  We currently assume no
350          * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
351          */
352         if (soc_info->gpio_unbanked) {
353                 static struct irq_chip gpio_irqchip_unbanked;
354 
355                 /* pass "bank 0" GPIO IRQs to AINTC */
356                 chips[0].chip.to_irq = gpio_to_irq_unbanked;
357                 binten = BIT(0);
358 
359                 /* AINTC handles mask/unmask; GPIO handles triggering */
360                 irq = bank_irq;
361                 gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
362                 gpio_irqchip_unbanked.name = "GPIO-AINTC";
363                 gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
364 
365                 /* default trigger: both edges */
366                 g = gpio2controller(0);
367                 __raw_writel(~0, &g->set_falling);
368                 __raw_writel(~0, &g->set_rising);
369 
370                 /* set the direct IRQs up to use that irqchip */
371                 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
372                         set_irq_chip(irq, &gpio_irqchip_unbanked);
373                         set_irq_data(irq, (void *) __gpio_mask(gpio));
374                         set_irq_chip_data(irq, g);
375                         irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
376                 }
377 
378                 goto done;
379         }
380 
381         /*
382          * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
383          * then chain through our own handler.
384          */
385         for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
386                         gpio < ngpio;
387                         bank++, bank_irq++) {
388                 unsigned                i;
389 
390                 /* disabled by default, enabled only as needed */
391                 g = gpio2controller(gpio);
392                 __raw_writel(~0, &g->clr_falling);
393                 __raw_writel(~0, &g->clr_rising);
394 
395                 /* set up all irqs in this bank */
396                 set_irq_chained_handler(bank_irq, gpio_irq_handler);
397                 set_irq_chip_data(bank_irq, g);
398                 set_irq_data(bank_irq, (void *)irq);
399 
400                 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
401                         set_irq_chip(irq, &gpio_irqchip);
402                         set_irq_chip_data(irq, g);
403                         set_irq_data(irq, (void *) __gpio_mask(gpio));
404                         set_irq_handler(irq, handle_simple_irq);
405                         set_irq_flags(irq, IRQF_VALID);
406                 }
407 
408                 binten |= BIT(bank);
409         }
410 
411 done:
412         /* BINTEN -- per-bank interrupt enable. genirq would also let these
413          * bits be set/cleared dynamically.
414          */
415         __raw_writel(binten, soc_info->gpio_base + 0x08);
416 
417         printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
418 
419         return 0;
420 }
421 

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