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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-dove/common.c

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  1 /*
  2  * arch/arm/mach-dove/common.c
  3  *
  4  * Core functions for Marvell Dove 88AP510 System On Chip
  5  *
  6  * This file is licensed under the terms of the GNU General Public
  7  * License version 2.  This program is licensed "as is" without any
  8  * warranty of any kind, whether express or implied.
  9  */
 10 
 11 #include <linux/clk-provider.h>
 12 #include <linux/dma-mapping.h>
 13 #include <linux/init.h>
 14 #include <linux/of.h>
 15 #include <linux/of_platform.h>
 16 #include <linux/platform_data/dma-mv_xor.h>
 17 #include <linux/platform_data/usb-ehci-orion.h>
 18 #include <linux/platform_device.h>
 19 #include <asm/hardware/cache-tauros2.h>
 20 #include <asm/mach/arch.h>
 21 #include <asm/mach/map.h>
 22 #include <asm/mach/time.h>
 23 #include <mach/bridge-regs.h>
 24 #include <mach/pm.h>
 25 #include <plat/common.h>
 26 #include <plat/irq.h>
 27 #include <plat/time.h>
 28 #include "common.h"
 29 
 30 /* These can go away once Dove uses the mvebu-mbus DT binding */
 31 #define DOVE_MBUS_PCIE0_MEM_TARGET    0x4
 32 #define DOVE_MBUS_PCIE0_MEM_ATTR      0xe8
 33 #define DOVE_MBUS_PCIE0_IO_TARGET     0x4
 34 #define DOVE_MBUS_PCIE0_IO_ATTR       0xe0
 35 #define DOVE_MBUS_PCIE1_MEM_TARGET    0x8
 36 #define DOVE_MBUS_PCIE1_MEM_ATTR      0xe8
 37 #define DOVE_MBUS_PCIE1_IO_TARGET     0x8
 38 #define DOVE_MBUS_PCIE1_IO_ATTR       0xe0
 39 #define DOVE_MBUS_CESA_TARGET         0x3
 40 #define DOVE_MBUS_CESA_ATTR           0x1
 41 #define DOVE_MBUS_BOOTROM_TARGET      0x1
 42 #define DOVE_MBUS_BOOTROM_ATTR        0xfd
 43 #define DOVE_MBUS_SCRATCHPAD_TARGET   0xd
 44 #define DOVE_MBUS_SCRATCHPAD_ATTR     0x0
 45 
 46 /*****************************************************************************
 47  * I/O Address Mapping
 48  ****************************************************************************/
 49 static struct map_desc dove_io_desc[] __initdata = {
 50         {
 51                 .virtual        = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
 52                 .pfn            = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
 53                 .length         = DOVE_SB_REGS_SIZE,
 54                 .type           = MT_DEVICE,
 55         }, {
 56                 .virtual        = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
 57                 .pfn            = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
 58                 .length         = DOVE_NB_REGS_SIZE,
 59                 .type           = MT_DEVICE,
 60         },
 61 };
 62 
 63 void __init dove_map_io(void)
 64 {
 65         iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
 66 }
 67 
 68 /*****************************************************************************
 69  * CLK tree
 70  ****************************************************************************/
 71 static int dove_tclk;
 72 
 73 static DEFINE_SPINLOCK(gating_lock);
 74 static struct clk *tclk;
 75 
 76 static struct clk __init *dove_register_gate(const char *name,
 77                                              const char *parent, u8 bit_idx)
 78 {
 79         return clk_register_gate(NULL, name, parent, 0,
 80                                  (void __iomem *)CLOCK_GATING_CONTROL,
 81                                  bit_idx, 0, &gating_lock);
 82 }
 83 
 84 static void __init dove_clk_init(void)
 85 {
 86         struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
 87         struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
 88         struct clk *xor0, *xor1, *ge, *gephy;
 89 
 90         tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
 91                                        dove_tclk);
 92 
 93         usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
 94         usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
 95         sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
 96         pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
 97         pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
 98         sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
 99         sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
100         nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
101         camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
102         i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
103         i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
104         crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
105         ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
106         pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
107         xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
108         xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
109         gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
110         ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
111 
112         orion_clkdev_add(NULL, "orion_spi.0", tclk);
113         orion_clkdev_add(NULL, "orion_spi.1", tclk);
114         orion_clkdev_add(NULL, "orion_wdt", tclk);
115         orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
116 
117         orion_clkdev_add(NULL, "orion-ehci.0", usb0);
118         orion_clkdev_add(NULL, "orion-ehci.1", usb1);
119         orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
120         orion_clkdev_add(NULL, "sata_mv.0", sata);
121         orion_clkdev_add("", "pcie", pex0);
122         orion_clkdev_add("1", "pcie", pex1);
123         orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
124         orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
125         orion_clkdev_add(NULL, "orion_nand", nand);
126         orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
127         orion_clkdev_add(NULL, "mvebu-audio.0", i2s0);
128         orion_clkdev_add(NULL, "mvebu-audio.1", i2s1);
129         orion_clkdev_add(NULL, "mv_crypto", crypto);
130         orion_clkdev_add(NULL, "dove-ac97", ac97);
131         orion_clkdev_add(NULL, "dove-pdma", pdma);
132         orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
133         orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
134 }
135 
136 /*****************************************************************************
137  * EHCI0
138  ****************************************************************************/
139 void __init dove_ehci0_init(void)
140 {
141         orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
142 }
143 
144 /*****************************************************************************
145  * EHCI1
146  ****************************************************************************/
147 void __init dove_ehci1_init(void)
148 {
149         orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
150 }
151 
152 /*****************************************************************************
153  * GE00
154  ****************************************************************************/
155 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
156 {
157         orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
158                         IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
159                         1600);
160 }
161 
162 /*****************************************************************************
163  * SoC RTC
164  ****************************************************************************/
165 static void __init dove_rtc_init(void)
166 {
167         orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
168 }
169 
170 /*****************************************************************************
171  * SATA
172  ****************************************************************************/
173 void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
174 {
175         orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
176 
177 }
178 
179 /*****************************************************************************
180  * UART0
181  ****************************************************************************/
182 void __init dove_uart0_init(void)
183 {
184         orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
185                          IRQ_DOVE_UART_0, tclk);
186 }
187 
188 /*****************************************************************************
189  * UART1
190  ****************************************************************************/
191 void __init dove_uart1_init(void)
192 {
193         orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
194                          IRQ_DOVE_UART_1, tclk);
195 }
196 
197 /*****************************************************************************
198  * UART2
199  ****************************************************************************/
200 void __init dove_uart2_init(void)
201 {
202         orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
203                          IRQ_DOVE_UART_2, tclk);
204 }
205 
206 /*****************************************************************************
207  * UART3
208  ****************************************************************************/
209 void __init dove_uart3_init(void)
210 {
211         orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
212                          IRQ_DOVE_UART_3, tclk);
213 }
214 
215 /*****************************************************************************
216  * SPI
217  ****************************************************************************/
218 void __init dove_spi0_init(void)
219 {
220         orion_spi_init(DOVE_SPI0_PHYS_BASE);
221 }
222 
223 void __init dove_spi1_init(void)
224 {
225         orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
226 }
227 
228 /*****************************************************************************
229  * I2C
230  ****************************************************************************/
231 void __init dove_i2c_init(void)
232 {
233         orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
234 }
235 
236 /*****************************************************************************
237  * Time handling
238  ****************************************************************************/
239 void __init dove_init_early(void)
240 {
241         orion_time_set_base(TIMER_VIRT_BASE);
242         mvebu_mbus_init("marvell,dove-mbus",
243                         BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
244                         DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
245 }
246 
247 static int __init dove_find_tclk(void)
248 {
249         return 166666667;
250 }
251 
252 void __init dove_timer_init(void)
253 {
254         dove_tclk = dove_find_tclk();
255         orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
256                         IRQ_DOVE_BRIDGE, dove_tclk);
257 }
258 
259 /*****************************************************************************
260  * XOR 0
261  ****************************************************************************/
262 static void __init dove_xor0_init(void)
263 {
264         orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
265                         IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
266 }
267 
268 /*****************************************************************************
269  * XOR 1
270  ****************************************************************************/
271 static void __init dove_xor1_init(void)
272 {
273         orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
274                         IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
275 }
276 
277 /*****************************************************************************
278  * SDIO
279  ****************************************************************************/
280 static u64 sdio_dmamask = DMA_BIT_MASK(32);
281 
282 static struct resource dove_sdio0_resources[] = {
283         {
284                 .start  = DOVE_SDIO0_PHYS_BASE,
285                 .end    = DOVE_SDIO0_PHYS_BASE + 0xff,
286                 .flags  = IORESOURCE_MEM,
287         }, {
288                 .start  = IRQ_DOVE_SDIO0,
289                 .end    = IRQ_DOVE_SDIO0,
290                 .flags  = IORESOURCE_IRQ,
291         },
292 };
293 
294 static struct platform_device dove_sdio0 = {
295         .name           = "sdhci-dove",
296         .id             = 0,
297         .dev            = {
298                 .dma_mask               = &sdio_dmamask,
299                 .coherent_dma_mask      = DMA_BIT_MASK(32),
300         },
301         .resource       = dove_sdio0_resources,
302         .num_resources  = ARRAY_SIZE(dove_sdio0_resources),
303 };
304 
305 void __init dove_sdio0_init(void)
306 {
307         platform_device_register(&dove_sdio0);
308 }
309 
310 static struct resource dove_sdio1_resources[] = {
311         {
312                 .start  = DOVE_SDIO1_PHYS_BASE,
313                 .end    = DOVE_SDIO1_PHYS_BASE + 0xff,
314                 .flags  = IORESOURCE_MEM,
315         }, {
316                 .start  = IRQ_DOVE_SDIO1,
317                 .end    = IRQ_DOVE_SDIO1,
318                 .flags  = IORESOURCE_IRQ,
319         },
320 };
321 
322 static struct platform_device dove_sdio1 = {
323         .name           = "sdhci-dove",
324         .id             = 1,
325         .dev            = {
326                 .dma_mask               = &sdio_dmamask,
327                 .coherent_dma_mask      = DMA_BIT_MASK(32),
328         },
329         .resource       = dove_sdio1_resources,
330         .num_resources  = ARRAY_SIZE(dove_sdio1_resources),
331 };
332 
333 void __init dove_sdio1_init(void)
334 {
335         platform_device_register(&dove_sdio1);
336 }
337 
338 void __init dove_setup_cpu_wins(void)
339 {
340         /*
341          * The PCIe windows will no longer be statically allocated
342          * here once Dove is migrated to the pci-mvebu driver. The
343          * non-PCIe windows will no longer be created here once Dove
344          * fully moves to DT.
345          */
346         mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
347                                           DOVE_MBUS_PCIE0_IO_ATTR,
348                                           DOVE_PCIE0_IO_PHYS_BASE,
349                                           DOVE_PCIE0_IO_SIZE,
350                                           DOVE_PCIE0_IO_BUS_BASE);
351         mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
352                                           DOVE_MBUS_PCIE1_IO_ATTR,
353                                           DOVE_PCIE1_IO_PHYS_BASE,
354                                           DOVE_PCIE1_IO_SIZE,
355                                           DOVE_PCIE1_IO_BUS_BASE);
356         mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
357                                     DOVE_MBUS_PCIE0_MEM_ATTR,
358                                     DOVE_PCIE0_MEM_PHYS_BASE,
359                                     DOVE_PCIE0_MEM_SIZE);
360         mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
361                                     DOVE_MBUS_PCIE1_MEM_ATTR,
362                                     DOVE_PCIE1_MEM_PHYS_BASE,
363                                     DOVE_PCIE1_MEM_SIZE);
364         mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
365                                     DOVE_MBUS_CESA_ATTR,
366                                     DOVE_CESA_PHYS_BASE,
367                                     DOVE_CESA_SIZE);
368         mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
369                                     DOVE_MBUS_BOOTROM_ATTR,
370                                     DOVE_BOOTROM_PHYS_BASE,
371                                     DOVE_BOOTROM_SIZE);
372         mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
373                                     DOVE_MBUS_SCRATCHPAD_ATTR,
374                                     DOVE_SCRATCHPAD_PHYS_BASE,
375                                     DOVE_SCRATCHPAD_SIZE);
376 }
377 
378 void __init dove_init(void)
379 {
380         pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
381                 (dove_tclk + 499999) / 1000000);
382 
383 #ifdef CONFIG_CACHE_TAUROS2
384         tauros2_init(0);
385 #endif
386         dove_setup_cpu_wins();
387 
388         /* Setup root of clk tree */
389         dove_clk_init();
390 
391         /* internal devices that every board has */
392         dove_rtc_init();
393         dove_xor0_init();
394         dove_xor1_init();
395 }
396 
397 void dove_restart(enum reboot_mode mode, const char *cmd)
398 {
399         /*
400          * Enable soft reset to assert RSTOUTn.
401          */
402         writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
403 
404         /*
405          * Assert soft reset.
406          */
407         writel(SOFT_RESET, SYSTEM_SOFT_RESET);
408 
409         while (1)
410                 ;
411 }
412 

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