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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-ep93xx/core.c

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  1 /*
  2  * arch/arm/mach-ep93xx/core.c
  3  * Core routines for Cirrus EP93xx chips.
  4  *
  5  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
  6  * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
  7  *
  8  * Thanks go to Michael Burian and Ray Lehtiniemi for their key
  9  * role in the ep93xx linux community.
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License as published by
 13  * the Free Software Foundation; either version 2 of the License, or (at
 14  * your option) any later version.
 15  */
 16 
 17 #include <linux/kernel.h>
 18 #include <linux/init.h>
 19 #include <linux/platform_device.h>
 20 #include <linux/interrupt.h>
 21 #include <linux/dma-mapping.h>
 22 #include <linux/timex.h>
 23 #include <linux/io.h>
 24 #include <linux/gpio.h>
 25 #include <linux/leds.h>
 26 #include <linux/termios.h>
 27 #include <linux/amba/bus.h>
 28 #include <linux/amba/serial.h>
 29 #include <linux/i2c.h>
 30 #include <linux/i2c-gpio.h>
 31 
 32 #include <mach/hardware.h>
 33 #include <mach/fb.h>
 34 
 35 #include <asm/mach/map.h>
 36 #include <asm/mach/time.h>
 37 #include <asm/mach/irq.h>
 38 
 39 #include <asm/hardware/vic.h>
 40 
 41 
 42 /*************************************************************************
 43  * Static I/O mappings that are needed for all EP93xx platforms
 44  *************************************************************************/
 45 static struct map_desc ep93xx_io_desc[] __initdata = {
 46         {
 47                 .virtual        = EP93XX_AHB_VIRT_BASE,
 48                 .pfn            = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
 49                 .length         = EP93XX_AHB_SIZE,
 50                 .type           = MT_DEVICE,
 51         }, {
 52                 .virtual        = EP93XX_APB_VIRT_BASE,
 53                 .pfn            = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
 54                 .length         = EP93XX_APB_SIZE,
 55                 .type           = MT_DEVICE,
 56         },
 57 };
 58 
 59 void __init ep93xx_map_io(void)
 60 {
 61         iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
 62 }
 63 
 64 
 65 /*************************************************************************
 66  * Timer handling for EP93xx
 67  *************************************************************************
 68  * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and
 69  * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
 70  * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,
 71  * is free-running, and can't generate interrupts.
 72  *
 73  * The 508 kHz timers are ideal for use for the timer interrupt, as the
 74  * most common values of HZ divide 508 kHz nicely.  We pick one of the 16
 75  * bit timers (timer 1) since we don't need more than 16 bits of reload
 76  * value as long as HZ >= 8.
 77  *
 78  * The higher clock rate of timer 4 makes it a better choice than the
 79  * other timers for use in gettimeoffset(), while the fact that it can't
 80  * generate interrupts means we don't have to worry about not being able
 81  * to use this timer for something else.  We also use timer 4 for keeping
 82  * track of lost jiffies.
 83  */
 84 static unsigned int last_jiffy_time;
 85 
 86 #define TIMER4_TICKS_PER_JIFFY          DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
 87 
 88 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
 89 {
 90         __raw_writel(1, EP93XX_TIMER1_CLEAR);
 91         while ((signed long)
 92                 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
 93                                                 >= TIMER4_TICKS_PER_JIFFY) {
 94                 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
 95                 timer_tick();
 96         }
 97 
 98         return IRQ_HANDLED;
 99 }
100 
101 static struct irqaction ep93xx_timer_irq = {
102         .name           = "ep93xx timer",
103         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
104         .handler        = ep93xx_timer_interrupt,
105 };
106 
107 static void __init ep93xx_timer_init(void)
108 {
109         /* Enable periodic HZ timer.  */
110         __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
111         __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
112         __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
113 
114         /* Enable lost jiffy timer.  */
115         __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
116 
117         setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
118 }
119 
120 static unsigned long ep93xx_gettimeoffset(void)
121 {
122         int offset;
123 
124         offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
125 
126         /* Calculate (1000000 / 983040) * offset.  */
127         return offset + (53 * offset / 3072);
128 }
129 
130 struct sys_timer ep93xx_timer = {
131         .init           = ep93xx_timer_init,
132         .offset         = ep93xx_gettimeoffset,
133 };
134 
135 
136 /*************************************************************************
137  * GPIO handling for EP93xx
138  *************************************************************************/
139 static unsigned char gpio_int_unmasked[3];
140 static unsigned char gpio_int_enabled[3];
141 static unsigned char gpio_int_type1[3];
142 static unsigned char gpio_int_type2[3];
143 static unsigned char gpio_int_debounce[3];
144 
145 /* Port ordering is: A B F */
146 static const u8 int_type1_register_offset[3]    = { 0x90, 0xac, 0x4c };
147 static const u8 int_type2_register_offset[3]    = { 0x94, 0xb0, 0x50 };
148 static const u8 eoi_register_offset[3]          = { 0x98, 0xb4, 0x54 };
149 static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x58 };
150 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
151 
152 void ep93xx_gpio_update_int_params(unsigned port)
153 {
154         BUG_ON(port > 2);
155 
156         __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
157 
158         __raw_writeb(gpio_int_type2[port],
159                 EP93XX_GPIO_REG(int_type2_register_offset[port]));
160 
161         __raw_writeb(gpio_int_type1[port],
162                 EP93XX_GPIO_REG(int_type1_register_offset[port]));
163 
164         __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
165                 EP93XX_GPIO_REG(int_en_register_offset[port]));
166 }
167 
168 void ep93xx_gpio_int_mask(unsigned line)
169 {
170         gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
171 }
172 
173 void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
174 {
175         int line = irq_to_gpio(irq);
176         int port = line >> 3;
177         int port_mask = 1 << (line & 7);
178 
179         if (enable)
180                 gpio_int_debounce[port] |= port_mask;
181         else
182                 gpio_int_debounce[port] &= ~port_mask;
183 
184         __raw_writeb(gpio_int_debounce[port],
185                 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
186 }
187 EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
188 
189 /*************************************************************************
190  * EP93xx IRQ handling
191  *************************************************************************/
192 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
193 {
194         unsigned char status;
195         int i;
196 
197         status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
198         for (i = 0; i < 8; i++) {
199                 if (status & (1 << i)) {
200                         int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
201                         generic_handle_irq(gpio_irq);
202                 }
203         }
204 
205         status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
206         for (i = 0; i < 8; i++) {
207                 if (status & (1 << i)) {
208                         int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
209                         generic_handle_irq(gpio_irq);
210                 }
211         }
212 }
213 
214 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
215 {
216         /*
217          * map discontiguous hw irq range to continous sw irq range:
218          *
219          *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
220          */
221         int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
222         int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
223 
224         generic_handle_irq(gpio_irq);
225 }
226 
227 static void ep93xx_gpio_irq_ack(unsigned int irq)
228 {
229         int line = irq_to_gpio(irq);
230         int port = line >> 3;
231         int port_mask = 1 << (line & 7);
232 
233         if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
234                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
235                 ep93xx_gpio_update_int_params(port);
236         }
237 
238         __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
239 }
240 
241 static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
242 {
243         int line = irq_to_gpio(irq);
244         int port = line >> 3;
245         int port_mask = 1 << (line & 7);
246 
247         if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
248                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
249 
250         gpio_int_unmasked[port] &= ~port_mask;
251         ep93xx_gpio_update_int_params(port);
252 
253         __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
254 }
255 
256 static void ep93xx_gpio_irq_mask(unsigned int irq)
257 {
258         int line = irq_to_gpio(irq);
259         int port = line >> 3;
260 
261         gpio_int_unmasked[port] &= ~(1 << (line & 7));
262         ep93xx_gpio_update_int_params(port);
263 }
264 
265 static void ep93xx_gpio_irq_unmask(unsigned int irq)
266 {
267         int line = irq_to_gpio(irq);
268         int port = line >> 3;
269 
270         gpio_int_unmasked[port] |= 1 << (line & 7);
271         ep93xx_gpio_update_int_params(port);
272 }
273 
274 
275 /*
276  * gpio_int_type1 controls whether the interrupt is level (0) or
277  * edge (1) triggered, while gpio_int_type2 controls whether it
278  * triggers on low/falling (0) or high/rising (1).
279  */
280 static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
281 {
282         struct irq_desc *desc = irq_desc + irq;
283         const int gpio = irq_to_gpio(irq);
284         const int port = gpio >> 3;
285         const int port_mask = 1 << (gpio & 7);
286 
287         gpio_direction_input(gpio);
288 
289         switch (type) {
290         case IRQ_TYPE_EDGE_RISING:
291                 gpio_int_type1[port] |= port_mask;
292                 gpio_int_type2[port] |= port_mask;
293                 desc->handle_irq = handle_edge_irq;
294                 break;
295         case IRQ_TYPE_EDGE_FALLING:
296                 gpio_int_type1[port] |= port_mask;
297                 gpio_int_type2[port] &= ~port_mask;
298                 desc->handle_irq = handle_edge_irq;
299                 break;
300         case IRQ_TYPE_LEVEL_HIGH:
301                 gpio_int_type1[port] &= ~port_mask;
302                 gpio_int_type2[port] |= port_mask;
303                 desc->handle_irq = handle_level_irq;
304                 break;
305         case IRQ_TYPE_LEVEL_LOW:
306                 gpio_int_type1[port] &= ~port_mask;
307                 gpio_int_type2[port] &= ~port_mask;
308                 desc->handle_irq = handle_level_irq;
309                 break;
310         case IRQ_TYPE_EDGE_BOTH:
311                 gpio_int_type1[port] |= port_mask;
312                 /* set initial polarity based on current input level */
313                 if (gpio_get_value(gpio))
314                         gpio_int_type2[port] &= ~port_mask; /* falling */
315                 else
316                         gpio_int_type2[port] |= port_mask; /* rising */
317                 desc->handle_irq = handle_edge_irq;
318                 break;
319         default:
320                 pr_err("ep93xx: failed to set irq type %d for gpio %d\n",
321                        type, gpio);
322                 return -EINVAL;
323         }
324 
325         gpio_int_enabled[port] |= port_mask;
326 
327         desc->status &= ~IRQ_TYPE_SENSE_MASK;
328         desc->status |= type & IRQ_TYPE_SENSE_MASK;
329 
330         ep93xx_gpio_update_int_params(port);
331 
332         return 0;
333 }
334 
335 static struct irq_chip ep93xx_gpio_irq_chip = {
336         .name           = "GPIO",
337         .ack            = ep93xx_gpio_irq_ack,
338         .mask_ack       = ep93xx_gpio_irq_mask_ack,
339         .mask           = ep93xx_gpio_irq_mask,
340         .unmask         = ep93xx_gpio_irq_unmask,
341         .set_type       = ep93xx_gpio_irq_type,
342 };
343 
344 
345 void __init ep93xx_init_irq(void)
346 {
347         int gpio_irq;
348 
349         vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
350         vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
351 
352         for (gpio_irq = gpio_to_irq(0);
353              gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
354                 set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
355                 set_irq_handler(gpio_irq, handle_level_irq);
356                 set_irq_flags(gpio_irq, IRQF_VALID);
357         }
358 
359         set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
360         set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
361         set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
362         set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
363         set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
364         set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
365         set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
366         set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
367         set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
368 }
369 
370 
371 /*************************************************************************
372  * EP93xx System Controller Software Locked register handling
373  *************************************************************************/
374 
375 /*
376  * syscon_swlock prevents anything else from writing to the syscon
377  * block while a software locked register is being written.
378  */
379 static DEFINE_SPINLOCK(syscon_swlock);
380 
381 void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
382 {
383         unsigned long flags;
384 
385         spin_lock_irqsave(&syscon_swlock, flags);
386 
387         __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
388         __raw_writel(val, reg);
389 
390         spin_unlock_irqrestore(&syscon_swlock, flags);
391 }
392 EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
393 
394 void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
395 {
396         unsigned long flags;
397         unsigned int val;
398 
399         spin_lock_irqsave(&syscon_swlock, flags);
400 
401         val = __raw_readl(EP93XX_SYSCON_DEVCFG);
402         val |= set_bits;
403         val &= ~clear_bits;
404         __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
405         __raw_writel(val, EP93XX_SYSCON_DEVCFG);
406 
407         spin_unlock_irqrestore(&syscon_swlock, flags);
408 }
409 EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
410 
411 
412 /*************************************************************************
413  * EP93xx peripheral handling
414  *************************************************************************/
415 #define EP93XX_UART_MCR_OFFSET          (0x0100)
416 
417 static void ep93xx_uart_set_mctrl(struct amba_device *dev,
418                                   void __iomem *base, unsigned int mctrl)
419 {
420         unsigned int mcr;
421 
422         mcr = 0;
423         if (!(mctrl & TIOCM_RTS))
424                 mcr |= 2;
425         if (!(mctrl & TIOCM_DTR))
426                 mcr |= 1;
427 
428         __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
429 }
430 
431 static struct amba_pl010_data ep93xx_uart_data = {
432         .set_mctrl      = ep93xx_uart_set_mctrl,
433 };
434 
435 static struct amba_device uart1_device = {
436         .dev            = {
437                 .init_name      = "apb:uart1",
438                 .platform_data  = &ep93xx_uart_data,
439         },
440         .res            = {
441                 .start  = EP93XX_UART1_PHYS_BASE,
442                 .end    = EP93XX_UART1_PHYS_BASE + 0x0fff,
443                 .flags  = IORESOURCE_MEM,
444         },
445         .irq            = { IRQ_EP93XX_UART1, NO_IRQ },
446         .periphid       = 0x00041010,
447 };
448 
449 static struct amba_device uart2_device = {
450         .dev            = {
451                 .init_name      = "apb:uart2",
452                 .platform_data  = &ep93xx_uart_data,
453         },
454         .res            = {
455                 .start  = EP93XX_UART2_PHYS_BASE,
456                 .end    = EP93XX_UART2_PHYS_BASE + 0x0fff,
457                 .flags  = IORESOURCE_MEM,
458         },
459         .irq            = { IRQ_EP93XX_UART2, NO_IRQ },
460         .periphid       = 0x00041010,
461 };
462 
463 static struct amba_device uart3_device = {
464         .dev            = {
465                 .init_name      = "apb:uart3",
466                 .platform_data  = &ep93xx_uart_data,
467         },
468         .res            = {
469                 .start  = EP93XX_UART3_PHYS_BASE,
470                 .end    = EP93XX_UART3_PHYS_BASE + 0x0fff,
471                 .flags  = IORESOURCE_MEM,
472         },
473         .irq            = { IRQ_EP93XX_UART3, NO_IRQ },
474         .periphid       = 0x00041010,
475 };
476 
477 
478 static struct resource ep93xx_rtc_resource[] = {
479         {
480                 .start          = EP93XX_RTC_PHYS_BASE,
481                 .end            = EP93XX_RTC_PHYS_BASE + 0x10c - 1,
482                 .flags          = IORESOURCE_MEM,
483         },
484 };
485 
486 static struct platform_device ep93xx_rtc_device = {
487         .name           = "ep93xx-rtc",
488         .id             = -1,
489         .num_resources  = ARRAY_SIZE(ep93xx_rtc_resource),
490         .resource       = ep93xx_rtc_resource,
491 };
492 
493 
494 static struct resource ep93xx_ohci_resources[] = {
495         [0] = {
496                 .start  = EP93XX_USB_PHYS_BASE,
497                 .end    = EP93XX_USB_PHYS_BASE + 0x0fff,
498                 .flags  = IORESOURCE_MEM,
499         },
500         [1] = {
501                 .start  = IRQ_EP93XX_USB,
502                 .end    = IRQ_EP93XX_USB,
503                 .flags  = IORESOURCE_IRQ,
504         },
505 };
506 
507 
508 static struct platform_device ep93xx_ohci_device = {
509         .name           = "ep93xx-ohci",
510         .id             = -1,
511         .dev            = {
512                 .dma_mask               = &ep93xx_ohci_device.dev.coherent_dma_mask,
513                 .coherent_dma_mask      = DMA_BIT_MASK(32),
514         },
515         .num_resources  = ARRAY_SIZE(ep93xx_ohci_resources),
516         .resource       = ep93xx_ohci_resources,
517 };
518 
519 static struct ep93xx_eth_data ep93xx_eth_data;
520 
521 static struct resource ep93xx_eth_resource[] = {
522         {
523                 .start  = EP93XX_ETHERNET_PHYS_BASE,
524                 .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
525                 .flags  = IORESOURCE_MEM,
526         }, {
527                 .start  = IRQ_EP93XX_ETHERNET,
528                 .end    = IRQ_EP93XX_ETHERNET,
529                 .flags  = IORESOURCE_IRQ,
530         }
531 };
532 
533 static struct platform_device ep93xx_eth_device = {
534         .name           = "ep93xx-eth",
535         .id             = -1,
536         .dev            = {
537                 .platform_data  = &ep93xx_eth_data,
538         },
539         .num_resources  = ARRAY_SIZE(ep93xx_eth_resource),
540         .resource       = ep93xx_eth_resource,
541 };
542 
543 void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
544 {
545         if (copy_addr)
546                 memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6);
547 
548         ep93xx_eth_data = *data;
549         platform_device_register(&ep93xx_eth_device);
550 }
551 
552 
553 /*************************************************************************
554  * EP93xx i2c peripheral handling
555  *************************************************************************/
556 static struct i2c_gpio_platform_data ep93xx_i2c_data;
557 
558 static struct platform_device ep93xx_i2c_device = {
559         .name                   = "i2c-gpio",
560         .id                     = 0,
561         .dev.platform_data      = &ep93xx_i2c_data,
562 };
563 
564 void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
565                                 struct i2c_board_info *devices, int num)
566 {
567         /*
568          * Set the EEPROM interface pin drive type control.
569          * Defines the driver type for the EECLK and EEDAT pins as either
570          * open drain, which will require an external pull-up, or a normal
571          * CMOS driver.
572          */
573         if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT)
574                 pr_warning("ep93xx: sda != EEDAT, open drain has no effect\n");
575         if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK)
576                 pr_warning("ep93xx: scl != EECLK, open drain has no effect\n");
577 
578         __raw_writel((data->sda_is_open_drain << 1) |
579                      (data->scl_is_open_drain << 0),
580                      EP93XX_GPIO_EEDRIVE);
581 
582         ep93xx_i2c_data = *data;
583         i2c_register_board_info(0, devices, num);
584         platform_device_register(&ep93xx_i2c_device);
585 }
586 
587 
588 /*************************************************************************
589  * EP93xx LEDs
590  *************************************************************************/
591 static struct gpio_led ep93xx_led_pins[] = {
592         {
593                 .name                   = "platform:grled",
594                 .gpio                   = EP93XX_GPIO_LINE_GRLED,
595         }, {
596                 .name                   = "platform:rdled",
597                 .gpio                   = EP93XX_GPIO_LINE_RDLED,
598         },
599 };
600 
601 static struct gpio_led_platform_data ep93xx_led_data = {
602         .num_leds       = ARRAY_SIZE(ep93xx_led_pins),
603         .leds           = ep93xx_led_pins,
604 };
605 
606 static struct platform_device ep93xx_leds = {
607         .name           = "leds-gpio",
608         .id             = -1,
609         .dev            = {
610                 .platform_data  = &ep93xx_led_data,
611         },
612 };
613 
614 
615 /*************************************************************************
616  * EP93xx pwm peripheral handling
617  *************************************************************************/
618 static struct resource ep93xx_pwm0_resource[] = {
619         {
620                 .start  = EP93XX_PWM_PHYS_BASE,
621                 .end    = EP93XX_PWM_PHYS_BASE + 0x10 - 1,
622                 .flags  = IORESOURCE_MEM,
623         },
624 };
625 
626 static struct platform_device ep93xx_pwm0_device = {
627         .name           = "ep93xx-pwm",
628         .id             = 0,
629         .num_resources  = ARRAY_SIZE(ep93xx_pwm0_resource),
630         .resource       = ep93xx_pwm0_resource,
631 };
632 
633 static struct resource ep93xx_pwm1_resource[] = {
634         {
635                 .start  = EP93XX_PWM_PHYS_BASE + 0x20,
636                 .end    = EP93XX_PWM_PHYS_BASE + 0x30 - 1,
637                 .flags  = IORESOURCE_MEM,
638         },
639 };
640 
641 static struct platform_device ep93xx_pwm1_device = {
642         .name           = "ep93xx-pwm",
643         .id             = 1,
644         .num_resources  = ARRAY_SIZE(ep93xx_pwm1_resource),
645         .resource       = ep93xx_pwm1_resource,
646 };
647 
648 void __init ep93xx_register_pwm(int pwm0, int pwm1)
649 {
650         if (pwm0)
651                 platform_device_register(&ep93xx_pwm0_device);
652 
653         /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
654         if (pwm1)
655                 platform_device_register(&ep93xx_pwm1_device);
656 }
657 
658 int ep93xx_pwm_acquire_gpio(struct platform_device *pdev)
659 {
660         int err;
661 
662         if (pdev->id == 0) {
663                 err = 0;
664         } else if (pdev->id == 1) {
665                 err = gpio_request(EP93XX_GPIO_LINE_EGPIO14,
666                                    dev_name(&pdev->dev));
667                 if (err)
668                         return err;
669                 err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0);
670                 if (err)
671                         goto fail;
672 
673                 /* PWM 1 output on EGPIO[14] */
674                 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG);
675         } else {
676                 err = -ENODEV;
677         }
678 
679         return err;
680 
681 fail:
682         gpio_free(EP93XX_GPIO_LINE_EGPIO14);
683         return err;
684 }
685 EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio);
686 
687 void ep93xx_pwm_release_gpio(struct platform_device *pdev)
688 {
689         if (pdev->id == 1) {
690                 gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14);
691                 gpio_free(EP93XX_GPIO_LINE_EGPIO14);
692 
693                 /* EGPIO[14] used for GPIO */
694                 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG);
695         }
696 }
697 EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
698 
699 
700 /*************************************************************************
701  * EP93xx video peripheral handling
702  *************************************************************************/
703 static struct ep93xxfb_mach_info ep93xxfb_data;
704 
705 static struct resource ep93xx_fb_resource[] = {
706         {
707                 .start          = EP93XX_RASTER_PHYS_BASE,
708                 .end            = EP93XX_RASTER_PHYS_BASE + 0x800 - 1,
709                 .flags          = IORESOURCE_MEM,
710         },
711 };
712 
713 static struct platform_device ep93xx_fb_device = {
714         .name                   = "ep93xx-fb",
715         .id                     = -1,
716         .dev                    = {
717                 .platform_data  = &ep93xxfb_data,
718                 .coherent_dma_mask      = DMA_BIT_MASK(32),
719                 .dma_mask               = &ep93xx_fb_device.dev.coherent_dma_mask,
720         },
721         .num_resources          = ARRAY_SIZE(ep93xx_fb_resource),
722         .resource               = ep93xx_fb_resource,
723 };
724 
725 void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
726 {
727         ep93xxfb_data = *data;
728         platform_device_register(&ep93xx_fb_device);
729 }
730 
731 extern void ep93xx_gpio_init(void);
732 
733 void __init ep93xx_init_devices(void)
734 {
735         /* Disallow access to MaverickCrunch initially */
736         ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
737 
738         ep93xx_gpio_init();
739 
740         amba_device_register(&uart1_device, &iomem_resource);
741         amba_device_register(&uart2_device, &iomem_resource);
742         amba_device_register(&uart3_device, &iomem_resource);
743 
744         platform_device_register(&ep93xx_rtc_device);
745         platform_device_register(&ep93xx_ohci_device);
746         platform_device_register(&ep93xx_leds);
747 }
748 

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