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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-exynos/clock-exynos4.c

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  1 /*
  2  * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  3  *              http://www.samsung.com
  4  *
  5  * EXYNOS4 - Clock support
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License version 2 as
  9  * published by the Free Software Foundation.
 10 */
 11 
 12 #include <linux/kernel.h>
 13 #include <linux/err.h>
 14 #include <linux/io.h>
 15 #include <linux/syscore_ops.h>
 16 
 17 #include <plat/cpu-freq.h>
 18 #include <plat/clock.h>
 19 #include <plat/cpu.h>
 20 #include <plat/pll.h>
 21 #include <plat/s5p-clock.h>
 22 #include <plat/clock-clksrc.h>
 23 #include <plat/pm.h>
 24 
 25 #include <mach/map.h>
 26 #include <mach/regs-clock.h>
 27 #include <mach/sysmmu.h>
 28 
 29 #include "common.h"
 30 #include "clock-exynos4.h"
 31 
 32 #ifdef CONFIG_PM_SLEEP
 33 static struct sleep_save exynos4_clock_save[] = {
 34         SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
 35         SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
 36         SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
 37         SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
 38         SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
 39         SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
 40         SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
 41         SAVE_ITEM(EXYNOS4_CLKSRC_TV),
 42         SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
 43         SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
 44         SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
 45         SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
 46         SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
 47         SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
 48         SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
 49         SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
 50         SAVE_ITEM(EXYNOS4_CLKDIV_TV),
 51         SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
 52         SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
 53         SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
 54         SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
 55         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
 56         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
 57         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
 58         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
 59         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
 60         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
 61         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
 62         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
 63         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
 64         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
 65         SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
 66         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
 67         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
 68         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
 69         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
 70         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
 71         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
 72         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
 73         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
 74         SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
 75         SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
 76         SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
 77         SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
 78         SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
 79         SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
 80         SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
 81         SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
 82         SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
 83         SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
 84         SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
 85         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
 86         SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
 87         SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
 88         SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
 89         SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
 90         SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
 91         SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
 92         SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
 93         SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
 94         SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
 95 };
 96 #endif
 97 
 98 static struct clk exynos4_clk_sclk_hdmi27m = {
 99         .name           = "sclk_hdmi27m",
100         .rate           = 27000000,
101 };
102 
103 static struct clk exynos4_clk_sclk_hdmiphy = {
104         .name           = "sclk_hdmiphy",
105 };
106 
107 static struct clk exynos4_clk_sclk_usbphy0 = {
108         .name           = "sclk_usbphy0",
109         .rate           = 27000000,
110 };
111 
112 static struct clk exynos4_clk_sclk_usbphy1 = {
113         .name           = "sclk_usbphy1",
114 };
115 
116 static struct clk dummy_apb_pclk = {
117         .name           = "apb_pclk",
118         .id             = -1,
119 };
120 
121 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
122 {
123         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
124 }
125 
126 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
127 {
128         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
129 }
130 
131 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
132 {
133         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
134 }
135 
136 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
137 {
138         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
139 }
140 
141 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
142 {
143         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
144 }
145 
146 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
147 {
148         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
149 }
150 
151 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
152 {
153         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
154 }
155 
156 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
157 {
158         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
159 }
160 
161 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
162 {
163         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
164 }
165 
166 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
167 {
168         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
169 }
170 
171 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
172 {
173         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
174 }
175 
176 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
177 {
178         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
179 }
180 
181 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
182 {
183         return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
184 }
185 
186 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
187 {
188         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
189 }
190 
191 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
192 {
193         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
194 }
195 
196 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
197 {
198         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
199 }
200 
201 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
202 {
203         return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
204 }
205 
206 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
207 {
208         return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
209 }
210 
211 /* Core list of CMU_CPU side */
212 
213 static struct clksrc_clk exynos4_clk_mout_apll = {
214         .clk    = {
215                 .name           = "mout_apll",
216         },
217         .sources = &clk_src_apll,
218         .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
219 };
220 
221 static struct clksrc_clk exynos4_clk_sclk_apll = {
222         .clk    = {
223                 .name           = "sclk_apll",
224                 .parent         = &exynos4_clk_mout_apll.clk,
225         },
226         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
227 };
228 
229 static struct clksrc_clk exynos4_clk_mout_epll = {
230         .clk    = {
231                 .name           = "mout_epll",
232         },
233         .sources = &clk_src_epll,
234         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
235 };
236 
237 struct clksrc_clk exynos4_clk_mout_mpll = {
238         .clk    = {
239                 .name           = "mout_mpll",
240         },
241         .sources = &clk_src_mpll,
242 
243         /* reg_src will be added in each SoCs' clock */
244 };
245 
246 static struct clk *exynos4_clkset_moutcore_list[] = {
247         [0] = &exynos4_clk_mout_apll.clk,
248         [1] = &exynos4_clk_mout_mpll.clk,
249 };
250 
251 static struct clksrc_sources exynos4_clkset_moutcore = {
252         .sources        = exynos4_clkset_moutcore_list,
253         .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
254 };
255 
256 static struct clksrc_clk exynos4_clk_moutcore = {
257         .clk    = {
258                 .name           = "moutcore",
259         },
260         .sources = &exynos4_clkset_moutcore,
261         .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
262 };
263 
264 static struct clksrc_clk exynos4_clk_coreclk = {
265         .clk    = {
266                 .name           = "core_clk",
267                 .parent         = &exynos4_clk_moutcore.clk,
268         },
269         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
270 };
271 
272 static struct clksrc_clk exynos4_clk_armclk = {
273         .clk    = {
274                 .name           = "armclk",
275                 .parent         = &exynos4_clk_coreclk.clk,
276         },
277 };
278 
279 static struct clksrc_clk exynos4_clk_aclk_corem0 = {
280         .clk    = {
281                 .name           = "aclk_corem0",
282                 .parent         = &exynos4_clk_coreclk.clk,
283         },
284         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
285 };
286 
287 static struct clksrc_clk exynos4_clk_aclk_cores = {
288         .clk    = {
289                 .name           = "aclk_cores",
290                 .parent         = &exynos4_clk_coreclk.clk,
291         },
292         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
293 };
294 
295 static struct clksrc_clk exynos4_clk_aclk_corem1 = {
296         .clk    = {
297                 .name           = "aclk_corem1",
298                 .parent         = &exynos4_clk_coreclk.clk,
299         },
300         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
301 };
302 
303 static struct clksrc_clk exynos4_clk_periphclk = {
304         .clk    = {
305                 .name           = "periphclk",
306                 .parent         = &exynos4_clk_coreclk.clk,
307         },
308         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
309 };
310 
311 /* Core list of CMU_CORE side */
312 
313 static struct clk *exynos4_clkset_corebus_list[] = {
314         [0] = &exynos4_clk_mout_mpll.clk,
315         [1] = &exynos4_clk_sclk_apll.clk,
316 };
317 
318 struct clksrc_sources exynos4_clkset_mout_corebus = {
319         .sources        = exynos4_clkset_corebus_list,
320         .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
321 };
322 
323 static struct clksrc_clk exynos4_clk_mout_corebus = {
324         .clk    = {
325                 .name           = "mout_corebus",
326         },
327         .sources = &exynos4_clkset_mout_corebus,
328         .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
329 };
330 
331 static struct clksrc_clk exynos4_clk_sclk_dmc = {
332         .clk    = {
333                 .name           = "sclk_dmc",
334                 .parent         = &exynos4_clk_mout_corebus.clk,
335         },
336         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
337 };
338 
339 static struct clksrc_clk exynos4_clk_aclk_cored = {
340         .clk    = {
341                 .name           = "aclk_cored",
342                 .parent         = &exynos4_clk_sclk_dmc.clk,
343         },
344         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
345 };
346 
347 static struct clksrc_clk exynos4_clk_aclk_corep = {
348         .clk    = {
349                 .name           = "aclk_corep",
350                 .parent         = &exynos4_clk_aclk_cored.clk,
351         },
352         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
353 };
354 
355 static struct clksrc_clk exynos4_clk_aclk_acp = {
356         .clk    = {
357                 .name           = "aclk_acp",
358                 .parent         = &exynos4_clk_mout_corebus.clk,
359         },
360         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
361 };
362 
363 static struct clksrc_clk exynos4_clk_pclk_acp = {
364         .clk    = {
365                 .name           = "pclk_acp",
366                 .parent         = &exynos4_clk_aclk_acp.clk,
367         },
368         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
369 };
370 
371 /* Core list of CMU_TOP side */
372 
373 struct clk *exynos4_clkset_aclk_top_list[] = {
374         [0] = &exynos4_clk_mout_mpll.clk,
375         [1] = &exynos4_clk_sclk_apll.clk,
376 };
377 
378 static struct clksrc_sources exynos4_clkset_aclk = {
379         .sources        = exynos4_clkset_aclk_top_list,
380         .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
381 };
382 
383 static struct clksrc_clk exynos4_clk_aclk_200 = {
384         .clk    = {
385                 .name           = "aclk_200",
386         },
387         .sources = &exynos4_clkset_aclk,
388         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
389         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
390 };
391 
392 static struct clksrc_clk exynos4_clk_aclk_100 = {
393         .clk    = {
394                 .name           = "aclk_100",
395         },
396         .sources = &exynos4_clkset_aclk,
397         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
398         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
399 };
400 
401 static struct clksrc_clk exynos4_clk_aclk_160 = {
402         .clk    = {
403                 .name           = "aclk_160",
404         },
405         .sources = &exynos4_clkset_aclk,
406         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
407         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
408 };
409 
410 struct clksrc_clk exynos4_clk_aclk_133 = {
411         .clk    = {
412                 .name           = "aclk_133",
413         },
414         .sources = &exynos4_clkset_aclk,
415         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
416         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
417 };
418 
419 static struct clk *exynos4_clkset_vpllsrc_list[] = {
420         [0] = &clk_fin_vpll,
421         [1] = &exynos4_clk_sclk_hdmi27m,
422 };
423 
424 static struct clksrc_sources exynos4_clkset_vpllsrc = {
425         .sources        = exynos4_clkset_vpllsrc_list,
426         .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
427 };
428 
429 static struct clksrc_clk exynos4_clk_vpllsrc = {
430         .clk    = {
431                 .name           = "vpll_src",
432                 .enable         = exynos4_clksrc_mask_top_ctrl,
433                 .ctrlbit        = (1 << 0),
434         },
435         .sources = &exynos4_clkset_vpllsrc,
436         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
437 };
438 
439 static struct clk *exynos4_clkset_sclk_vpll_list[] = {
440         [0] = &exynos4_clk_vpllsrc.clk,
441         [1] = &clk_fout_vpll,
442 };
443 
444 static struct clksrc_sources exynos4_clkset_sclk_vpll = {
445         .sources        = exynos4_clkset_sclk_vpll_list,
446         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
447 };
448 
449 static struct clksrc_clk exynos4_clk_sclk_vpll = {
450         .clk    = {
451                 .name           = "sclk_vpll",
452         },
453         .sources = &exynos4_clkset_sclk_vpll,
454         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
455 };
456 
457 static struct clk exynos4_init_clocks_off[] = {
458         {
459                 .name           = "timers",
460                 .parent         = &exynos4_clk_aclk_100.clk,
461                 .enable         = exynos4_clk_ip_peril_ctrl,
462                 .ctrlbit        = (1<<24),
463         }, {
464                 .name           = "csis",
465                 .devname        = "s5p-mipi-csis.0",
466                 .enable         = exynos4_clk_ip_cam_ctrl,
467                 .ctrlbit        = (1 << 4),
468         }, {
469                 .name           = "csis",
470                 .devname        = "s5p-mipi-csis.1",
471                 .enable         = exynos4_clk_ip_cam_ctrl,
472                 .ctrlbit        = (1 << 5),
473         }, {
474                 .name           = "jpeg",
475                 .id             = 0,
476                 .enable         = exynos4_clk_ip_cam_ctrl,
477                 .ctrlbit        = (1 << 6),
478         }, {
479                 .name           = "fimc",
480                 .devname        = "exynos4-fimc.0",
481                 .enable         = exynos4_clk_ip_cam_ctrl,
482                 .ctrlbit        = (1 << 0),
483         }, {
484                 .name           = "fimc",
485                 .devname        = "exynos4-fimc.1",
486                 .enable         = exynos4_clk_ip_cam_ctrl,
487                 .ctrlbit        = (1 << 1),
488         }, {
489                 .name           = "fimc",
490                 .devname        = "exynos4-fimc.2",
491                 .enable         = exynos4_clk_ip_cam_ctrl,
492                 .ctrlbit        = (1 << 2),
493         }, {
494                 .name           = "fimc",
495                 .devname        = "exynos4-fimc.3",
496                 .enable         = exynos4_clk_ip_cam_ctrl,
497                 .ctrlbit        = (1 << 3),
498         }, {
499                 .name           = "hsmmc",
500                 .devname        = "exynos4-sdhci.0",
501                 .parent         = &exynos4_clk_aclk_133.clk,
502                 .enable         = exynos4_clk_ip_fsys_ctrl,
503                 .ctrlbit        = (1 << 5),
504         }, {
505                 .name           = "hsmmc",
506                 .devname        = "exynos4-sdhci.1",
507                 .parent         = &exynos4_clk_aclk_133.clk,
508                 .enable         = exynos4_clk_ip_fsys_ctrl,
509                 .ctrlbit        = (1 << 6),
510         }, {
511                 .name           = "hsmmc",
512                 .devname        = "exynos4-sdhci.2",
513                 .parent         = &exynos4_clk_aclk_133.clk,
514                 .enable         = exynos4_clk_ip_fsys_ctrl,
515                 .ctrlbit        = (1 << 7),
516         }, {
517                 .name           = "hsmmc",
518                 .devname        = "exynos4-sdhci.3",
519                 .parent         = &exynos4_clk_aclk_133.clk,
520                 .enable         = exynos4_clk_ip_fsys_ctrl,
521                 .ctrlbit        = (1 << 8),
522         }, {
523                 .name           = "dwmmc",
524                 .parent         = &exynos4_clk_aclk_133.clk,
525                 .enable         = exynos4_clk_ip_fsys_ctrl,
526                 .ctrlbit        = (1 << 9),
527         }, {
528                 .name           = "dac",
529                 .devname        = "s5p-sdo",
530                 .enable         = exynos4_clk_ip_tv_ctrl,
531                 .ctrlbit        = (1 << 2),
532         }, {
533                 .name           = "mixer",
534                 .devname        = "s5p-mixer",
535                 .enable         = exynos4_clk_ip_tv_ctrl,
536                 .ctrlbit        = (1 << 1),
537         }, {
538                 .name           = "vp",
539                 .devname        = "s5p-mixer",
540                 .enable         = exynos4_clk_ip_tv_ctrl,
541                 .ctrlbit        = (1 << 0),
542         }, {
543                 .name           = "hdmi",
544                 .devname        = "exynos4-hdmi",
545                 .enable         = exynos4_clk_ip_tv_ctrl,
546                 .ctrlbit        = (1 << 3),
547         }, {
548                 .name           = "hdmiphy",
549                 .devname        = "exynos4-hdmi",
550                 .enable         = exynos4_clk_hdmiphy_ctrl,
551                 .ctrlbit        = (1 << 0),
552         }, {
553                 .name           = "dacphy",
554                 .devname        = "s5p-sdo",
555                 .enable         = exynos4_clk_dac_ctrl,
556                 .ctrlbit        = (1 << 0),
557         }, {
558                 .name           = "adc",
559                 .enable         = exynos4_clk_ip_peril_ctrl,
560                 .ctrlbit        = (1 << 15),
561         }, {
562                 .name           = "keypad",
563                 .enable         = exynos4_clk_ip_perir_ctrl,
564                 .ctrlbit        = (1 << 16),
565         }, {
566                 .name           = "rtc",
567                 .enable         = exynos4_clk_ip_perir_ctrl,
568                 .ctrlbit        = (1 << 15),
569         }, {
570                 .name           = "watchdog",
571                 .parent         = &exynos4_clk_aclk_100.clk,
572                 .enable         = exynos4_clk_ip_perir_ctrl,
573                 .ctrlbit        = (1 << 14),
574         }, {
575                 .name           = "usbhost",
576                 .enable         = exynos4_clk_ip_fsys_ctrl ,
577                 .ctrlbit        = (1 << 12),
578         }, {
579                 .name           = "otg",
580                 .enable         = exynos4_clk_ip_fsys_ctrl,
581                 .ctrlbit        = (1 << 13),
582         }, {
583                 .name           = "spi",
584                 .devname        = "s3c64xx-spi.0",
585                 .enable         = exynos4_clk_ip_peril_ctrl,
586                 .ctrlbit        = (1 << 16),
587         }, {
588                 .name           = "spi",
589                 .devname        = "s3c64xx-spi.1",
590                 .enable         = exynos4_clk_ip_peril_ctrl,
591                 .ctrlbit        = (1 << 17),
592         }, {
593                 .name           = "spi",
594                 .devname        = "s3c64xx-spi.2",
595                 .enable         = exynos4_clk_ip_peril_ctrl,
596                 .ctrlbit        = (1 << 18),
597         }, {
598                 .name           = "iis",
599                 .devname        = "samsung-i2s.0",
600                 .enable         = exynos4_clk_ip_peril_ctrl,
601                 .ctrlbit        = (1 << 19),
602         }, {
603                 .name           = "iis",
604                 .devname        = "samsung-i2s.1",
605                 .enable         = exynos4_clk_ip_peril_ctrl,
606                 .ctrlbit        = (1 << 20),
607         }, {
608                 .name           = "iis",
609                 .devname        = "samsung-i2s.2",
610                 .enable         = exynos4_clk_ip_peril_ctrl,
611                 .ctrlbit        = (1 << 21),
612         }, {
613                 .name           = "ac97",
614                 .devname        = "samsung-ac97",
615                 .enable         = exynos4_clk_ip_peril_ctrl,
616                 .ctrlbit        = (1 << 27),
617         }, {
618                 .name           = "fimg2d",
619                 .enable         = exynos4_clk_ip_image_ctrl,
620                 .ctrlbit        = (1 << 0),
621         }, {
622                 .name           = "mfc",
623                 .devname        = "s5p-mfc",
624                 .enable         = exynos4_clk_ip_mfc_ctrl,
625                 .ctrlbit        = (1 << 0),
626         }, {
627                 .name           = "i2c",
628                 .devname        = "s3c2440-i2c.0",
629                 .parent         = &exynos4_clk_aclk_100.clk,
630                 .enable         = exynos4_clk_ip_peril_ctrl,
631                 .ctrlbit        = (1 << 6),
632         }, {
633                 .name           = "i2c",
634                 .devname        = "s3c2440-i2c.1",
635                 .parent         = &exynos4_clk_aclk_100.clk,
636                 .enable         = exynos4_clk_ip_peril_ctrl,
637                 .ctrlbit        = (1 << 7),
638         }, {
639                 .name           = "i2c",
640                 .devname        = "s3c2440-i2c.2",
641                 .parent         = &exynos4_clk_aclk_100.clk,
642                 .enable         = exynos4_clk_ip_peril_ctrl,
643                 .ctrlbit        = (1 << 8),
644         }, {
645                 .name           = "i2c",
646                 .devname        = "s3c2440-i2c.3",
647                 .parent         = &exynos4_clk_aclk_100.clk,
648                 .enable         = exynos4_clk_ip_peril_ctrl,
649                 .ctrlbit        = (1 << 9),
650         }, {
651                 .name           = "i2c",
652                 .devname        = "s3c2440-i2c.4",
653                 .parent         = &exynos4_clk_aclk_100.clk,
654                 .enable         = exynos4_clk_ip_peril_ctrl,
655                 .ctrlbit        = (1 << 10),
656         }, {
657                 .name           = "i2c",
658                 .devname        = "s3c2440-i2c.5",
659                 .parent         = &exynos4_clk_aclk_100.clk,
660                 .enable         = exynos4_clk_ip_peril_ctrl,
661                 .ctrlbit        = (1 << 11),
662         }, {
663                 .name           = "i2c",
664                 .devname        = "s3c2440-i2c.6",
665                 .parent         = &exynos4_clk_aclk_100.clk,
666                 .enable         = exynos4_clk_ip_peril_ctrl,
667                 .ctrlbit        = (1 << 12),
668         }, {
669                 .name           = "i2c",
670                 .devname        = "s3c2440-i2c.7",
671                 .parent         = &exynos4_clk_aclk_100.clk,
672                 .enable         = exynos4_clk_ip_peril_ctrl,
673                 .ctrlbit        = (1 << 13),
674         }, {
675                 .name           = "i2c",
676                 .devname        = "s3c2440-hdmiphy-i2c",
677                 .parent         = &exynos4_clk_aclk_100.clk,
678                 .enable         = exynos4_clk_ip_peril_ctrl,
679                 .ctrlbit        = (1 << 14),
680         }, {
681                 .name           = "SYSMMU_MDMA",
682                 .enable         = exynos4_clk_ip_image_ctrl,
683                 .ctrlbit        = (1 << 5),
684         }, {
685                 .name           = "SYSMMU_FIMC0",
686                 .enable         = exynos4_clk_ip_cam_ctrl,
687                 .ctrlbit        = (1 << 7),
688         }, {
689                 .name           = "SYSMMU_FIMC1",
690                 .enable         = exynos4_clk_ip_cam_ctrl,
691                 .ctrlbit        = (1 << 8),
692         }, {
693                 .name           = "SYSMMU_FIMC2",
694                 .enable         = exynos4_clk_ip_cam_ctrl,
695                 .ctrlbit        = (1 << 9),
696         }, {
697                 .name           = "SYSMMU_FIMC3",
698                 .enable         = exynos4_clk_ip_cam_ctrl,
699                 .ctrlbit        = (1 << 10),
700         }, {
701                 .name           = "SYSMMU_JPEG",
702                 .enable         = exynos4_clk_ip_cam_ctrl,
703                 .ctrlbit        = (1 << 11),
704         }, {
705                 .name           = "SYSMMU_FIMD0",
706                 .enable         = exynos4_clk_ip_lcd0_ctrl,
707                 .ctrlbit        = (1 << 4),
708         }, {
709                 .name           = "SYSMMU_FIMD1",
710                 .enable         = exynos4_clk_ip_lcd1_ctrl,
711                 .ctrlbit        = (1 << 4),
712         }, {
713                 .name           = "SYSMMU_PCIe",
714                 .enable         = exynos4_clk_ip_fsys_ctrl,
715                 .ctrlbit        = (1 << 18),
716         }, {
717                 .name           = "SYSMMU_G2D",
718                 .enable         = exynos4_clk_ip_image_ctrl,
719                 .ctrlbit        = (1 << 3),
720         }, {
721                 .name           = "SYSMMU_ROTATOR",
722                 .enable         = exynos4_clk_ip_image_ctrl,
723                 .ctrlbit        = (1 << 4),
724         }, {
725                 .name           = "SYSMMU_TV",
726                 .enable         = exynos4_clk_ip_tv_ctrl,
727                 .ctrlbit        = (1 << 4),
728         }, {
729                 .name           = "SYSMMU_MFC_L",
730                 .enable         = exynos4_clk_ip_mfc_ctrl,
731                 .ctrlbit        = (1 << 1),
732         }, {
733                 .name           = "SYSMMU_MFC_R",
734                 .enable         = exynos4_clk_ip_mfc_ctrl,
735                 .ctrlbit        = (1 << 2),
736         }
737 };
738 
739 static struct clk exynos4_init_clocks_on[] = {
740         {
741                 .name           = "uart",
742                 .devname        = "s5pv210-uart.0",
743                 .enable         = exynos4_clk_ip_peril_ctrl,
744                 .ctrlbit        = (1 << 0),
745         }, {
746                 .name           = "uart",
747                 .devname        = "s5pv210-uart.1",
748                 .enable         = exynos4_clk_ip_peril_ctrl,
749                 .ctrlbit        = (1 << 1),
750         }, {
751                 .name           = "uart",
752                 .devname        = "s5pv210-uart.2",
753                 .enable         = exynos4_clk_ip_peril_ctrl,
754                 .ctrlbit        = (1 << 2),
755         }, {
756                 .name           = "uart",
757                 .devname        = "s5pv210-uart.3",
758                 .enable         = exynos4_clk_ip_peril_ctrl,
759                 .ctrlbit        = (1 << 3),
760         }, {
761                 .name           = "uart",
762                 .devname        = "s5pv210-uart.4",
763                 .enable         = exynos4_clk_ip_peril_ctrl,
764                 .ctrlbit        = (1 << 4),
765         }, {
766                 .name           = "uart",
767                 .devname        = "s5pv210-uart.5",
768                 .enable         = exynos4_clk_ip_peril_ctrl,
769                 .ctrlbit        = (1 << 5),
770         }
771 };
772 
773 static struct clk exynos4_clk_pdma0 = {
774         .name           = "dma",
775         .devname        = "dma-pl330.0",
776         .enable         = exynos4_clk_ip_fsys_ctrl,
777         .ctrlbit        = (1 << 0),
778 };
779 
780 static struct clk exynos4_clk_pdma1 = {
781         .name           = "dma",
782         .devname        = "dma-pl330.1",
783         .enable         = exynos4_clk_ip_fsys_ctrl,
784         .ctrlbit        = (1 << 1),
785 };
786 
787 static struct clk exynos4_clk_mdma1 = {
788         .name           = "dma",
789         .devname        = "dma-pl330.2",
790         .enable         = exynos4_clk_ip_image_ctrl,
791         .ctrlbit        = ((1 << 8) | (1 << 5) | (1 << 2)),
792 };
793 
794 static struct clk exynos4_clk_fimd0 = {
795         .name           = "fimd",
796         .devname        = "exynos4-fb.0",
797         .enable         = exynos4_clk_ip_lcd0_ctrl,
798         .ctrlbit        = (1 << 0),
799 };
800 
801 struct clk *exynos4_clkset_group_list[] = {
802         [0] = &clk_ext_xtal_mux,
803         [1] = &clk_xusbxti,
804         [2] = &exynos4_clk_sclk_hdmi27m,
805         [3] = &exynos4_clk_sclk_usbphy0,
806         [4] = &exynos4_clk_sclk_usbphy1,
807         [5] = &exynos4_clk_sclk_hdmiphy,
808         [6] = &exynos4_clk_mout_mpll.clk,
809         [7] = &exynos4_clk_mout_epll.clk,
810         [8] = &exynos4_clk_sclk_vpll.clk,
811 };
812 
813 struct clksrc_sources exynos4_clkset_group = {
814         .sources        = exynos4_clkset_group_list,
815         .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
816 };
817 
818 static struct clk *exynos4_clkset_mout_g2d0_list[] = {
819         [0] = &exynos4_clk_mout_mpll.clk,
820         [1] = &exynos4_clk_sclk_apll.clk,
821 };
822 
823 static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
824         .sources        = exynos4_clkset_mout_g2d0_list,
825         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
826 };
827 
828 static struct clksrc_clk exynos4_clk_mout_g2d0 = {
829         .clk    = {
830                 .name           = "mout_g2d0",
831         },
832         .sources = &exynos4_clkset_mout_g2d0,
833         .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
834 };
835 
836 static struct clk *exynos4_clkset_mout_g2d1_list[] = {
837         [0] = &exynos4_clk_mout_epll.clk,
838         [1] = &exynos4_clk_sclk_vpll.clk,
839 };
840 
841 static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
842         .sources        = exynos4_clkset_mout_g2d1_list,
843         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
844 };
845 
846 static struct clksrc_clk exynos4_clk_mout_g2d1 = {
847         .clk    = {
848                 .name           = "mout_g2d1",
849         },
850         .sources = &exynos4_clkset_mout_g2d1,
851         .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
852 };
853 
854 static struct clk *exynos4_clkset_mout_g2d_list[] = {
855         [0] = &exynos4_clk_mout_g2d0.clk,
856         [1] = &exynos4_clk_mout_g2d1.clk,
857 };
858 
859 static struct clksrc_sources exynos4_clkset_mout_g2d = {
860         .sources        = exynos4_clkset_mout_g2d_list,
861         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
862 };
863 
864 static struct clk *exynos4_clkset_mout_mfc0_list[] = {
865         [0] = &exynos4_clk_mout_mpll.clk,
866         [1] = &exynos4_clk_sclk_apll.clk,
867 };
868 
869 static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
870         .sources        = exynos4_clkset_mout_mfc0_list,
871         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
872 };
873 
874 static struct clksrc_clk exynos4_clk_mout_mfc0 = {
875         .clk    = {
876                 .name           = "mout_mfc0",
877         },
878         .sources = &exynos4_clkset_mout_mfc0,
879         .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
880 };
881 
882 static struct clk *exynos4_clkset_mout_mfc1_list[] = {
883         [0] = &exynos4_clk_mout_epll.clk,
884         [1] = &exynos4_clk_sclk_vpll.clk,
885 };
886 
887 static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
888         .sources        = exynos4_clkset_mout_mfc1_list,
889         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
890 };
891 
892 static struct clksrc_clk exynos4_clk_mout_mfc1 = {
893         .clk    = {
894                 .name           = "mout_mfc1",
895         },
896         .sources = &exynos4_clkset_mout_mfc1,
897         .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
898 };
899 
900 static struct clk *exynos4_clkset_mout_mfc_list[] = {
901         [0] = &exynos4_clk_mout_mfc0.clk,
902         [1] = &exynos4_clk_mout_mfc1.clk,
903 };
904 
905 static struct clksrc_sources exynos4_clkset_mout_mfc = {
906         .sources        = exynos4_clkset_mout_mfc_list,
907         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
908 };
909 
910 static struct clk *exynos4_clkset_sclk_dac_list[] = {
911         [0] = &exynos4_clk_sclk_vpll.clk,
912         [1] = &exynos4_clk_sclk_hdmiphy,
913 };
914 
915 static struct clksrc_sources exynos4_clkset_sclk_dac = {
916         .sources        = exynos4_clkset_sclk_dac_list,
917         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
918 };
919 
920 static struct clksrc_clk exynos4_clk_sclk_dac = {
921         .clk            = {
922                 .name           = "sclk_dac",
923                 .enable         = exynos4_clksrc_mask_tv_ctrl,
924                 .ctrlbit        = (1 << 8),
925         },
926         .sources = &exynos4_clkset_sclk_dac,
927         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
928 };
929 
930 static struct clksrc_clk exynos4_clk_sclk_pixel = {
931         .clk            = {
932                 .name           = "sclk_pixel",
933                 .parent         = &exynos4_clk_sclk_vpll.clk,
934         },
935         .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
936 };
937 
938 static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
939         [0] = &exynos4_clk_sclk_pixel.clk,
940         [1] = &exynos4_clk_sclk_hdmiphy,
941 };
942 
943 static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
944         .sources        = exynos4_clkset_sclk_hdmi_list,
945         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
946 };
947 
948 static struct clksrc_clk exynos4_clk_sclk_hdmi = {
949         .clk            = {
950                 .name           = "sclk_hdmi",
951                 .enable         = exynos4_clksrc_mask_tv_ctrl,
952                 .ctrlbit        = (1 << 0),
953         },
954         .sources = &exynos4_clkset_sclk_hdmi,
955         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
956 };
957 
958 static struct clk *exynos4_clkset_sclk_mixer_list[] = {
959         [0] = &exynos4_clk_sclk_dac.clk,
960         [1] = &exynos4_clk_sclk_hdmi.clk,
961 };
962 
963 static struct clksrc_sources exynos4_clkset_sclk_mixer = {
964         .sources        = exynos4_clkset_sclk_mixer_list,
965         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
966 };
967 
968 static struct clksrc_clk exynos4_clk_sclk_mixer = {
969         .clk    = {
970                 .name           = "sclk_mixer",
971                 .enable         = exynos4_clksrc_mask_tv_ctrl,
972                 .ctrlbit        = (1 << 4),
973         },
974         .sources = &exynos4_clkset_sclk_mixer,
975         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
976 };
977 
978 static struct clksrc_clk *exynos4_sclk_tv[] = {
979         &exynos4_clk_sclk_dac,
980         &exynos4_clk_sclk_pixel,
981         &exynos4_clk_sclk_hdmi,
982         &exynos4_clk_sclk_mixer,
983 };
984 
985 static struct clksrc_clk exynos4_clk_dout_mmc0 = {
986         .clk    = {
987                 .name           = "dout_mmc0",
988         },
989         .sources = &exynos4_clkset_group,
990         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
991         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
992 };
993 
994 static struct clksrc_clk exynos4_clk_dout_mmc1 = {
995         .clk    = {
996                 .name           = "dout_mmc1",
997         },
998         .sources = &exynos4_clkset_group,
999         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
1000         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1001 };
1002 
1003 static struct clksrc_clk exynos4_clk_dout_mmc2 = {
1004         .clk    = {
1005                 .name           = "dout_mmc2",
1006         },
1007         .sources = &exynos4_clkset_group,
1008         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
1009         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1010 };
1011 
1012 static struct clksrc_clk exynos4_clk_dout_mmc3 = {
1013         .clk    = {
1014                 .name           = "dout_mmc3",
1015         },
1016         .sources = &exynos4_clkset_group,
1017         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
1018         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1019 };
1020 
1021 static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1022         .clk            = {
1023                 .name           = "dout_mmc4",
1024         },
1025         .sources = &exynos4_clkset_group,
1026         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
1027         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1028 };
1029 
1030 static struct clksrc_clk exynos4_clksrcs[] = {
1031         {
1032                 .clk    = {
1033                         .name           = "sclk_pwm",
1034                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
1035                         .ctrlbit        = (1 << 24),
1036                 },
1037                 .sources = &exynos4_clkset_group,
1038                 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1039                 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1040         }, {
1041                 .clk    = {
1042                         .name           = "sclk_csis",
1043                         .devname        = "s5p-mipi-csis.0",
1044                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1045                         .ctrlbit        = (1 << 24),
1046                 },
1047                 .sources = &exynos4_clkset_group,
1048                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1049                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1050         }, {
1051                 .clk    = {
1052                         .name           = "sclk_csis",
1053                         .devname        = "s5p-mipi-csis.1",
1054                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1055                         .ctrlbit        = (1 << 28),
1056                 },
1057                 .sources = &exynos4_clkset_group,
1058                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1059                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1060         }, {
1061                 .clk    = {
1062                         .name           = "sclk_cam0",
1063                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1064                         .ctrlbit        = (1 << 16),
1065                 },
1066                 .sources = &exynos4_clkset_group,
1067                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1068                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1069         }, {
1070                 .clk    = {
1071                         .name           = "sclk_cam1",
1072                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1073                         .ctrlbit        = (1 << 20),
1074                 },
1075                 .sources = &exynos4_clkset_group,
1076                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1077                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1078         }, {
1079                 .clk    = {
1080                         .name           = "sclk_fimc",
1081                         .devname        = "exynos4-fimc.0",
1082                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1083                         .ctrlbit        = (1 << 0),
1084                 },
1085                 .sources = &exynos4_clkset_group,
1086                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1087                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1088         }, {
1089                 .clk    = {
1090                         .name           = "sclk_fimc",
1091                         .devname        = "exynos4-fimc.1",
1092                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1093                         .ctrlbit        = (1 << 4),
1094                 },
1095                 .sources = &exynos4_clkset_group,
1096                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1097                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1098         }, {
1099                 .clk    = {
1100                         .name           = "sclk_fimc",
1101                         .devname        = "exynos4-fimc.2",
1102                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1103                         .ctrlbit        = (1 << 8),
1104                 },
1105                 .sources = &exynos4_clkset_group,
1106                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1107                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1108         }, {
1109                 .clk    = {
1110                         .name           = "sclk_fimc",
1111                         .devname        = "exynos4-fimc.3",
1112                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1113                         .ctrlbit        = (1 << 12),
1114                 },
1115                 .sources = &exynos4_clkset_group,
1116                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1117                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1118         }, {
1119                 .clk    = {
1120                         .name           = "sclk_fimd",
1121                         .devname        = "exynos4-fb.0",
1122                         .enable         = exynos4_clksrc_mask_lcd0_ctrl,
1123                         .ctrlbit        = (1 << 0),
1124                 },
1125                 .sources = &exynos4_clkset_group,
1126                 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1127                 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1128         }, {
1129                 .clk    = {
1130                         .name           = "sclk_fimg2d",
1131                 },
1132                 .sources = &exynos4_clkset_mout_g2d,
1133                 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1134                 .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1135         }, {
1136                 .clk    = {
1137                         .name           = "sclk_mfc",
1138                         .devname        = "s5p-mfc",
1139                 },
1140                 .sources = &exynos4_clkset_mout_mfc,
1141                 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1142                 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1143         }, {
1144                 .clk    = {
1145                         .name           = "sclk_dwmmc",
1146                         .parent         = &exynos4_clk_dout_mmc4.clk,
1147                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1148                         .ctrlbit        = (1 << 16),
1149                 },
1150                 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1151         }
1152 };
1153 
1154 static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1155         .clk    = {
1156                 .name           = "uclk1",
1157                 .devname        = "exynos4210-uart.0",
1158                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1159                 .ctrlbit        = (1 << 0),
1160         },
1161         .sources = &exynos4_clkset_group,
1162         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1163         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1164 };
1165 
1166 static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1167         .clk    = {
1168                 .name           = "uclk1",
1169                 .devname        = "exynos4210-uart.1",
1170                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1171                 .ctrlbit        = (1 << 4),
1172         },
1173         .sources = &exynos4_clkset_group,
1174         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1175         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1176 };
1177 
1178 static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1179         .clk    = {
1180                 .name           = "uclk1",
1181                 .devname        = "exynos4210-uart.2",
1182                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1183                 .ctrlbit        = (1 << 8),
1184         },
1185         .sources = &exynos4_clkset_group,
1186         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1187         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1188 };
1189 
1190 static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1191         .clk    = {
1192                 .name           = "uclk1",
1193                 .devname        = "exynos4210-uart.3",
1194                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1195                 .ctrlbit        = (1 << 12),
1196         },
1197         .sources = &exynos4_clkset_group,
1198         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1199         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1200 };
1201 
1202 static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1203         .clk    = {
1204                 .name           = "sclk_mmc",
1205                 .devname        = "exynos4-sdhci.0",
1206                 .parent         = &exynos4_clk_dout_mmc0.clk,
1207                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1208                 .ctrlbit        = (1 << 0),
1209         },
1210         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1211 };
1212 
1213 static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1214         .clk    = {
1215                 .name           = "sclk_mmc",
1216                 .devname        = "exynos4-sdhci.1",
1217                 .parent         = &exynos4_clk_dout_mmc1.clk,
1218                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1219                 .ctrlbit        = (1 << 4),
1220         },
1221         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1222 };
1223 
1224 static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1225         .clk    = {
1226                 .name           = "sclk_mmc",
1227                 .devname        = "exynos4-sdhci.2",
1228                 .parent         = &exynos4_clk_dout_mmc2.clk,
1229                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1230                 .ctrlbit        = (1 << 8),
1231         },
1232         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1233 };
1234 
1235 static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1236         .clk    = {
1237                 .name           = "sclk_mmc",
1238                 .devname        = "exynos4-sdhci.3",
1239                 .parent         = &exynos4_clk_dout_mmc3.clk,
1240                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1241                 .ctrlbit        = (1 << 12),
1242         },
1243         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1244 };
1245 
1246 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1247         .clk    = {
1248                 .name           = "sclk_spi",
1249                 .devname        = "s3c64xx-spi.0",
1250                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1251                 .ctrlbit        = (1 << 16),
1252         },
1253         .sources = &exynos4_clkset_group,
1254         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1255         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1256 };
1257 
1258 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1259         .clk    = {
1260                 .name           = "sclk_spi",
1261                 .devname        = "s3c64xx-spi.1",
1262                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1263                 .ctrlbit        = (1 << 20),
1264         },
1265         .sources = &exynos4_clkset_group,
1266         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1267         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1268 };
1269 
1270 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1271         .clk    = {
1272                 .name           = "sclk_spi",
1273                 .devname        = "s3c64xx-spi.2",
1274                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1275                 .ctrlbit        = (1 << 24),
1276         },
1277         .sources = &exynos4_clkset_group,
1278         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1279         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1280 };
1281 
1282 /* Clock initialization code */
1283 static struct clksrc_clk *exynos4_sysclks[] = {
1284         &exynos4_clk_mout_apll,
1285         &exynos4_clk_sclk_apll,
1286         &exynos4_clk_mout_epll,
1287         &exynos4_clk_mout_mpll,
1288         &exynos4_clk_moutcore,
1289         &exynos4_clk_coreclk,
1290         &exynos4_clk_armclk,
1291         &exynos4_clk_aclk_corem0,
1292         &exynos4_clk_aclk_cores,
1293         &exynos4_clk_aclk_corem1,
1294         &exynos4_clk_periphclk,
1295         &exynos4_clk_mout_corebus,
1296         &exynos4_clk_sclk_dmc,
1297         &exynos4_clk_aclk_cored,
1298         &exynos4_clk_aclk_corep,
1299         &exynos4_clk_aclk_acp,
1300         &exynos4_clk_pclk_acp,
1301         &exynos4_clk_vpllsrc,
1302         &exynos4_clk_sclk_vpll,
1303         &exynos4_clk_aclk_200,
1304         &exynos4_clk_aclk_100,
1305         &exynos4_clk_aclk_160,
1306         &exynos4_clk_aclk_133,
1307         &exynos4_clk_dout_mmc0,
1308         &exynos4_clk_dout_mmc1,
1309         &exynos4_clk_dout_mmc2,
1310         &exynos4_clk_dout_mmc3,
1311         &exynos4_clk_dout_mmc4,
1312         &exynos4_clk_mout_mfc0,
1313         &exynos4_clk_mout_mfc1,
1314 };
1315 
1316 static struct clk *exynos4_clk_cdev[] = {
1317         &exynos4_clk_pdma0,
1318         &exynos4_clk_pdma1,
1319         &exynos4_clk_mdma1,
1320         &exynos4_clk_fimd0,
1321 };
1322 
1323 static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1324         &exynos4_clk_sclk_uart0,
1325         &exynos4_clk_sclk_uart1,
1326         &exynos4_clk_sclk_uart2,
1327         &exynos4_clk_sclk_uart3,
1328         &exynos4_clk_sclk_mmc0,
1329         &exynos4_clk_sclk_mmc1,
1330         &exynos4_clk_sclk_mmc2,
1331         &exynos4_clk_sclk_mmc3,
1332         &exynos4_clk_sclk_spi0,
1333         &exynos4_clk_sclk_spi1,
1334         &exynos4_clk_sclk_spi2,
1335 
1336 };
1337 
1338 static struct clk_lookup exynos4_clk_lookup[] = {
1339         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1340         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1341         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1342         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1343         CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1344         CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1345         CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1346         CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1347         CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1348         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1349         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1350         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1351         CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1352         CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1353         CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1354 };
1355 
1356 static int xtal_rate;
1357 
1358 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1359 {
1360         if (soc_is_exynos4210())
1361                 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1362                                         pll_4508);
1363         else if (soc_is_exynos4212() || soc_is_exynos4412())
1364                 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1365         else
1366                 return 0;
1367 }
1368 
1369 static struct clk_ops exynos4_fout_apll_ops = {
1370         .get_rate = exynos4_fout_apll_get_rate,
1371 };
1372 
1373 static u32 exynos4_vpll_div[][8] = {
1374         {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
1375         { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1376 };
1377 
1378 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1379 {
1380         return clk->rate;
1381 }
1382 
1383 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1384 {
1385         unsigned int vpll_con0, vpll_con1 = 0;
1386         unsigned int i;
1387 
1388         /* Return if nothing changed */
1389         if (clk->rate == rate)
1390                 return 0;
1391 
1392         vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1393         vpll_con0 &= ~(0x1 << 27 |                                      \
1394                         PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
1395                         PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
1396                         PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1397 
1398         vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1399         vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
1400                         PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1401                         PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1402 
1403         for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1404                 if (exynos4_vpll_div[i][0] == rate) {
1405                         vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1406                         vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1407                         vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1408                         vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1409                         vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1410                         vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1411                         vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1412                         break;
1413                 }
1414         }
1415 
1416         if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1417                 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1418                                 __func__);
1419                 return -EINVAL;
1420         }
1421 
1422         __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1423         __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1424 
1425         /* Wait for VPLL lock */
1426         while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1427                 continue;
1428 
1429         clk->rate = rate;
1430         return 0;
1431 }
1432 
1433 static struct clk_ops exynos4_vpll_ops = {
1434         .get_rate = exynos4_vpll_get_rate,
1435         .set_rate = exynos4_vpll_set_rate,
1436 };
1437 
1438 void __init_or_cpufreq exynos4_setup_clocks(void)
1439 {
1440         struct clk *xtal_clk;
1441         unsigned long apll = 0;
1442         unsigned long mpll = 0;
1443         unsigned long epll = 0;
1444         unsigned long vpll = 0;
1445         unsigned long vpllsrc;
1446         unsigned long xtal;
1447         unsigned long armclk;
1448         unsigned long sclk_dmc;
1449         unsigned long aclk_200;
1450         unsigned long aclk_100;
1451         unsigned long aclk_160;
1452         unsigned long aclk_133;
1453         unsigned int ptr;
1454 
1455         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1456 
1457         xtal_clk = clk_get(NULL, "xtal");
1458         BUG_ON(IS_ERR(xtal_clk));
1459 
1460         xtal = clk_get_rate(xtal_clk);
1461 
1462         xtal_rate = xtal;
1463 
1464         clk_put(xtal_clk);
1465 
1466         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1467 
1468         if (soc_is_exynos4210()) {
1469                 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1470                                         pll_4508);
1471                 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1472                                         pll_4508);
1473                 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1474                                         __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1475 
1476                 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1477                 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1478                                         __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1479         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1480                 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1481                 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1482                 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1483                                         __raw_readl(EXYNOS4_EPLL_CON1));
1484 
1485                 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1486                 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1487                                         __raw_readl(EXYNOS4_VPLL_CON1));
1488         } else {
1489                 /* nothing */
1490         }
1491 
1492         clk_fout_apll.ops = &exynos4_fout_apll_ops;
1493         clk_fout_mpll.rate = mpll;
1494         clk_fout_epll.rate = epll;
1495         clk_fout_vpll.ops = &exynos4_vpll_ops;
1496         clk_fout_vpll.rate = vpll;
1497 
1498         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1499                         apll, mpll, epll, vpll);
1500 
1501         armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1502         sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1503 
1504         aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1505         aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1506         aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1507         aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1508 
1509         printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1510                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1511                         armclk, sclk_dmc, aclk_200,
1512                         aclk_100, aclk_160, aclk_133);
1513 
1514         clk_f.rate = armclk;
1515         clk_h.rate = sclk_dmc;
1516         clk_p.rate = aclk_100;
1517 
1518         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1519                 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1520 }
1521 
1522 static struct clk *exynos4_clks[] __initdata = {
1523         &exynos4_clk_sclk_hdmi27m,
1524         &exynos4_clk_sclk_hdmiphy,
1525         &exynos4_clk_sclk_usbphy0,
1526         &exynos4_clk_sclk_usbphy1,
1527 };
1528 
1529 #ifdef CONFIG_PM_SLEEP
1530 static int exynos4_clock_suspend(void)
1531 {
1532         s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1533         return 0;
1534 }
1535 
1536 static void exynos4_clock_resume(void)
1537 {
1538         s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1539 }
1540 
1541 #else
1542 #define exynos4_clock_suspend NULL
1543 #define exynos4_clock_resume NULL
1544 #endif
1545 
1546 static struct syscore_ops exynos4_clock_syscore_ops = {
1547         .suspend        = exynos4_clock_suspend,
1548         .resume         = exynos4_clock_resume,
1549 };
1550 
1551 void __init exynos4_register_clocks(void)
1552 {
1553         int ptr;
1554 
1555         s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1556 
1557         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1558                 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1559 
1560         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1561                 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1562 
1563         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1564                 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1565 
1566         s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1567         s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1568 
1569         s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1570         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1571                 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1572 
1573         s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1574         s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1575         clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1576 
1577         register_syscore_ops(&exynos4_clock_syscore_ops);
1578         s3c24xx_register_clock(&dummy_apb_pclk);
1579 
1580         s3c_pwmclk_init();
1581 }
1582 

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