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Linux/arch/arm/mach-imx/mach-mx21ads.c

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  1 /*
  2  *  Copyright (C) 2000 Deep Blue Solutions Ltd
  3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
  4  *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; either version 2 of the License, or
  9  * (at your option) any later version.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  */
 16 
 17 #include <linux/platform_device.h>
 18 #include <linux/mtd/mtd.h>
 19 #include <linux/mtd/physmap.h>
 20 #include <linux/gpio.h>
 21 #include <asm/mach-types.h>
 22 #include <asm/mach/arch.h>
 23 #include <asm/mach/time.h>
 24 #include <asm/mach/map.h>
 25 
 26 #include "common.h"
 27 #include "devices-imx21.h"
 28 #include "hardware.h"
 29 #include "iomux-mx21.h"
 30 
 31 /*
 32  * Memory-mapped I/O on MX21ADS base board
 33  */
 34 #define MX21ADS_MMIO_BASE_ADDR   0xf5000000
 35 #define MX21ADS_MMIO_SIZE        0xc00000
 36 
 37 #define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
 38                 (MX21ADS_MMIO_BASE_ADDR + (offset))
 39 
 40 #define MX21ADS_CS8900A_MMIO_SIZE   0x200000
 41 #define MX21ADS_CS8900A_IRQ_GPIO    IMX_GPIO_NR(5, 11)
 42 #define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
 43 #define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
 44 #define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
 45 
 46 /* MX21ADS_IO_REG bit definitions */
 47 #define MX21ADS_IO_SD_WP        0x0001 /* read */
 48 #define MX21ADS_IO_TP6          0x0001 /* write */
 49 #define MX21ADS_IO_SW_SEL       0x0002 /* read */
 50 #define MX21ADS_IO_TP7          0x0002 /* write */
 51 #define MX21ADS_IO_RESET_E_UART 0x0004
 52 #define MX21ADS_IO_RESET_BASE   0x0008
 53 #define MX21ADS_IO_CSI_CTL2     0x0010
 54 #define MX21ADS_IO_CSI_CTL1     0x0020
 55 #define MX21ADS_IO_CSI_CTL0     0x0040
 56 #define MX21ADS_IO_UART1_EN     0x0080
 57 #define MX21ADS_IO_UART4_EN     0x0100
 58 #define MX21ADS_IO_LCDON        0x0200
 59 #define MX21ADS_IO_IRDA_EN      0x0400
 60 #define MX21ADS_IO_IRDA_FIR_SEL 0x0800
 61 #define MX21ADS_IO_IRDA_MD0_B   0x1000
 62 #define MX21ADS_IO_IRDA_MD1     0x2000
 63 #define MX21ADS_IO_LED4_ON      0x4000
 64 #define MX21ADS_IO_LED3_ON      0x8000
 65 
 66 static const int mx21ads_pins[] __initconst = {
 67 
 68         /* CS8900A */
 69         (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),
 70 
 71         /* UART1 */
 72         PE12_PF_UART1_TXD,
 73         PE13_PF_UART1_RXD,
 74         PE14_PF_UART1_CTS,
 75         PE15_PF_UART1_RTS,
 76 
 77         /* UART3 (IrDA) - only TXD and RXD */
 78         PE8_PF_UART3_TXD,
 79         PE9_PF_UART3_RXD,
 80 
 81         /* UART4 */
 82         PB26_AF_UART4_RTS,
 83         PB28_AF_UART4_TXD,
 84         PB29_AF_UART4_CTS,
 85         PB31_AF_UART4_RXD,
 86 
 87         /* LCDC */
 88         PA5_PF_LSCLK,
 89         PA6_PF_LD0,
 90         PA7_PF_LD1,
 91         PA8_PF_LD2,
 92         PA9_PF_LD3,
 93         PA10_PF_LD4,
 94         PA11_PF_LD5,
 95         PA12_PF_LD6,
 96         PA13_PF_LD7,
 97         PA14_PF_LD8,
 98         PA15_PF_LD9,
 99         PA16_PF_LD10,
100         PA17_PF_LD11,
101         PA18_PF_LD12,
102         PA19_PF_LD13,
103         PA20_PF_LD14,
104         PA21_PF_LD15,
105         PA22_PF_LD16,
106         PA24_PF_REV,     /* Sharp panel dedicated signal */
107         PA25_PF_CLS,     /* Sharp panel dedicated signal */
108         PA26_PF_PS,      /* Sharp panel dedicated signal */
109         PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */
110         PA28_PF_HSYNC,
111         PA29_PF_VSYNC,
112         PA30_PF_CONTRAST,
113         PA31_PF_OE_ACD,
114 
115         /* MMC/SDHC */
116         PE18_PF_SD1_D0,
117         PE19_PF_SD1_D1,
118         PE20_PF_SD1_D2,
119         PE21_PF_SD1_D3,
120         PE22_PF_SD1_CMD,
121         PE23_PF_SD1_CLK,
122 
123         /* NFC */
124         PF0_PF_NRFB,
125         PF1_PF_NFCE,
126         PF2_PF_NFWP,
127         PF3_PF_NFCLE,
128         PF4_PF_NFALE,
129         PF5_PF_NFRE,
130         PF6_PF_NFWE,
131         PF7_PF_NFIO0,
132         PF8_PF_NFIO1,
133         PF9_PF_NFIO2,
134         PF10_PF_NFIO3,
135         PF11_PF_NFIO4,
136         PF12_PF_NFIO5,
137         PF13_PF_NFIO6,
138         PF14_PF_NFIO7,
139 };
140 
141 /* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */
142 static struct physmap_flash_data mx21ads_flash_data = {
143         .width = 4,
144 };
145 
146 static struct resource mx21ads_flash_resource = {
147         .start = MX21_CS0_BASE_ADDR,
148         .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
149         .flags = IORESOURCE_MEM,
150 };
151 
152 static struct platform_device mx21ads_nor_mtd_device = {
153         .name = "physmap-flash",
154         .id = 0,
155         .dev = {
156                 .platform_data = &mx21ads_flash_data,
157         },
158         .num_resources = 1,
159         .resource = &mx21ads_flash_resource,
160 };
161 
162 static struct resource mx21ads_cs8900_resources[] __initdata = {
163         DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE),
164         /* irq number is run-time assigned */
165         DEFINE_RES_IRQ(-1),
166 };
167 
168 static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = {
169         .name = "cs89x0",
170         .id = 0,
171         .res = mx21ads_cs8900_resources,
172         .num_res = ARRAY_SIZE(mx21ads_cs8900_resources),
173 };
174 
175 static const struct imxuart_platform_data uart_pdata_rts __initconst = {
176         .flags = IMXUART_HAVE_RTSCTS,
177 };
178 
179 static const struct imxuart_platform_data uart_pdata_norts __initconst = {
180 };
181 
182 static int mx21ads_fb_init(struct platform_device *pdev)
183 {
184         u16 tmp;
185 
186         tmp = __raw_readw(MX21ADS_IO_REG);
187         tmp |= MX21ADS_IO_LCDON;
188         __raw_writew(tmp, MX21ADS_IO_REG);
189         return 0;
190 }
191 
192 static void mx21ads_fb_exit(struct platform_device *pdev)
193 {
194         u16 tmp;
195 
196         tmp = __raw_readw(MX21ADS_IO_REG);
197         tmp &= ~MX21ADS_IO_LCDON;
198         __raw_writew(tmp, MX21ADS_IO_REG);
199 }
200 
201 /*
202  * Connected is a portrait Sharp-QVGA display
203  * of type: LQ035Q7DB02
204  */
205 static struct imx_fb_videomode mx21ads_modes[] = {
206         {
207                 .mode = {
208                         .name           = "Sharp-LQ035Q7",
209                         .refresh        = 60,
210                         .xres           = 240,
211                         .yres           = 320,
212                         .pixclock       = 188679, /* in ps (5.3MHz) */
213                         .hsync_len      = 2,
214                         .left_margin    = 6,
215                         .right_margin   = 16,
216                         .vsync_len      = 1,
217                         .upper_margin   = 8,
218                         .lower_margin   = 10,
219                 },
220                 .pcr            = 0xfb108bc7,
221                 .bpp            = 16,
222         },
223 };
224 
225 static const struct imx_fb_platform_data mx21ads_fb_data __initconst = {
226         .mode = mx21ads_modes,
227         .num_modes = ARRAY_SIZE(mx21ads_modes),
228 
229         .pwmr           = 0x00a903ff,
230         .lscr1          = 0x00120300,
231         .dmacr          = 0x00020008,
232 
233         .init = mx21ads_fb_init,
234         .exit = mx21ads_fb_exit,
235 };
236 
237 static int mx21ads_sdhc_get_ro(struct device *dev)
238 {
239         return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0;
240 }
241 
242 static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
243         void *data)
244 {
245         return request_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), detect_irq,
246                 IRQF_TRIGGER_FALLING, "mmc-detect", data);
247 }
248 
249 static void mx21ads_sdhc_exit(struct device *dev, void *data)
250 {
251         free_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), data);
252 }
253 
254 static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
255         .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
256         .get_ro = mx21ads_sdhc_get_ro,
257         .init = mx21ads_sdhc_init,
258         .exit = mx21ads_sdhc_exit,
259 };
260 
261 static const struct mxc_nand_platform_data
262 mx21ads_nand_board_info __initconst = {
263         .width = 1,
264         .hw_ecc = 1,
265 };
266 
267 static struct map_desc mx21ads_io_desc[] __initdata = {
268         /*
269          * Memory-mapped I/O on MX21ADS Base board:
270          *   - CS8900A Ethernet controller
271          *   - ST16C2552CJ UART
272          *   - CPU and Base board version
273          *   - Base board I/O register
274          */
275         {
276                 .virtual = MX21ADS_MMIO_BASE_ADDR,
277                 .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
278                 .length = MX21ADS_MMIO_SIZE,
279                 .type = MT_DEVICE,
280         },
281 };
282 
283 static void __init mx21ads_map_io(void)
284 {
285         mx21_map_io();
286         iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc));
287 }
288 
289 static struct platform_device *platform_devices[] __initdata = {
290         &mx21ads_nor_mtd_device,
291 };
292 
293 static void __init mx21ads_board_init(void)
294 {
295         imx21_soc_init();
296 
297         mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
298                         "mx21ads");
299 
300         imx21_add_imx_uart0(&uart_pdata_rts);
301         imx21_add_imx_uart2(&uart_pdata_norts);
302         imx21_add_imx_uart3(&uart_pdata_rts);
303         imx21_add_imx_fb(&mx21ads_fb_data);
304         imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata);
305         imx21_add_mxc_nand(&mx21ads_nand_board_info);
306 
307         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
308 
309         mx21ads_cs8900_resources[1].start =
310                         gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
311         mx21ads_cs8900_resources[1].end =
312                         gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
313         platform_device_register_full(&mx21ads_cs8900_devinfo);
314 }
315 
316 static void __init mx21ads_timer_init(void)
317 {
318         mx21_clocks_init(32768, 26000000);
319 }
320 
321 MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
322         /* maintainer: Freescale Semiconductor, Inc. */
323         .atag_offset = 0x100,
324         .map_io = mx21ads_map_io,
325         .init_early = imx21_init_early,
326         .init_irq = mx21_init_irq,
327         .handle_irq = imx21_handle_irq,
328         .init_time      = mx21ads_timer_init,
329         .init_machine = mx21ads_board_init,
330         .restart        = mxc_restart,
331 MACHINE_END
332 

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