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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-imx/mm-imx3.c

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  1 /*
  2  *  Copyright (C) 1999,2000 Arm Limited
  3  *  Copyright (C) 2000 Deep Blue Solutions Ltd
  4  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
  5  *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  6  *    - add MX31 specific definitions
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  */
 18 
 19 #include <linux/mm.h>
 20 #include <linux/init.h>
 21 #include <linux/err.h>
 22 #include <linux/io.h>
 23 #include <linux/pinctrl/machine.h>
 24 
 25 #include <asm/pgtable.h>
 26 #include <asm/system_misc.h>
 27 #include <asm/hardware/cache-l2x0.h>
 28 #include <asm/mach/map.h>
 29 
 30 #include "common.h"
 31 #include "crmregs-imx3.h"
 32 #include "devices/devices-common.h"
 33 #include "hardware.h"
 34 #include "iomux-v3.h"
 35 
 36 void __iomem *mx3_ccm_base;
 37 
 38 static void imx3_idle(void)
 39 {
 40         unsigned long reg = 0;
 41 
 42         __asm__ __volatile__(
 43                 /* disable I and D cache */
 44                 "mrc p15, 0, %0, c1, c0, 0\n"
 45                 "bic %0, %0, #0x00001000\n"
 46                 "bic %0, %0, #0x00000004\n"
 47                 "mcr p15, 0, %0, c1, c0, 0\n"
 48                 /* invalidate I cache */
 49                 "mov %0, #0\n"
 50                 "mcr p15, 0, %0, c7, c5, 0\n"
 51                 /* clear and invalidate D cache */
 52                 "mov %0, #0\n"
 53                 "mcr p15, 0, %0, c7, c14, 0\n"
 54                 /* WFI */
 55                 "mov %0, #0\n"
 56                 "mcr p15, 0, %0, c7, c0, 4\n"
 57                 "nop\n" "nop\n" "nop\n" "nop\n"
 58                 "nop\n" "nop\n" "nop\n"
 59                 /* enable I and D cache */
 60                 "mrc p15, 0, %0, c1, c0, 0\n"
 61                 "orr %0, %0, #0x00001000\n"
 62                 "orr %0, %0, #0x00000004\n"
 63                 "mcr p15, 0, %0, c1, c0, 0\n"
 64                 : "=r" (reg));
 65 }
 66 
 67 static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
 68                                          unsigned int mtype, void *caller)
 69 {
 70         if (mtype == MT_DEVICE) {
 71                 /*
 72                  * Access all peripherals below 0x80000000 as nonshared device
 73                  * on mx3, but leave l2cc alone.  Otherwise cache corruptions
 74                  * can occur.
 75                  */
 76                 if (phys_addr < 0x80000000 &&
 77                                 !addr_in_module(phys_addr, MX3x_L2CC))
 78                         mtype = MT_DEVICE_NONSHARED;
 79         }
 80 
 81         return __arm_ioremap_caller(phys_addr, size, mtype, caller);
 82 }
 83 
 84 static void __init imx3_init_l2x0(void)
 85 {
 86 #ifdef CONFIG_CACHE_L2X0
 87         void __iomem *l2x0_base;
 88         void __iomem *clkctl_base;
 89 
 90 /*
 91  * First of all, we must repair broken chip settings. There are some
 92  * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
 93  * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
 94  * Workaraound is to setup the correct register setting prior enabling the
 95  * L2 cache. This should not hurt already working CPUs, as they are using the
 96  * same value.
 97  */
 98 #define L2_MEM_VAL 0x10
 99 
100         clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
101         if (clkctl_base != NULL) {
102                 writel(0x00000515, clkctl_base + L2_MEM_VAL);
103                 iounmap(clkctl_base);
104         } else {
105                 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
106         }
107 
108         l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
109         if (!l2x0_base) {
110                 printk(KERN_ERR "remapping L2 cache area failed\n");
111                 return;
112         }
113 
114         l2x0_init(l2x0_base, 0x00030024, 0x00000000);
115 #endif
116 }
117 
118 #ifdef CONFIG_SOC_IMX31
119 static struct map_desc mx31_io_desc[] __initdata = {
120         imx_map_entry(MX31, X_MEMC, MT_DEVICE),
121         imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
122         imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
123         imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
124         imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
125 };
126 
127 /*
128  * This function initializes the memory map. It is called during the
129  * system startup to create static physical to virtual memory mappings
130  * for the IO modules.
131  */
132 void __init mx31_map_io(void)
133 {
134         iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
135 }
136 
137 static void imx31_idle(void)
138 {
139         int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
140         reg &= ~MXC_CCM_CCMR_LPM_MASK;
141         imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
142 
143         imx3_idle();
144 }
145 
146 void __init imx31_init_early(void)
147 {
148         mxc_set_cpu_type(MXC_CPU_MX31);
149         arch_ioremap_caller = imx3_ioremap_caller;
150         arm_pm_idle = imx31_idle;
151         mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
152 }
153 
154 void __init mx31_init_irq(void)
155 {
156         mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
157 }
158 
159 static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
160         .per_2_per_addr = 1677,
161 };
162 
163 static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
164         .ap_2_ap_addr = 423,
165         .ap_2_bp_addr = 829,
166         .bp_2_ap_addr = 1029,
167 };
168 
169 static struct sdma_platform_data imx31_sdma_pdata __initdata = {
170         .fw_name = "sdma-imx31-to2.bin",
171         .script_addrs = &imx31_to2_sdma_script,
172 };
173 
174 static const struct resource imx31_audmux_res[] __initconst = {
175         DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
176 };
177 
178 static const struct resource imx31_rnga_res[] __initconst = {
179         DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K),
180 };
181 
182 void __init imx31_soc_init(void)
183 {
184         int to_version = mx31_revision() >> 4;
185 
186         imx3_init_l2x0();
187 
188         mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
189         mxc_device_init();
190 
191         mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
192         mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
193         mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
194 
195         pinctrl_provide_dummies();
196 
197         if (to_version == 1) {
198                 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
199                         strlen(imx31_sdma_pdata.fw_name));
200                 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
201         }
202 
203         imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
204 
205         imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
206         imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
207 
208         platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
209                                         ARRAY_SIZE(imx31_audmux_res));
210         platform_device_register_simple("mxc_rnga", -1, imx31_rnga_res,
211                                         ARRAY_SIZE(imx31_rnga_res));
212 }
213 #endif /* ifdef CONFIG_SOC_IMX31 */
214 
215 #ifdef CONFIG_SOC_IMX35
216 static struct map_desc mx35_io_desc[] __initdata = {
217         imx_map_entry(MX35, X_MEMC, MT_DEVICE),
218         imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
219         imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
220         imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
221         imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
222 };
223 
224 void __init mx35_map_io(void)
225 {
226         iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
227 }
228 
229 static void imx35_idle(void)
230 {
231         int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
232         reg &= ~MXC_CCM_CCMR_LPM_MASK;
233         reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
234         imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
235 
236         imx3_idle();
237 }
238 
239 void __init imx35_init_early(void)
240 {
241         mxc_set_cpu_type(MXC_CPU_MX35);
242         mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
243         arm_pm_idle = imx35_idle;
244         arch_ioremap_caller = imx3_ioremap_caller;
245         mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
246 }
247 
248 void __init mx35_init_irq(void)
249 {
250         mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
251 }
252 
253 static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
254         .ap_2_ap_addr = 642,
255         .uart_2_mcu_addr = 817,
256         .mcu_2_app_addr = 747,
257         .uartsh_2_mcu_addr = 1183,
258         .per_2_shp_addr = 1033,
259         .mcu_2_shp_addr = 961,
260         .ata_2_mcu_addr = 1333,
261         .mcu_2_ata_addr = 1252,
262         .app_2_mcu_addr = 683,
263         .shp_2_per_addr = 1111,
264         .shp_2_mcu_addr = 892,
265 };
266 
267 static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
268         .ap_2_ap_addr = 729,
269         .uart_2_mcu_addr = 904,
270         .per_2_app_addr = 1597,
271         .mcu_2_app_addr = 834,
272         .uartsh_2_mcu_addr = 1270,
273         .per_2_shp_addr = 1120,
274         .mcu_2_shp_addr = 1048,
275         .ata_2_mcu_addr = 1429,
276         .mcu_2_ata_addr = 1339,
277         .app_2_per_addr = 1531,
278         .app_2_mcu_addr = 770,
279         .shp_2_per_addr = 1198,
280         .shp_2_mcu_addr = 979,
281 };
282 
283 static struct sdma_platform_data imx35_sdma_pdata __initdata = {
284         .fw_name = "sdma-imx35-to2.bin",
285         .script_addrs = &imx35_to2_sdma_script,
286 };
287 
288 static const struct resource imx35_audmux_res[] __initconst = {
289         DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
290 };
291 
292 void __init imx35_soc_init(void)
293 {
294         int to_version = mx35_revision() >> 4;
295 
296         imx3_init_l2x0();
297 
298         mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
299         mxc_device_init();
300 
301         mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
302         mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
303         mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
304 
305         pinctrl_provide_dummies();
306         if (to_version == 1) {
307                 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
308                         strlen(imx35_sdma_pdata.fw_name));
309                 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
310         }
311 
312         imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
313 
314         /* Setup AIPS registers */
315         imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
316         imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
317 
318         /* i.mx35 has the i.mx31 type audmux */
319         platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
320                                         ARRAY_SIZE(imx35_audmux_res));
321 }
322 #endif /* ifdef CONFIG_SOC_IMX35 */
323 

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