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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-imx/pm-imx6.c

Version: ~ [ linux-5.3-rc5 ] ~ [ linux-5.2.9 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.67 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.139 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.189 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.189 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.72 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * Copyright 2011-2014 Freescale Semiconductor, Inc.
  3  * Copyright 2011 Linaro Ltd.
  4  *
  5  * The code contained herein is licensed under the GNU General Public
  6  * License. You may obtain a copy of the GNU General Public License
  7  * Version 2 or later at the following locations:
  8  *
  9  * http://www.opensource.org/licenses/gpl-license.html
 10  * http://www.gnu.org/copyleft/gpl.html
 11  */
 12 
 13 #include <linux/delay.h>
 14 #include <linux/init.h>
 15 #include <linux/io.h>
 16 #include <linux/irq.h>
 17 #include <linux/genalloc.h>
 18 #include <linux/mfd/syscon.h>
 19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 20 #include <linux/of.h>
 21 #include <linux/of_address.h>
 22 #include <linux/of_platform.h>
 23 #include <linux/regmap.h>
 24 #include <linux/suspend.h>
 25 #include <asm/cacheflush.h>
 26 #include <asm/fncpy.h>
 27 #include <asm/proc-fns.h>
 28 #include <asm/suspend.h>
 29 #include <asm/tlb.h>
 30 
 31 #include "common.h"
 32 #include "hardware.h"
 33 
 34 #define CCR                             0x0
 35 #define BM_CCR_WB_COUNT                 (0x7 << 16)
 36 #define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
 37 #define BM_CCR_RBC_EN                   (0x1 << 27)
 38 
 39 #define CLPCR                           0x54
 40 #define BP_CLPCR_LPM                    0
 41 #define BM_CLPCR_LPM                    (0x3 << 0)
 42 #define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
 43 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
 44 #define BM_CLPCR_SBYOS                  (0x1 << 6)
 45 #define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
 46 #define BM_CLPCR_VSTBY                  (0x1 << 8)
 47 #define BP_CLPCR_STBY_COUNT             9
 48 #define BM_CLPCR_STBY_COUNT             (0x3 << 9)
 49 #define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
 50 #define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
 51 #define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
 52 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
 53 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
 54 #define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
 55 #define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
 56 #define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
 57 #define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
 58 #define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
 59 #define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
 60 
 61 #define CGPR                            0x64
 62 #define BM_CGPR_INT_MEM_CLK_LPM         (0x1 << 17)
 63 
 64 #define MX6Q_SUSPEND_OCRAM_SIZE         0x1000
 65 #define MX6_MAX_MMDC_IO_NUM             33
 66 
 67 static void __iomem *ccm_base;
 68 static void __iomem *suspend_ocram_base;
 69 static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
 70 
 71 /*
 72  * suspend ocram space layout:
 73  * ======================== high address ======================
 74  *                              .
 75  *                              .
 76  *                              .
 77  *                              ^
 78  *                              ^
 79  *                              ^
 80  *                      imx6_suspend code
 81  *              PM_INFO structure(imx6_cpu_pm_info)
 82  * ======================== low address =======================
 83  */
 84 
 85 struct imx6_pm_base {
 86         phys_addr_t pbase;
 87         void __iomem *vbase;
 88 };
 89 
 90 struct imx6_pm_socdata {
 91         u32 ddr_type;
 92         const char *mmdc_compat;
 93         const char *src_compat;
 94         const char *iomuxc_compat;
 95         const char *gpc_compat;
 96         const u32 mmdc_io_num;
 97         const u32 *mmdc_io_offset;
 98 };
 99 
100 static const u32 imx6q_mmdc_io_offset[] __initconst = {
101         0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
102         0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
103         0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
104         0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
105         0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
106         0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
107         0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
108         0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
109         0x74c,                      /* GPR_ADDS */
110 };
111 
112 static const u32 imx6dl_mmdc_io_offset[] __initconst = {
113         0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
114         0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
115         0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
116         0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
117         0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
118         0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
119         0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
120         0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
121         0x74c,                      /* GPR_ADDS */
122 };
123 
124 static const u32 imx6sl_mmdc_io_offset[] __initconst = {
125         0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
126         0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
127         0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
128         0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
129         0x330, 0x334, 0x320,        /* SDCKE0, SDCKE1, RESET */
130 };
131 
132 static const u32 imx6sx_mmdc_io_offset[] __initconst = {
133         0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
134         0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
135         0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
136         0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
137         0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
138 };
139 
140 static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
141         .mmdc_compat = "fsl,imx6q-mmdc",
142         .src_compat = "fsl,imx6q-src",
143         .iomuxc_compat = "fsl,imx6q-iomuxc",
144         .gpc_compat = "fsl,imx6q-gpc",
145         .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
146         .mmdc_io_offset = imx6q_mmdc_io_offset,
147 };
148 
149 static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
150         .mmdc_compat = "fsl,imx6q-mmdc",
151         .src_compat = "fsl,imx6q-src",
152         .iomuxc_compat = "fsl,imx6dl-iomuxc",
153         .gpc_compat = "fsl,imx6q-gpc",
154         .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
155         .mmdc_io_offset = imx6dl_mmdc_io_offset,
156 };
157 
158 static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
159         .mmdc_compat = "fsl,imx6sl-mmdc",
160         .src_compat = "fsl,imx6sl-src",
161         .iomuxc_compat = "fsl,imx6sl-iomuxc",
162         .gpc_compat = "fsl,imx6sl-gpc",
163         .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
164         .mmdc_io_offset = imx6sl_mmdc_io_offset,
165 };
166 
167 static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
168         .mmdc_compat = "fsl,imx6sx-mmdc",
169         .src_compat = "fsl,imx6sx-src",
170         .iomuxc_compat = "fsl,imx6sx-iomuxc",
171         .gpc_compat = "fsl,imx6sx-gpc",
172         .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
173         .mmdc_io_offset = imx6sx_mmdc_io_offset,
174 };
175 
176 /*
177  * This structure is for passing necessary data for low level ocram
178  * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
179  * definition is changed, the offset definition in
180  * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
181  * otherwise, the suspend to ocram function will be broken!
182  */
183 struct imx6_cpu_pm_info {
184         phys_addr_t pbase; /* The physical address of pm_info. */
185         phys_addr_t resume_addr; /* The physical resume address for asm code */
186         u32 ddr_type;
187         u32 pm_info_size; /* Size of pm_info. */
188         struct imx6_pm_base mmdc_base;
189         struct imx6_pm_base src_base;
190         struct imx6_pm_base iomuxc_base;
191         struct imx6_pm_base ccm_base;
192         struct imx6_pm_base gpc_base;
193         struct imx6_pm_base l2_base;
194         u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
195         u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
196 } __aligned(8);
197 
198 void imx6q_set_int_mem_clk_lpm(bool enable)
199 {
200         u32 val = readl_relaxed(ccm_base + CGPR);
201 
202         val &= ~BM_CGPR_INT_MEM_CLK_LPM;
203         if (enable)
204                 val |= BM_CGPR_INT_MEM_CLK_LPM;
205         writel_relaxed(val, ccm_base + CGPR);
206 }
207 
208 void imx6_enable_rbc(bool enable)
209 {
210         u32 val;
211 
212         /*
213          * need to mask all interrupts in GPC before
214          * operating RBC configurations
215          */
216         imx_gpc_mask_all();
217 
218         /* configure RBC enable bit */
219         val = readl_relaxed(ccm_base + CCR);
220         val &= ~BM_CCR_RBC_EN;
221         val |= enable ? BM_CCR_RBC_EN : 0;
222         writel_relaxed(val, ccm_base + CCR);
223 
224         /* configure RBC count */
225         val = readl_relaxed(ccm_base + CCR);
226         val &= ~BM_CCR_RBC_BYPASS_COUNT;
227         val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
228         writel(val, ccm_base + CCR);
229 
230         /*
231          * need to delay at least 2 cycles of CKIL(32K)
232          * due to hardware design requirement, which is
233          * ~61us, here we use 65us for safe
234          */
235         udelay(65);
236 
237         /* restore GPC interrupt mask settings */
238         imx_gpc_restore_all();
239 }
240 
241 static void imx6q_enable_wb(bool enable)
242 {
243         u32 val;
244 
245         /* configure well bias enable bit */
246         val = readl_relaxed(ccm_base + CLPCR);
247         val &= ~BM_CLPCR_WB_PER_AT_LPM;
248         val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
249         writel_relaxed(val, ccm_base + CLPCR);
250 
251         /* configure well bias count */
252         val = readl_relaxed(ccm_base + CCR);
253         val &= ~BM_CCR_WB_COUNT;
254         val |= enable ? BM_CCR_WB_COUNT : 0;
255         writel_relaxed(val, ccm_base + CCR);
256 }
257 
258 int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
259 {
260         u32 val = readl_relaxed(ccm_base + CLPCR);
261 
262         val &= ~BM_CLPCR_LPM;
263         switch (mode) {
264         case WAIT_CLOCKED:
265                 break;
266         case WAIT_UNCLOCKED:
267                 val |= 0x1 << BP_CLPCR_LPM;
268                 val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
269                 break;
270         case STOP_POWER_ON:
271                 val |= 0x2 << BP_CLPCR_LPM;
272                 val &= ~BM_CLPCR_VSTBY;
273                 val &= ~BM_CLPCR_SBYOS;
274                 if (cpu_is_imx6sl())
275                         val |= BM_CLPCR_BYPASS_PMIC_READY;
276                 if (cpu_is_imx6sl() || cpu_is_imx6sx())
277                         val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
278                 else
279                         val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
280                 break;
281         case WAIT_UNCLOCKED_POWER_OFF:
282                 val |= 0x1 << BP_CLPCR_LPM;
283                 val &= ~BM_CLPCR_VSTBY;
284                 val &= ~BM_CLPCR_SBYOS;
285                 break;
286         case STOP_POWER_OFF:
287                 val |= 0x2 << BP_CLPCR_LPM;
288                 val |= 0x3 << BP_CLPCR_STBY_COUNT;
289                 val |= BM_CLPCR_VSTBY;
290                 val |= BM_CLPCR_SBYOS;
291                 if (cpu_is_imx6sl())
292                         val |= BM_CLPCR_BYPASS_PMIC_READY;
293                 if (cpu_is_imx6sl() || cpu_is_imx6sx())
294                         val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
295                 else
296                         val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
297                 break;
298         default:
299                 return -EINVAL;
300         }
301 
302         /*
303          * ERR007265: CCM: When improper low-power sequence is used,
304          * the SoC enters low power mode before the ARM core executes WFI.
305          *
306          * Software workaround:
307          * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
308          *    by setting IOMUX_GPR1_GINT.
309          * 2) Software should then unmask IRQ #32 in GPC before setting CCM
310          *    Low-Power mode.
311          * 3) Software should mask IRQ #32 right after CCM Low-Power mode
312          *    is set (set bits 0-1 of CCM_CLPCR).
313          *
314          * Note that IRQ #32 is GIC SPI #0.
315          */
316         imx_gpc_hwirq_unmask(0);
317         writel_relaxed(val, ccm_base + CLPCR);
318         imx_gpc_hwirq_mask(0);
319 
320         return 0;
321 }
322 
323 static int imx6q_suspend_finish(unsigned long val)
324 {
325         if (!imx6_suspend_in_ocram_fn) {
326                 cpu_do_idle();
327         } else {
328                 /*
329                  * call low level suspend function in ocram,
330                  * as we need to float DDR IO.
331                  */
332                 local_flush_tlb_all();
333                 imx6_suspend_in_ocram_fn(suspend_ocram_base);
334         }
335 
336         return 0;
337 }
338 
339 static int imx6q_pm_enter(suspend_state_t state)
340 {
341         switch (state) {
342         case PM_SUSPEND_STANDBY:
343                 imx6_set_lpm(STOP_POWER_ON);
344                 imx6q_set_int_mem_clk_lpm(true);
345                 imx_gpc_pre_suspend(false);
346                 if (cpu_is_imx6sl())
347                         imx6sl_set_wait_clk(true);
348                 /* Zzz ... */
349                 cpu_do_idle();
350                 if (cpu_is_imx6sl())
351                         imx6sl_set_wait_clk(false);
352                 imx_gpc_post_resume();
353                 imx6_set_lpm(WAIT_CLOCKED);
354                 break;
355         case PM_SUSPEND_MEM:
356                 imx6_set_lpm(STOP_POWER_OFF);
357                 imx6q_set_int_mem_clk_lpm(false);
358                 imx6q_enable_wb(true);
359                 /*
360                  * For suspend into ocram, asm code already take care of
361                  * RBC setting, so we do NOT need to do that here.
362                  */
363                 if (!imx6_suspend_in_ocram_fn)
364                         imx6_enable_rbc(true);
365                 imx_gpc_pre_suspend(true);
366                 imx_anatop_pre_suspend();
367                 /* Zzz ... */
368                 cpu_suspend(0, imx6q_suspend_finish);
369                 if (cpu_is_imx6q() || cpu_is_imx6dl())
370                         imx_smp_prepare();
371                 imx_anatop_post_resume();
372                 imx_gpc_post_resume();
373                 imx6_enable_rbc(false);
374                 imx6q_enable_wb(false);
375                 imx6q_set_int_mem_clk_lpm(true);
376                 imx6_set_lpm(WAIT_CLOCKED);
377                 break;
378         default:
379                 return -EINVAL;
380         }
381 
382         return 0;
383 }
384 
385 static int imx6q_pm_valid(suspend_state_t state)
386 {
387         return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
388 }
389 
390 static const struct platform_suspend_ops imx6q_pm_ops = {
391         .enter = imx6q_pm_enter,
392         .valid = imx6q_pm_valid,
393 };
394 
395 static int __init imx6_pm_get_base(struct imx6_pm_base *base,
396                                 const char *compat)
397 {
398         struct device_node *node;
399         struct resource res;
400         int ret = 0;
401 
402         node = of_find_compatible_node(NULL, NULL, compat);
403         if (!node) {
404                 ret = -ENODEV;
405                 goto out;
406         }
407 
408         ret = of_address_to_resource(node, 0, &res);
409         if (ret)
410                 goto put_node;
411 
412         base->pbase = res.start;
413         base->vbase = ioremap(res.start, resource_size(&res));
414         if (!base->vbase)
415                 ret = -ENOMEM;
416 
417 put_node:
418         of_node_put(node);
419 out:
420         return ret;
421 }
422 
423 static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
424 {
425         phys_addr_t ocram_pbase;
426         struct device_node *node;
427         struct platform_device *pdev;
428         struct imx6_cpu_pm_info *pm_info;
429         struct gen_pool *ocram_pool;
430         unsigned long ocram_base;
431         int i, ret = 0;
432         const u32 *mmdc_offset_array;
433 
434         suspend_set_ops(&imx6q_pm_ops);
435 
436         if (!socdata) {
437                 pr_warn("%s: invalid argument!\n", __func__);
438                 return -EINVAL;
439         }
440 
441         node = of_find_compatible_node(NULL, NULL, "mmio-sram");
442         if (!node) {
443                 pr_warn("%s: failed to find ocram node!\n", __func__);
444                 return -ENODEV;
445         }
446 
447         pdev = of_find_device_by_node(node);
448         if (!pdev) {
449                 pr_warn("%s: failed to find ocram device!\n", __func__);
450                 ret = -ENODEV;
451                 goto put_node;
452         }
453 
454         ocram_pool = gen_pool_get(&pdev->dev);
455         if (!ocram_pool) {
456                 pr_warn("%s: ocram pool unavailable!\n", __func__);
457                 ret = -ENODEV;
458                 goto put_node;
459         }
460 
461         ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
462         if (!ocram_base) {
463                 pr_warn("%s: unable to alloc ocram!\n", __func__);
464                 ret = -ENOMEM;
465                 goto put_node;
466         }
467 
468         ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
469 
470         suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
471                 MX6Q_SUSPEND_OCRAM_SIZE, false);
472 
473         pm_info = suspend_ocram_base;
474         pm_info->pbase = ocram_pbase;
475         pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
476         pm_info->pm_info_size = sizeof(*pm_info);
477 
478         /*
479          * ccm physical address is not used by asm code currently,
480          * so get ccm virtual address directly.
481          */
482         pm_info->ccm_base.vbase = ccm_base;
483 
484         ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
485         if (ret) {
486                 pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
487                 goto put_node;
488         }
489 
490         ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
491         if (ret) {
492                 pr_warn("%s: failed to get src base %d!\n", __func__, ret);
493                 goto src_map_failed;
494         }
495 
496         ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
497         if (ret) {
498                 pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
499                 goto iomuxc_map_failed;
500         }
501 
502         ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
503         if (ret) {
504                 pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
505                 goto gpc_map_failed;
506         }
507 
508         ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache");
509         if (ret) {
510                 pr_warn("%s: failed to get pl310-cache base %d!\n",
511                         __func__, ret);
512                 goto pl310_cache_map_failed;
513         }
514 
515         pm_info->ddr_type = imx_mmdc_get_ddr_type();
516         pm_info->mmdc_io_num = socdata->mmdc_io_num;
517         mmdc_offset_array = socdata->mmdc_io_offset;
518 
519         for (i = 0; i < pm_info->mmdc_io_num; i++) {
520                 pm_info->mmdc_io_val[i][0] =
521                         mmdc_offset_array[i];
522                 pm_info->mmdc_io_val[i][1] =
523                         readl_relaxed(pm_info->iomuxc_base.vbase +
524                         mmdc_offset_array[i]);
525         }
526 
527         imx6_suspend_in_ocram_fn = fncpy(
528                 suspend_ocram_base + sizeof(*pm_info),
529                 &imx6_suspend,
530                 MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
531 
532         goto put_node;
533 
534 pl310_cache_map_failed:
535         iounmap(&pm_info->gpc_base.vbase);
536 gpc_map_failed:
537         iounmap(&pm_info->iomuxc_base.vbase);
538 iomuxc_map_failed:
539         iounmap(&pm_info->src_base.vbase);
540 src_map_failed:
541         iounmap(&pm_info->mmdc_base.vbase);
542 put_node:
543         of_node_put(node);
544 
545         return ret;
546 }
547 
548 static void __init imx6_pm_common_init(const struct imx6_pm_socdata
549                                         *socdata)
550 {
551         struct regmap *gpr;
552         int ret;
553 
554         WARN_ON(!ccm_base);
555 
556         if (IS_ENABLED(CONFIG_SUSPEND)) {
557                 ret = imx6q_suspend_init(socdata);
558                 if (ret)
559                         pr_warn("%s: No DDR LPM support with suspend %d!\n",
560                                 __func__, ret);
561         }
562 
563         /*
564          * This is for SW workaround step #1 of ERR007265, see comments
565          * in imx6_set_lpm for details of this errata.
566          * Force IOMUXC irq pending, so that the interrupt to GPC can be
567          * used to deassert dsm_request signal when the signal gets
568          * asserted unexpectedly.
569          */
570         gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
571         if (!IS_ERR(gpr))
572                 regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
573                                    IMX6Q_GPR1_GINT);
574 }
575 
576 void __init imx6_pm_ccm_init(const char *ccm_compat)
577 {
578         struct device_node *np;
579         u32 val;
580 
581         np = of_find_compatible_node(NULL, NULL, ccm_compat);
582         ccm_base = of_iomap(np, 0);
583         BUG_ON(!ccm_base);
584 
585         /*
586          * Initialize CCM_CLPCR_LPM into RUN mode to avoid ARM core
587          * clock being shut down unexpectedly by WAIT mode.
588          */
589         val = readl_relaxed(ccm_base + CLPCR);
590         val &= ~BM_CLPCR_LPM;
591         writel_relaxed(val, ccm_base + CLPCR);
592 }
593 
594 void __init imx6q_pm_init(void)
595 {
596         imx6_pm_common_init(&imx6q_pm_data);
597 }
598 
599 void __init imx6dl_pm_init(void)
600 {
601         imx6_pm_common_init(&imx6dl_pm_data);
602 }
603 
604 void __init imx6sl_pm_init(void)
605 {
606         imx6_pm_common_init(&imx6sl_pm_data);
607 }
608 
609 void __init imx6sx_pm_init(void)
610 {
611         imx6_pm_common_init(&imx6sx_pm_data);
612 }
613 

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