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Linux/arch/arm/mach-imx/system.c

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  1 /*
  2  * Copyright (C) 1999 ARM Limited
  3  * Copyright (C) 2000 Deep Blue Solutions Ltd
  4  * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  5  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  6  * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  */
 18 
 19 #include <linux/kernel.h>
 20 #include <linux/clk.h>
 21 #include <linux/io.h>
 22 #include <linux/err.h>
 23 #include <linux/delay.h>
 24 #include <linux/of.h>
 25 #include <linux/of_address.h>
 26 
 27 #include <asm/system_misc.h>
 28 #include <asm/proc-fns.h>
 29 #include <asm/mach-types.h>
 30 #include <asm/hardware/cache-l2x0.h>
 31 
 32 #include "common.h"
 33 #include "hardware.h"
 34 
 35 static void __iomem *wdog_base;
 36 static struct clk *wdog_clk;
 37 static int wcr_enable = (1 << 2);
 38 
 39 /*
 40  * Reset the system. It is called by machine_restart().
 41  */
 42 void mxc_restart(enum reboot_mode mode, const char *cmd)
 43 {
 44         if (!wdog_base)
 45                 goto reset_fallback;
 46 
 47         if (!IS_ERR(wdog_clk))
 48                 clk_enable(wdog_clk);
 49 
 50         /* Assert SRS signal */
 51         imx_writew(wcr_enable, wdog_base);
 52         /*
 53          * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
 54          * written twice), we add another two writes to ensure there must be at
 55          * least two writes happen in the same one 32kHz clock period.  We save
 56          * the target check here, since the writes shouldn't be a huge burden
 57          * for other platforms.
 58          */
 59         imx_writew(wcr_enable, wdog_base);
 60         imx_writew(wcr_enable, wdog_base);
 61 
 62         /* wait for reset to assert... */
 63         mdelay(500);
 64 
 65         pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
 66 
 67         /* delay to allow the serial port to show the message */
 68         mdelay(50);
 69 
 70 reset_fallback:
 71         /* we'll take a jump through zero as a poor second */
 72         soft_restart(0);
 73 }
 74 
 75 void __init mxc_arch_reset_init(void __iomem *base)
 76 {
 77         wdog_base = base;
 78 
 79         wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
 80         if (IS_ERR(wdog_clk))
 81                 pr_warn("%s: failed to get wdog clock\n", __func__);
 82         else
 83                 clk_prepare(wdog_clk);
 84 }
 85 
 86 #ifdef CONFIG_SOC_IMX1
 87 void __init imx1_reset_init(void __iomem *base)
 88 {
 89         wcr_enable = (1 << 0);
 90         mxc_arch_reset_init(base);
 91 }
 92 #endif
 93 
 94 #ifdef CONFIG_CACHE_L2X0
 95 void __init imx_init_l2cache(void)
 96 {
 97         void __iomem *l2x0_base;
 98         struct device_node *np;
 99         unsigned int val;
100 
101         np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
102         if (!np)
103                 return;
104 
105         l2x0_base = of_iomap(np, 0);
106         if (!l2x0_base)
107                 goto put_node;
108 
109         if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
110                 /* Configure the L2 PREFETCH and POWER registers */
111                 val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
112                 val |= L310_PREFETCH_CTRL_DBL_LINEFILL |
113                         L310_PREFETCH_CTRL_INSTR_PREFETCH |
114                         L310_PREFETCH_CTRL_DATA_PREFETCH;
115 
116                 /* Set perfetch offset to improve performance */
117                 val &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
118                 val |= 15;
119 
120                 writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
121         }
122 
123         iounmap(l2x0_base);
124 put_node:
125         of_node_put(np);
126 }
127 #endif
128 

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