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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-iop13xx/pci.c

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  1 /*
  2  * iop13xx PCI support
  3  * Copyright (c) 2005-2006, Intel Corporation.
  4  *
  5  * This program is free software; you can redistribute it and/or modify it
  6  * under the terms and conditions of the GNU General Public License,
  7  * version 2, as published by the Free Software Foundation.
  8  *
  9  * This program is distributed in the hope it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 12  * more details.
 13  *
 14  * You should have received a copy of the GNU General Public License along with
 15  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 16  * Place - Suite 330, Boston, MA 02111-1307 USA.
 17  *
 18  */
 19 
 20 #include <linux/pci.h>
 21 #include <linux/slab.h>
 22 #include <linux/delay.h>
 23 #include <linux/jiffies.h>
 24 #include <linux/export.h>
 25 #include <asm/irq.h>
 26 #include <mach/hardware.h>
 27 #include <asm/sizes.h>
 28 #include <asm/signal.h>
 29 #include <asm/mach/pci.h>
 30 #include "pci.h"
 31 
 32 #define IOP13XX_PCI_DEBUG 0
 33 #define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
 34 
 35 u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
 36 u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
 37 static struct pci_bus *pci_bus_atux = 0;
 38 static struct pci_bus *pci_bus_atue = 0;
 39 void __iomem *iop13xx_atue_mem_base;
 40 void __iomem *iop13xx_atux_mem_base;
 41 size_t iop13xx_atue_mem_size;
 42 size_t iop13xx_atux_mem_size;
 43 
 44 EXPORT_SYMBOL(iop13xx_atue_mem_base);
 45 EXPORT_SYMBOL(iop13xx_atux_mem_base);
 46 EXPORT_SYMBOL(iop13xx_atue_mem_size);
 47 EXPORT_SYMBOL(iop13xx_atux_mem_size);
 48 
 49 int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */
 50 static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first
 51                                                  access */
 52 
 53 /* Scan the initialized busses and ioremap the requested memory range
 54  */
 55 void iop13xx_map_pci_memory(void)
 56 {
 57         int atu;
 58         struct pci_bus *bus;
 59         struct pci_dev *dev;
 60         resource_size_t end = 0;
 61 
 62         for (atu = 0; atu < 2; atu++) {
 63                 bus = atu ? pci_bus_atue : pci_bus_atux;
 64                 if (bus) {
 65                         list_for_each_entry(dev, &bus->devices, bus_list) {
 66                                 int i;
 67                                 int max = 7;
 68 
 69                                 if (dev->subordinate)
 70                                         max = DEVICE_COUNT_RESOURCE;
 71 
 72                                 for (i = 0; i < max; i++) {
 73                                         struct resource *res = &dev->resource[i];
 74                                         if (res->flags & IORESOURCE_MEM)
 75                                                 end = max(res->end, end);
 76                                 }
 77                         }
 78 
 79                         switch(atu) {
 80                         case 0:
 81                                 iop13xx_atux_mem_size =
 82                                         (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1;
 83 
 84                                 /* 16MB align the request */
 85                                 if (iop13xx_atux_mem_size & (SZ_16M - 1)) {
 86                                         iop13xx_atux_mem_size &= ~(SZ_16M - 1);
 87                                         iop13xx_atux_mem_size += SZ_16M;
 88                                 }
 89 
 90                                 if (end) {
 91                                         iop13xx_atux_mem_base = __arm_ioremap_pfn(
 92                                         __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
 93                                         , 0, iop13xx_atux_mem_size, MT_DEVICE);
 94                                         if (!iop13xx_atux_mem_base) {
 95                                                 printk("%s: atux allocation "
 96                                                        "failed\n", __func__);
 97                                                 BUG();
 98                                         }
 99                                 } else
100                                         iop13xx_atux_mem_size = 0;
101                                 PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
102                                 __func__, atu, iop13xx_atux_mem_size,
103                                 iop13xx_atux_mem_base);
104                                 break;
105                         case 1:
106                                 iop13xx_atue_mem_size =
107                                         (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1;
108 
109                                 /* 16MB align the request */
110                                 if (iop13xx_atue_mem_size & (SZ_16M - 1)) {
111                                         iop13xx_atue_mem_size &= ~(SZ_16M - 1);
112                                         iop13xx_atue_mem_size += SZ_16M;
113                                 }
114 
115                                 if (end) {
116                                         iop13xx_atue_mem_base = __arm_ioremap_pfn(
117                                         __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
118                                         , 0, iop13xx_atue_mem_size, MT_DEVICE);
119                                         if (!iop13xx_atue_mem_base) {
120                                                 printk("%s: atue allocation "
121                                                        "failed\n", __func__);
122                                                 BUG();
123                                         }
124                                 } else
125                                         iop13xx_atue_mem_size = 0;
126                                 PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
127                                 __func__, atu, iop13xx_atue_mem_size,
128                                 iop13xx_atue_mem_base);
129                                 break;
130                         }
131 
132                         printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n",
133                         atu ? "ATUE" : "ATUX",
134                         (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
135                         SZ_1M,
136                         atu ? IOP13XX_PCIE_LOWER_MEM_RA :
137                         IOP13XX_PCIX_LOWER_MEM_RA,
138                         atu ? iop13xx_atue_mem_base :
139                         iop13xx_atux_mem_base);
140                         end = 0;
141                 }
142 
143         }
144 }
145 
146 static int iop13xx_atu_function(int atu)
147 {
148         int func = 0;
149         /* the function number depends on the value of the
150          * IOP13XX_INTERFACE_SEL_PCIX reset strap
151          * see C-Spec section 3.17
152          */
153         switch(atu) {
154         case IOP13XX_INIT_ATU_ATUX:
155                 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
156                         func = 5;
157                 else
158                         func = 0;
159                 break;
160         case IOP13XX_INIT_ATU_ATUE:
161                 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
162                         func = 0;
163                 else
164                         func = 5;
165                 break;
166         default:
167                 BUG();
168         }
169 
170         return func;
171 }
172 
173 /* iop13xx_atux_cfg_address - format a configuration address for atux
174  * @bus: Target bus to access
175  * @devfn: Combined device number and function number
176  * @where: Desired register's address offset
177  *
178  * Convert the parameters to a configuration address formatted
179  * according the PCI-X 2.0 specification
180  */
181 static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where)
182 {
183         struct pci_sys_data *sys = bus->sysdata;
184         u32 addr;
185 
186         if (sys->busnr == bus->number)
187                 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
188         else
189                 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
190 
191         addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3);
192         addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */
193 
194         return addr;
195 }
196 
197 /* iop13xx_atue_cfg_address - format a configuration address for atue
198  * @bus: Target bus to access
199  * @devfn: Combined device number and function number
200  * @where: Desired register's address offset
201  *
202  * Convert the parameters to an address usable by the ATUE_OCCAR
203  */
204 static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
205 {
206         struct pci_sys_data *sys = bus->sysdata;
207         u32 addr;
208 
209         PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d",
210                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
211         addr = ((u32) bus->number)     << IOP13XX_ATUE_OCCAR_BUS_NUM |
212                    ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM |
213                    ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM |
214                    (where & ~0x3);
215 
216         if (sys->busnr != bus->number)
217                 addr |= 1; /* type 1 access */
218 
219         return addr;
220 }
221 
222 /* This routine checks the status of the last configuration cycle.  If an error
223  * was detected it returns >0, else it returns a 0.  The errors being checked
224  * are parity, master abort, target abort (master and target).  These types of
225  * errors occur during a config cycle where there is no device, like during
226  * the discovery stage.
227  */
228 static int iop13xx_atux_pci_status(int clear)
229 {
230         unsigned int status;
231         int err = 0;
232 
233         /*
234          * Check the status registers.
235          */
236         status = __raw_readw(IOP13XX_ATUX_ATUSR);
237         if (status & IOP_PCI_STATUS_ERROR)
238         {
239                 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
240                 if(clear)
241                         __raw_writew(status & IOP_PCI_STATUS_ERROR,
242                                 IOP13XX_ATUX_ATUSR);
243                 err = 1;
244         }
245         status = __raw_readl(IOP13XX_ATUX_ATUISR);
246         if (status & IOP13XX_ATUX_ATUISR_ERROR)
247         {
248                 PRINTK("\t\t\tPCI error interrupt:  ATUISR %#08x", status);
249                 if(clear)
250                         __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR,
251                                 IOP13XX_ATUX_ATUISR);
252                 err = 1;
253         }
254         return err;
255 }
256 
257 /* Simply write the address register and read the configuration
258  * data.  Note that the data dependency on %0 encourages an abort
259  * to be detected before we return.
260  */
261 static u32 iop13xx_atux_read(unsigned long addr)
262 {
263         u32 val;
264 
265         __asm__ __volatile__(
266                 "str    %1, [%2]\n\t"
267                 "ldr    %0, [%3]\n\t"
268                 "mov    %0, %0\n\t"
269                 : "=r" (val)
270                 : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR));
271 
272         return val;
273 }
274 
275 /* The read routines must check the error status of the last configuration
276  * cycle.  If there was an error, the routine returns all hex f's.
277  */
278 static int
279 iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where,
280                 int size, u32 *value)
281 {
282         unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
283         u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8);
284 
285         if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
286                 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
287                         IOP13XX_XBG_BECSR);
288                 val = 0xffffffff;
289         }
290 
291         *value = val;
292 
293         return PCIBIOS_SUCCESSFUL;
294 }
295 
296 static int
297 iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where,
298                 int size, u32 value)
299 {
300         unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
301         u32 val;
302 
303         if (size != 4) {
304                 val = iop13xx_atux_read(addr);
305                 if (!iop13xx_atux_pci_status(1) == 0)
306                         return PCIBIOS_SUCCESSFUL;
307 
308                 where = (where & 3) * 8;
309 
310                 if (size == 1)
311                         val &= ~(0xff << where);
312                 else
313                         val &= ~(0xffff << where);
314 
315                 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR);
316         } else {
317                 __raw_writel(addr, IOP13XX_ATUX_OCCAR);
318                 __raw_writel(value, IOP13XX_ATUX_OCCDR);
319         }
320 
321         return PCIBIOS_SUCCESSFUL;
322 }
323 
324 static struct pci_ops iop13xx_atux_ops = {
325         .read   = iop13xx_atux_read_config,
326         .write  = iop13xx_atux_write_config,
327 };
328 
329 /* This routine checks the status of the last configuration cycle.  If an error
330  * was detected it returns >0, else it returns a 0.  The errors being checked
331  * are parity, master abort, target abort (master and target).  These types of
332  * errors occur during a config cycle where there is no device, like during
333  * the discovery stage.
334  */
335 static int iop13xx_atue_pci_status(int clear)
336 {
337         unsigned int status;
338         int err = 0;
339 
340         /*
341          * Check the status registers.
342          */
343 
344         /* standard pci status register */
345         status = __raw_readw(IOP13XX_ATUE_ATUSR);
346         if (status & IOP_PCI_STATUS_ERROR) {
347                 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
348                 if(clear)
349                         __raw_writew(status & IOP_PCI_STATUS_ERROR,
350                                 IOP13XX_ATUE_ATUSR);
351                 err++;
352         }
353 
354         /* check the normal status bits in the ATUISR */
355         status = __raw_readl(IOP13XX_ATUE_ATUISR);
356         if (status & IOP13XX_ATUE_ATUISR_ERROR) {
357                 PRINTK("\t\t\tPCI error: ATUISR %#08x", status);
358                 if (clear)
359                         __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR,
360                                 IOP13XX_ATUE_ATUISR);
361                 err++;
362 
363                 /* check the PCI-E status if the ATUISR reports an interface error */
364                 if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) {
365                         /* get the unmasked errors */
366                         status = __raw_readl(IOP13XX_ATUE_PIE_STS) &
367                                         ~(__raw_readl(IOP13XX_ATUE_PIE_MSK));
368 
369                         if (status) {
370                                 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
371                                         __raw_readl(IOP13XX_ATUE_PIE_STS));
372                                 err++;
373                         } else {
374                                 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
375                                         __raw_readl(IOP13XX_ATUE_PIE_STS));
376                                 PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x",
377                                         __raw_readl(IOP13XX_ATUE_PIE_MSK));
378                                 BUG();
379                         }
380 
381                         if(clear)
382                                 __raw_writel(status, IOP13XX_ATUE_PIE_STS);
383                 }
384         }
385 
386         return err;
387 }
388 
389 static int
390 iop13xx_pcie_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
391 {
392         WARN_ON(idsel != 0);
393 
394         switch (pin) {
395         case 1: return ATUE_INTA;
396         case 2: return ATUE_INTB;
397         case 3: return ATUE_INTC;
398         case 4: return ATUE_INTD;
399         default: return -1;
400         }
401 }
402 
403 static u32 iop13xx_atue_read(unsigned long addr)
404 {
405         u32 val;
406 
407         __raw_writel(addr, IOP13XX_ATUE_OCCAR);
408         val = __raw_readl(IOP13XX_ATUE_OCCDR);
409 
410         rmb();
411 
412         return val;
413 }
414 
415 /* The read routines must check the error status of the last configuration
416  * cycle.  If there was an error, the routine returns all hex f's.
417  */
418 static int
419 iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where,
420                 int size, u32 *value)
421 {
422         u32 val;
423         unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
424 
425         /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */
426         if (!PCI_SLOT(devfn) || (addr & 1)) {
427                 val = iop13xx_atue_read(addr) >> ((where & 3) * 8);
428                 if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) {
429                         __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
430                                 IOP13XX_XBG_BECSR);
431                         val = 0xffffffff;
432                 }
433 
434                 PRINTK("addr=%#0lx, val=%#010x", addr, val);
435         } else
436                 val = 0xffffffff;
437 
438         *value = val;
439 
440         return PCIBIOS_SUCCESSFUL;
441 }
442 
443 static int
444 iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where,
445                 int size, u32 value)
446 {
447         unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
448         u32 val;
449 
450         if (size != 4) {
451                 val = iop13xx_atue_read(addr);
452                 if (!iop13xx_atue_pci_status(1) == 0)
453                         return PCIBIOS_SUCCESSFUL;
454 
455                 where = (where & 3) * 8;
456 
457                 if (size == 1)
458                         val &= ~(0xff << where);
459                 else
460                         val &= ~(0xffff << where);
461 
462                 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR);
463         } else {
464                 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
465                 __raw_writel(value, IOP13XX_ATUE_OCCDR);
466         }
467 
468         return PCIBIOS_SUCCESSFUL;
469 }
470 
471 static struct pci_ops iop13xx_atue_ops = {
472         .read   = iop13xx_atue_read_config,
473         .write  = iop13xx_atue_write_config,
474 };
475 
476 /* When a PCI device does not exist during config cycles, the XScale gets a
477  * bus error instead of returning 0xffffffff.  We can't rely on the ATU status
478  * bits to tell us that it was indeed a configuration cycle that caused this
479  * error especially in the case when the ATUE link is down.  Instead we rely
480  * on data from the south XSI bridge to validate the abort
481  */
482 int
483 iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
484 {
485         PRINTK("Data abort: address = 0x%08lx "
486                     "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx",
487                 addr, fsr, regs->ARM_pc, regs->ARM_lr);
488 
489         PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR));
490         PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR));
491         PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR));
492 
493         /*  If it was an imprecise abort, then we need to correct the
494          *  return address to be _after_ the instruction.
495          */
496         if (fsr & (1 << 10))
497                 regs->ARM_pc += 4;
498 
499         if (is_atue_occdr_error() || is_atux_occdr_error())
500                 return 0;
501         else
502                 return 1;
503 }
504 
505 /* Scan an IOP13XX PCI bus.  nr selects which ATU we use.
506  */
507 int iop13xx_scan_bus(int nr, struct pci_host_bridge *bridge)
508 {
509         int which_atu, ret;
510         struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
511 
512         switch (init_atu) {
513         case IOP13XX_INIT_ATU_ATUX:
514                 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
515                 break;
516         case IOP13XX_INIT_ATU_ATUE:
517                 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
518                 break;
519         case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
520                 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
521                 break;
522         default:
523                 which_atu = 0;
524         }
525 
526         if (!which_atu) {
527                 BUG();
528                 return -ENODEV;
529         }
530 
531         list_splice_init(&sys->resources, &bridge->windows);
532         bridge->dev.parent = NULL;
533         bridge->sysdata = sys;
534         bridge->busnr = sys->busnr;
535 
536         switch (which_atu) {
537         case IOP13XX_INIT_ATU_ATUX:
538                 if (time_after_eq(jiffies + msecs_to_jiffies(1000),
539                                   atux_trhfa_timeout))  /* ensure not wrap */
540                         while(time_before(jiffies, atux_trhfa_timeout))
541                                 udelay(100);
542 
543                 bridge->ops = &iop13xx_atux_ops;
544                 ret = pci_scan_root_bus_bridge(bridge);
545                 if (!ret)
546                         pci_bus_atux = bridge->bus;
547                 break;
548         case IOP13XX_INIT_ATU_ATUE:
549                 bridge->ops = &iop13xx_atue_ops;
550                 ret = pci_scan_root_bus_bridge(bridge);
551                 if (!ret)
552                         pci_bus_atue = bridge->bus;
553                 break;
554         default:
555                 ret = -EINVAL;
556         }
557 
558         return ret;
559 }
560 
561 /* This function is called from iop13xx_pci_init() after assigning valid
562  * values to iop13xx_atue_pmmr_offset.  This is the location for common
563  * setup of ATUE for all IOP13XX implementations.
564  */
565 void __init iop13xx_atue_setup(void)
566 {
567         int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE);
568         u32 reg_val;
569 
570 #ifdef CONFIG_PCI_MSI
571         /* BAR 0 (inbound msi window) */
572         __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
573         __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0);
574         __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0);
575         __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0);
576 #endif
577 
578         /* BAR 1 (1:1 mapping with Physical RAM) */
579         /* Set limit and enable */
580         __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
581                         IOP13XX_ATUE_IALR1);
582         __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
583 
584         /* Set base at the top of the reserved address space */
585         __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
586                         PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1);
587 
588         /* 1:1 mapping with physical ram
589          * (leave big endian byte swap disabled)
590          */
591          __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
592          __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1);
593 
594         /* Outbound window 1 (PCIX/PCIE memory window) */
595         /* 32 bit Address Space */
596         __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1);
597         /* PA[35:32] */
598         __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE |
599                         (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32),
600                         IOP13XX_ATUE_OUMBAR1);
601 
602         /* Setup the I/O Bar
603          * A[35-16] in 31-12
604          */
605         __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000),
606                 IOP13XX_ATUE_OIOBAR);
607         __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
608 
609         /* clear startup errors */
610         iop13xx_atue_pci_status(1);
611 
612         /* OIOBAR function number
613          */
614         reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR);
615         reg_val &= ~0x7;
616         reg_val |= func;
617         __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR);
618 
619         /* OUMBAR function numbers
620          */
621         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
622         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
623                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
624         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
625         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
626 
627         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
628         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
629                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
630         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
631         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
632 
633         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
634         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
635                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
636         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
637         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
638 
639         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
640         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
641                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
642         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
643         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
644 
645         /* Enable inbound and outbound cycles
646          */
647         reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD);
648         reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
649                         PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
650         __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD);
651 
652         reg_val = __raw_readl(IOP13XX_ATUE_ATUCR);
653         reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN |
654                         IOP13XX_ATUE_ATUCR_IVM;
655         __raw_writel(reg_val, IOP13XX_ATUE_ATUCR);
656 }
657 
658 void __init iop13xx_atue_disable(void)
659 {
660         u32 reg_val;
661 
662         __raw_writew(0x0, IOP13XX_ATUE_ATUCMD);
663         __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR);
664 
665         /* wait for cycles to quiesce */
666         while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY |
667                                              IOP13XX_ATUE_PCSR_IN_Q_BUSY |
668                                              IOP13XX_ATUE_PCSR_LLRB_BUSY))
669                 cpu_relax();
670 
671         /* BAR 0 ( Disabled ) */
672         __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0);
673         __raw_writel(0x0, IOP13XX_ATUE_IABAR0);
674         __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0);
675         __raw_writel(0x0, IOP13XX_ATUE_IATVR0);
676         __raw_writel(0x0, IOP13XX_ATUE_IALR0);
677         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
678         reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
679         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
680 
681         /* BAR 1 ( Disabled ) */
682         __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
683         __raw_writel(0x0, IOP13XX_ATUE_IABAR1);
684         __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
685         __raw_writel(0x0, IOP13XX_ATUE_IATVR1);
686         __raw_writel(0x0, IOP13XX_ATUE_IALR1);
687         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
688         reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
689         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
690 
691         /* BAR 2 ( Disabled ) */
692         __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2);
693         __raw_writel(0x0, IOP13XX_ATUE_IABAR2);
694         __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2);
695         __raw_writel(0x0, IOP13XX_ATUE_IATVR2);
696         __raw_writel(0x0, IOP13XX_ATUE_IALR2);
697         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
698         reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
699         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
700 
701         /* BAR 3 ( Disabled ) */
702         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
703         reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
704         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
705 
706         /* Setup the I/O Bar
707          * A[35-16] in 31-12
708          */
709         __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000,
710                         IOP13XX_ATUE_OIOBAR);
711         __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
712 }
713 
714 /* This function is called from iop13xx_pci_init() after assigning valid
715  * values to iop13xx_atux_pmmr_offset.  This is the location for common
716  * setup of ATUX for all IOP13XX implementations.
717  */
718 void __init iop13xx_atux_setup(void)
719 {
720         u32 reg_val;
721         int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX);
722 
723         /* Take PCI-X bus out of reset if bootloader hasn't already.
724          * According to spec, we should wait for 2^25 PCI clocks to meet
725          * the PCI timing parameter Trhfa (RST# high to first access).
726          * This is rarely necessary and often ignored.
727          */
728         reg_val = __raw_readl(IOP13XX_ATUX_PCSR);
729         if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) {
730                 int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7;
731                 msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */
732                 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT,
733                                 IOP13XX_ATUX_PCSR);
734                 atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec);
735         }
736         else
737                 atux_trhfa_timeout = jiffies;
738 
739 #ifdef CONFIG_PCI_MSI
740         /* BAR 0 (inbound msi window) */
741         __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
742         __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0);
743         __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0);
744         __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0);
745 #endif
746 
747         /* BAR 1 (1:1 mapping with Physical RAM) */
748         /* Set limit and enable */
749         __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
750                         IOP13XX_ATUX_IALR1);
751         __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
752 
753         /* Set base at the top of the reserved address space */
754         __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
755                         PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1);
756 
757         /* 1:1 mapping with physical ram
758          * (leave big endian byte swap disabled)
759          */
760         __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
761         __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1);
762 
763         /* Outbound window 1 (PCIX/PCIE memory window) */
764         /* 32 bit Address Space */
765         __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1);
766         /* PA[35:32] */
767         __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE |
768                         IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32,
769                         IOP13XX_ATUX_OUMBAR1);
770 
771         /* Setup the I/O Bar
772          * A[35-16] in 31-12
773          */
774         __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
775                 IOP13XX_ATUX_OIOBAR);
776         __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
777 
778         /* clear startup errors */
779         iop13xx_atux_pci_status(1);
780 
781         /* OIOBAR function number
782          */
783         reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR);
784         reg_val &= ~0x7;
785         reg_val |= func;
786         __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR);
787 
788         /* OUMBAR function numbers
789          */
790         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
791         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
792                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
793         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
794         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
795 
796         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
797         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
798                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
799         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
800         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
801 
802         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
803         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
804                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
805         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
806         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
807 
808         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
809         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
810                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
811         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
812         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
813 
814         /* Enable inbound and outbound cycles
815          */
816         reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD);
817         reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
818                         PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
819         __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD);
820 
821         reg_val = __raw_readl(IOP13XX_ATUX_ATUCR);
822         reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN;
823         __raw_writel(reg_val, IOP13XX_ATUX_ATUCR);
824 }
825 
826 void __init iop13xx_atux_disable(void)
827 {
828         u32 reg_val;
829 
830         __raw_writew(0x0, IOP13XX_ATUX_ATUCMD);
831         __raw_writel(0x0, IOP13XX_ATUX_ATUCR);
832 
833         /* wait for cycles to quiesce */
834         while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY |
835                                      IOP13XX_ATUX_PCSR_IN_Q_BUSY))
836                 cpu_relax();
837 
838         /* BAR 0 ( Disabled ) */
839         __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0);
840         __raw_writel(0x0, IOP13XX_ATUX_IABAR0);
841         __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0);
842         __raw_writel(0x0, IOP13XX_ATUX_IATVR0);
843         __raw_writel(0x0, IOP13XX_ATUX_IALR0);
844         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
845         reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
846         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
847 
848         /* BAR 1 ( Disabled ) */
849         __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
850         __raw_writel(0x0, IOP13XX_ATUX_IABAR1);
851         __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
852         __raw_writel(0x0, IOP13XX_ATUX_IATVR1);
853         __raw_writel(0x0, IOP13XX_ATUX_IALR1);
854         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
855         reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
856         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
857 
858         /* BAR 2 ( Disabled ) */
859         __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2);
860         __raw_writel(0x0, IOP13XX_ATUX_IABAR2);
861         __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2);
862         __raw_writel(0x0, IOP13XX_ATUX_IATVR2);
863         __raw_writel(0x0, IOP13XX_ATUX_IALR2);
864         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
865         reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
866         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
867 
868         /* BAR 3 ( Disabled ) */
869         __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3);
870         __raw_writel(0x0, IOP13XX_ATUX_IABAR3);
871         __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3);
872         __raw_writel(0x0, IOP13XX_ATUX_IATVR3);
873         __raw_writel(0x0, IOP13XX_ATUX_IALR3);
874         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
875         reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
876         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
877 
878         /* Setup the I/O Bar
879         * A[35-16] in 31-12
880         */
881         __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
882                         IOP13XX_ATUX_OIOBAR);
883         __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
884 }
885 
886 void __init iop13xx_set_atu_mmr_bases(void)
887 {
888         /* Based on ESSR0, determine the ATU X/E offsets */
889         switch(__raw_readl(IOP13XX_ESSR0) &
890                 (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) {
891         /* both asserted */
892         case 0:
893                 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
894                 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
895                 break;
896         /* IOP13XX_CONTROLLER_ONLY = deasserted
897          * IOP13XX_INTERFACE_SEL_PCIX = asserted
898          */
899         case IOP13XX_CONTROLLER_ONLY:
900                 iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
901                 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
902                 break;
903         /* IOP13XX_CONTROLLER_ONLY = asserted
904          * IOP13XX_INTERFACE_SEL_PCIX = deasserted
905          */
906         case IOP13XX_INTERFACE_SEL_PCIX:
907                 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
908                 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
909                 break;
910         /* both deasserted */
911         case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX:
912                 iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
913                 iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
914                 break;
915         default:
916                 BUG();
917         }
918 }
919 
920 void __init iop13xx_atu_select(struct hw_pci *plat_pci)
921 {
922         int i;
923 
924         /* set system defaults
925          * note: if "iop13xx_init_atu=" is specified this autodetect
926          * sequence will be bypassed
927          */
928         if (init_atu == IOP13XX_INIT_ATU_DEFAULT) {
929                 /* check for single/dual interface */
930                 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) {
931                         /* ATUE must be present check the device id
932                          * to see if ATUX is present.
933                          */
934                         init_atu |= IOP13XX_INIT_ATU_ATUE;
935                         switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) {
936                         case 0x70:
937                         case 0x80:
938                         case 0xc0:
939                                 init_atu |= IOP13XX_INIT_ATU_ATUX;
940                                 break;
941                         }
942                 } else {
943                         /* ATUX must be present check the device id
944                          * to see if ATUE is present.
945                          */
946                         init_atu |= IOP13XX_INIT_ATU_ATUX;
947                         switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) {
948                         case 0x70:
949                         case 0x80:
950                         case 0xc0:
951                                 init_atu |= IOP13XX_INIT_ATU_ATUE;
952                                 break;
953                         }
954                 }
955 
956                 /* check central resource and root complex capability */
957                 if (init_atu & IOP13XX_INIT_ATU_ATUX)
958                         if (!(__raw_readl(IOP13XX_ATUX_PCSR) &
959                                 IOP13XX_ATUX_PCSR_CENTRAL_RES))
960                                 init_atu &= ~IOP13XX_INIT_ATU_ATUX;
961 
962                 if (init_atu & IOP13XX_INIT_ATU_ATUE)
963                         if (__raw_readl(IOP13XX_ATUE_PCSR) &
964                                 IOP13XX_ATUE_PCSR_END_POINT)
965                                 init_atu &= ~IOP13XX_INIT_ATU_ATUE;
966         }
967 
968         for (i = 0; i < 2; i++) {
969                 if((init_atu & (1 << i)) == (1 << i))
970                         plat_pci->nr_controllers++;
971         }
972 }
973 
974 void __init iop13xx_pci_init(void)
975 {
976         /* clear pre-existing south bridge errors */
977         __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
978 
979         /* Setup the Min Address for PCI memory... */
980         pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
981 
982         /* if Linux is given control of an ATU
983          * clear out its prior configuration,
984          * otherwise do not touch the registers
985          */
986         if (init_atu & IOP13XX_INIT_ATU_ATUE) {
987                 iop13xx_atue_disable();
988                 iop13xx_atue_setup();
989         }
990 
991         if (init_atu & IOP13XX_INIT_ATU_ATUX) {
992                 iop13xx_atux_disable();
993                 iop13xx_atux_setup();
994         }
995 
996         hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0,
997                         "imprecise external abort");
998 }
999 
1000 /* initialize the pci memory space.  handle any combination of
1001  * atue and atux enabled/disabled
1002  */
1003 int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
1004 {
1005         struct resource *res;
1006         int which_atu;
1007         u32 pcixsr, pcsr;
1008 
1009         if (nr > 1)
1010                 return 0;
1011 
1012         res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1013         if (!res)
1014                 panic("PCI: unable to alloc resources");
1015 
1016 
1017         /* 'nr' assumptions:
1018          * ATUX is always 0
1019          * ATUE is 1 when ATUX is also enabled
1020          * ATUE is 0 when ATUX is disabled
1021          */
1022         switch(init_atu) {
1023         case IOP13XX_INIT_ATU_ATUX:
1024                 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
1025                 break;
1026         case IOP13XX_INIT_ATU_ATUE:
1027                 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
1028                 break;
1029         case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
1030                 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
1031                 break;
1032         default:
1033                 which_atu = 0;
1034         }
1035 
1036         if (!which_atu) {
1037                 kfree(res);
1038                 return 0;
1039         }
1040 
1041         switch(which_atu) {
1042         case IOP13XX_INIT_ATU_ATUX:
1043                 pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR);
1044                 pcixsr &= ~0xffff;
1045                 pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM |
1046                           0 << IOP13XX_ATUX_PCIXSR_DEV_NUM |
1047                           iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX)
1048                                   << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
1049                 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
1050 
1051                 pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA);
1052 
1053                 res->start = IOP13XX_PCIX_LOWER_MEM_RA;
1054                 res->end   = IOP13XX_PCIX_UPPER_MEM_RA;
1055                 res->name  = "IQ81340 ATUX PCI Memory Space";
1056                 res->flags = IORESOURCE_MEM;
1057                 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
1058                 break;
1059         case IOP13XX_INIT_ATU_ATUE:
1060                 /* Note: the function number field in the PCSR is ro */
1061                 pcsr = __raw_readl(IOP13XX_ATUE_PCSR);
1062                 pcsr &= ~(0xfff8 << 16);
1063                 pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM |
1064                                 0 << IOP13XX_ATUE_PCSR_DEV_NUM;
1065 
1066                 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
1067 
1068                 pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA);
1069 
1070                 res->start = IOP13XX_PCIE_LOWER_MEM_RA;
1071                 res->end   = IOP13XX_PCIE_UPPER_MEM_RA;
1072                 res->name  = "IQ81340 ATUE PCI Memory Space";
1073                 res->flags = IORESOURCE_MEM;
1074                 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
1075                 sys->map_irq = iop13xx_pcie_map_irq;
1076                 break;
1077         default:
1078                 kfree(res);
1079                 return 0;
1080         }
1081 
1082         request_resource(&iomem_resource, res);
1083 
1084         pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
1085 
1086         return 1;
1087 }
1088 
1089 u16 iop13xx_dev_id(void)
1090 {
1091         if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
1092                 return __raw_readw(IOP13XX_ATUE_DID);
1093         else
1094                 return __raw_readw(IOP13XX_ATUX_DID);
1095 }
1096 
1097 static int __init iop13xx_init_atu_setup(char *str)
1098 {
1099         init_atu = IOP13XX_INIT_ATU_NONE;
1100         if (str) {
1101                 while (*str != '\0') {
1102                         switch (*str) {
1103                         case 'x':
1104                         case 'X':
1105                                 init_atu |= IOP13XX_INIT_ATU_ATUX;
1106                                 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1107                                 break;
1108                         case 'e':
1109                         case 'E':
1110                                 init_atu |= IOP13XX_INIT_ATU_ATUE;
1111                                 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1112                                 break;
1113                         case ',':
1114                         case '=':
1115                                 break;
1116                         default:
1117                                 PRINTK("\"iop13xx_init_atu\" malformed at "
1118                                             "character: \'%c\'", *str);
1119                                 *(str + 1) = '\0';
1120                                 init_atu = IOP13XX_INIT_ATU_DEFAULT;
1121                         }
1122                         str++;
1123                 }
1124         }
1125         return 1;
1126 }
1127 
1128 __setup("iop13xx_init_atu", iop13xx_init_atu_setup);
1129 

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