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Linux/arch/arm/mach-ixp4xx/common-pci.c

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  1 /*
  2  * arch/arm/mach-ixp4xx/common-pci.c 
  3  *
  4  * IXP4XX PCI routines for all platforms
  5  *
  6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
  7  *
  8  * Copyright (C) 2002 Intel Corporation.
  9  * Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com>
 10  * Copyright (C) 2003-2004 MontaVista Software, Inc.
 11  *
 12  * This program is free software; you can redistribute it and/or modify
 13  * it under the terms of the GNU General Public License version 2 as
 14  * published by the Free Software Foundation.
 15  *
 16  */
 17 
 18 #include <linux/sched.h>
 19 #include <linux/kernel.h>
 20 #include <linux/pci.h>
 21 #include <linux/interrupt.h>
 22 #include <linux/mm.h>
 23 #include <linux/init.h>
 24 #include <linux/ioport.h>
 25 #include <linux/slab.h>
 26 #include <linux/delay.h>
 27 #include <linux/device.h>
 28 #include <linux/io.h>
 29 #include <linux/export.h>
 30 #include <asm/dma-mapping.h>
 31 
 32 #include <asm/cputype.h>
 33 #include <asm/irq.h>
 34 #include <asm/sizes.h>
 35 #include <asm/mach/pci.h>
 36 #include <mach/hardware.h>
 37 
 38 
 39 /*
 40  * IXP4xx PCI read function is dependent on whether we are 
 41  * running A0 or B0 (AppleGate) silicon.
 42  */
 43 int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
 44 
 45 /*
 46  * Base address for PCI regsiter region
 47  */
 48 unsigned long ixp4xx_pci_reg_base = 0;
 49 
 50 /*
 51  * PCI cfg an I/O routines are done by programming a 
 52  * command/byte enable register, and then read/writing
 53  * the data from a data regsiter. We need to ensure
 54  * these transactions are atomic or we will end up
 55  * with corrupt data on the bus or in a driver.
 56  */
 57 static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock);
 58 
 59 /*
 60  * Read from PCI config space
 61  */
 62 static void crp_read(u32 ad_cbe, u32 *data)
 63 {
 64         unsigned long flags;
 65         raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
 66         *PCI_CRP_AD_CBE = ad_cbe;
 67         *data = *PCI_CRP_RDATA;
 68         raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
 69 }
 70 
 71 /*
 72  * Write to PCI config space
 73  */
 74 static void crp_write(u32 ad_cbe, u32 data)
 75 { 
 76         unsigned long flags;
 77         raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
 78         *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
 79         *PCI_CRP_WDATA = data;
 80         raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
 81 }
 82 
 83 static inline int check_master_abort(void)
 84 {
 85         /* check Master Abort bit after access */
 86         unsigned long isr = *PCI_ISR;
 87 
 88         if (isr & PCI_ISR_PFE) {
 89                 /* make sure the Master Abort bit is reset */    
 90                 *PCI_ISR = PCI_ISR_PFE;
 91                 pr_debug("%s failed\n", __func__);
 92                 return 1;
 93         }
 94 
 95         return 0;
 96 }
 97 
 98 int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
 99 {
100         unsigned long flags;
101         int retval = 0;
102         int i;
103 
104         raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
105 
106         *PCI_NP_AD = addr;
107 
108         /* 
109          * PCI workaround  - only works if NP PCI space reads have 
110          * no side effects!!! Read 8 times. last one will be good.
111          */
112         for (i = 0; i < 8; i++) {
113                 *PCI_NP_CBE = cmd;
114                 *data = *PCI_NP_RDATA;
115                 *data = *PCI_NP_RDATA;
116         }
117 
118         if(check_master_abort())
119                 retval = 1;
120 
121         raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
122         return retval;
123 }
124 
125 int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
126 {
127         unsigned long flags;
128         int retval = 0;
129 
130         raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
131 
132         *PCI_NP_AD = addr;
133 
134         /* set up and execute the read */    
135         *PCI_NP_CBE = cmd;
136 
137         /* the result of the read is now in NP_RDATA */
138         *data = *PCI_NP_RDATA; 
139 
140         if(check_master_abort())
141                 retval = 1;
142 
143         raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
144         return retval;
145 }
146 
147 int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
148 {    
149         unsigned long flags;
150         int retval = 0;
151 
152         raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
153 
154         *PCI_NP_AD = addr;
155 
156         /* set up the write */
157         *PCI_NP_CBE = cmd;
158 
159         /* execute the write by writing to NP_WDATA */
160         *PCI_NP_WDATA = data;
161 
162         if(check_master_abort())
163                 retval = 1;
164 
165         raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
166         return retval;
167 }
168 
169 static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
170 {
171         u32 addr;
172         if (!bus_num) {
173                 /* type 0 */
174                 addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) | 
175                     (where & ~3);       
176         } else {
177                 /* type 1 */
178                 addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) | 
179                         ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
180         }
181         return addr;
182 }
183 
184 /*
185  * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
186  * 0 and 3 are not valid indexes...
187  */
188 static u32 bytemask[] = {
189         /**/   0,
190         /*1*/   0xff,
191         /*2*/   0xffff,
192         /*3*/   0,
193         /*4*/   0xffffffff,
194 };
195 
196 static u32 local_byte_lane_enable_bits(u32 n, int size)
197 {
198         if (size == 1)
199                 return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
200         if (size == 2)
201                 return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
202         if (size == 4)
203                 return 0;
204         return 0xffffffff;
205 }
206 
207 static int local_read_config(int where, int size, u32 *value)
208 { 
209         u32 n, data;
210         pr_debug("local_read_config from %d size %d\n", where, size);
211         n = where % 4;
212         crp_read(where & ~3, &data);
213         *value = (data >> (8*n)) & bytemask[size];
214         pr_debug("local_read_config read %#x\n", *value);
215         return PCIBIOS_SUCCESSFUL;
216 }
217 
218 static int local_write_config(int where, int size, u32 value)
219 {
220         u32 n, byte_enables, data;
221         pr_debug("local_write_config %#x to %d size %d\n", value, where, size);
222         n = where % 4;
223         byte_enables = local_byte_lane_enable_bits(n, size);
224         if (byte_enables == 0xffffffff)
225                 return PCIBIOS_BAD_REGISTER_NUMBER;
226         data = value << (8*n);
227         crp_write((where & ~3) | byte_enables, data);
228         return PCIBIOS_SUCCESSFUL;
229 }
230 
231 static u32 byte_lane_enable_bits(u32 n, int size)
232 {
233         if (size == 1)
234                 return (0xf & ~BIT(n)) << 4;
235         if (size == 2)
236                 return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
237         if (size == 4)
238                 return 0;
239         return 0xffffffff;
240 }
241 
242 static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
243 {
244         u32 n, byte_enables, addr, data;
245         u8 bus_num = bus->number;
246 
247         pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
248                 bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
249 
250         *value = 0xffffffff;
251         n = where % 4;
252         byte_enables = byte_lane_enable_bits(n, size);
253         if (byte_enables == 0xffffffff)
254                 return PCIBIOS_BAD_REGISTER_NUMBER;
255 
256         addr = ixp4xx_config_addr(bus_num, devfn, where);
257         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data))
258                 return PCIBIOS_DEVICE_NOT_FOUND;
259 
260         *value = (data >> (8*n)) & bytemask[size];
261         pr_debug("read_config_byte read %#x\n", *value);
262         return PCIBIOS_SUCCESSFUL;
263 }
264 
265 static int ixp4xx_pci_write_config(struct pci_bus *bus,  unsigned int devfn, int where, int size, u32 value)
266 {
267         u32 n, byte_enables, addr, data;
268         u8 bus_num = bus->number;
269 
270         pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
271                 size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
272 
273         n = where % 4;
274         byte_enables = byte_lane_enable_bits(n, size);
275         if (byte_enables == 0xffffffff)
276                 return PCIBIOS_BAD_REGISTER_NUMBER;
277 
278         addr = ixp4xx_config_addr(bus_num, devfn, where);
279         data = value << (8*n);
280         if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data))
281                 return PCIBIOS_DEVICE_NOT_FOUND;
282 
283         return PCIBIOS_SUCCESSFUL;
284 }
285 
286 struct pci_ops ixp4xx_ops = {
287         .read =  ixp4xx_pci_read_config,
288         .write = ixp4xx_pci_write_config,
289 };
290 
291 /*
292  * PCI abort handler
293  */
294 static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
295 {
296         u32 isr, status;
297 
298         isr = *PCI_ISR;
299         local_read_config(PCI_STATUS, 2, &status);
300         pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, "
301                 "status = %#x\n", addr, isr, status);
302 
303         /* make sure the Master Abort bit is reset */    
304         *PCI_ISR = PCI_ISR_PFE;
305         status |= PCI_STATUS_REC_MASTER_ABORT;
306         local_write_config(PCI_STATUS, 2, status);
307 
308         /*
309          * If it was an imprecise abort, then we need to correct the
310          * return address to be _after_ the instruction.
311          */
312         if (fsr & (1 << 10))
313                 regs->ARM_pc += 4;
314 
315         return 0;
316 }
317 
318 
319 static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
320 {
321         return (dma_addr + size) >= SZ_64M;
322 }
323 
324 /*
325  * Setup DMA mask to 64MB on PCI devices. Ignore all other devices.
326  */
327 static int ixp4xx_pci_platform_notify(struct device *dev)
328 {
329         if(dev->bus == &pci_bus_type) {
330                 *dev->dma_mask =  SZ_64M - 1;
331                 dev->coherent_dma_mask = SZ_64M - 1;
332                 dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
333         }
334         return 0;
335 }
336 
337 static int ixp4xx_pci_platform_notify_remove(struct device *dev)
338 {
339         if(dev->bus == &pci_bus_type) {
340                 dmabounce_unregister_dev(dev);
341         }
342         return 0;
343 }
344 
345 void __init ixp4xx_pci_preinit(void)
346 {
347         unsigned long cpuid = read_cpuid_id();
348 
349 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
350         pcibios_min_mem = 0x10000000; /* 1 GB of indirect PCI MMIO space */
351 #else
352         pcibios_min_mem = 0x48000000; /* 64 MB of PCI MMIO space */
353 #endif
354         /*
355          * Determine which PCI read method to use.
356          * Rev 0 IXP425 requires workaround.
357          */
358         if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
359                 printk("PCI: IXP42x A0 silicon detected - "
360                         "PCI Non-Prefetch Workaround Enabled\n");
361                 ixp4xx_pci_read = ixp4xx_pci_read_errata;
362         } else
363                 ixp4xx_pci_read = ixp4xx_pci_read_no_errata;
364 
365 
366         /* hook in our fault handler for PCI errors */
367         hook_fault_code(16+6, abort_handler, SIGBUS, 0,
368                         "imprecise external abort");
369 
370         pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
371 
372         /*
373          * We use identity AHB->PCI address translation
374          * in the 0x48000000 to 0x4bffffff address space
375          */
376         *PCI_PCIMEMBASE = 0x48494A4B;
377 
378         /*
379          * We also use identity PCI->AHB address translation
380          * in 4 16MB BARs that begin at the physical memory start
381          */
382         *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
383                 ((PHYS_OFFSET & 0xFF000000) >> 8) +
384                 ((PHYS_OFFSET & 0xFF000000) >> 16) +
385                 ((PHYS_OFFSET & 0xFF000000) >> 24) +
386                 0x00010203;
387 
388         if (*PCI_CSR & PCI_CSR_HOST) {
389                 printk("PCI: IXP4xx is host\n");
390 
391                 pr_debug("setup BARs in controller\n");
392 
393                 /*
394                  * We configure the PCI inbound memory windows to be
395                  * 1:1 mapped to SDRAM
396                  */
397                 local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
398                 local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
399                 local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
400                 local_write_config(PCI_BASE_ADDRESS_3, 4,
401                                         PHYS_OFFSET + SZ_32M + SZ_16M);
402 
403                 /*
404                  * Enable CSR window at 64 MiB to allow PCI masters
405                  * to continue prefetching past 64 MiB boundary.
406                  */
407                 local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);
408 
409                 /*
410                  * Enable the IO window to be way up high, at 0xfffffc00
411                  */
412                 local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
413                 local_write_config(0x40, 4, 0x000080FF); /* No TRDY time limit */
414         } else {
415                 printk("PCI: IXP4xx is target - No bus scan performed\n");
416         }
417 
418         printk("PCI: IXP4xx Using %s access for memory space\n",
419 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
420                         "direct"
421 #else
422                         "indirect"
423 #endif
424                 );
425 
426         pr_debug("clear error bits in ISR\n");
427         *PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
428 
429         /*
430          * Set Initialize Complete in PCI Control Register: allow IXP4XX to
431          * respond to PCI configuration cycles. Specify that the AHB bus is
432          * operating in big endian mode. Set up byte lane swapping between 
433          * little-endian PCI and the big-endian AHB bus 
434          */
435 #ifdef __ARMEB__
436         *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
437 #else
438         *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE;
439 #endif
440 
441         pr_debug("DONE\n");
442 }
443 
444 int ixp4xx_setup(int nr, struct pci_sys_data *sys)
445 {
446         struct resource *res;
447 
448         if (nr >= 1)
449                 return 0;
450 
451         res = kzalloc(sizeof(*res) * 2, GFP_KERNEL);
452         if (res == NULL) {
453                 /* 
454                  * If we're out of memory this early, something is wrong,
455                  * so we might as well catch it here.
456                  */
457                 panic("PCI: unable to allocate resources?\n");
458         }
459 
460         local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
461 
462         res[0].name = "PCI I/O Space";
463         res[0].start = 0x00000000;
464         res[0].end = 0x0000ffff;
465         res[0].flags = IORESOURCE_IO;
466 
467         res[1].name = "PCI Memory Space";
468         res[1].start = PCIBIOS_MIN_MEM;
469         res[1].end = PCIBIOS_MAX_MEM;
470         res[1].flags = IORESOURCE_MEM;
471 
472         request_resource(&ioport_resource, &res[0]);
473         request_resource(&iomem_resource, &res[1]);
474 
475         pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
476         pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
477 
478         platform_notify = ixp4xx_pci_platform_notify;
479         platform_notify_remove = ixp4xx_pci_platform_notify_remove;
480 
481         return 1;
482 }
483 
484 int dma_set_coherent_mask(struct device *dev, u64 mask)
485 {
486         if (mask >= SZ_64M - 1)
487                 return 0;
488 
489         return -EIO;
490 }
491 
492 EXPORT_SYMBOL(ixp4xx_pci_read);
493 EXPORT_SYMBOL(ixp4xx_pci_write);
494 EXPORT_SYMBOL(dma_set_coherent_mask);
495 

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