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Linux/arch/arm/mach-ixp4xx/common-pci.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  * arch/arm/mach-ixp4xx/common-pci.c 
  4  *
  5  * IXP4XX PCI routines for all platforms
  6  *
  7  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
  8  *
  9  * Copyright (C) 2002 Intel Corporation.
 10  * Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com>
 11  * Copyright (C) 2003-2004 MontaVista Software, Inc.
 12  */
 13 
 14 #include <linux/sched.h>
 15 #include <linux/kernel.h>
 16 #include <linux/pci.h>
 17 #include <linux/interrupt.h>
 18 #include <linux/mm.h>
 19 #include <linux/init.h>
 20 #include <linux/ioport.h>
 21 #include <linux/slab.h>
 22 #include <linux/delay.h>
 23 #include <linux/device.h>
 24 #include <linux/io.h>
 25 #include <linux/export.h>
 26 #include <asm/dma-mapping.h>
 27 
 28 #include <asm/cputype.h>
 29 #include <asm/irq.h>
 30 #include <linux/sizes.h>
 31 #include <asm/mach/pci.h>
 32 #include <mach/hardware.h>
 33 
 34 
 35 /*
 36  * IXP4xx PCI read function is dependent on whether we are 
 37  * running A0 or B0 (AppleGate) silicon.
 38  */
 39 int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
 40 
 41 /*
 42  * Base address for PCI register region
 43  */
 44 unsigned long ixp4xx_pci_reg_base = 0;
 45 
 46 /*
 47  * PCI cfg an I/O routines are done by programming a 
 48  * command/byte enable register, and then read/writing
 49  * the data from a data register. We need to ensure
 50  * these transactions are atomic or we will end up
 51  * with corrupt data on the bus or in a driver.
 52  */
 53 static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock);
 54 
 55 /*
 56  * Read from PCI config space
 57  */
 58 static void crp_read(u32 ad_cbe, u32 *data)
 59 {
 60         unsigned long flags;
 61         raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
 62         *PCI_CRP_AD_CBE = ad_cbe;
 63         *data = *PCI_CRP_RDATA;
 64         raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
 65 }
 66 
 67 /*
 68  * Write to PCI config space
 69  */
 70 static void crp_write(u32 ad_cbe, u32 data)
 71 { 
 72         unsigned long flags;
 73         raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
 74         *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
 75         *PCI_CRP_WDATA = data;
 76         raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
 77 }
 78 
 79 static inline int check_master_abort(void)
 80 {
 81         /* check Master Abort bit after access */
 82         unsigned long isr = *PCI_ISR;
 83 
 84         if (isr & PCI_ISR_PFE) {
 85                 /* make sure the Master Abort bit is reset */    
 86                 *PCI_ISR = PCI_ISR_PFE;
 87                 pr_debug("%s failed\n", __func__);
 88                 return 1;
 89         }
 90 
 91         return 0;
 92 }
 93 
 94 int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
 95 {
 96         unsigned long flags;
 97         int retval = 0;
 98         int i;
 99 
100         raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
101 
102         *PCI_NP_AD = addr;
103 
104         /* 
105          * PCI workaround  - only works if NP PCI space reads have 
106          * no side effects!!! Read 8 times. last one will be good.
107          */
108         for (i = 0; i < 8; i++) {
109                 *PCI_NP_CBE = cmd;
110                 *data = *PCI_NP_RDATA;
111                 *data = *PCI_NP_RDATA;
112         }
113 
114         if(check_master_abort())
115                 retval = 1;
116 
117         raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
118         return retval;
119 }
120 
121 int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
122 {
123         unsigned long flags;
124         int retval = 0;
125 
126         raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
127 
128         *PCI_NP_AD = addr;
129 
130         /* set up and execute the read */    
131         *PCI_NP_CBE = cmd;
132 
133         /* the result of the read is now in NP_RDATA */
134         *data = *PCI_NP_RDATA; 
135 
136         if(check_master_abort())
137                 retval = 1;
138 
139         raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
140         return retval;
141 }
142 
143 int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
144 {    
145         unsigned long flags;
146         int retval = 0;
147 
148         raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
149 
150         *PCI_NP_AD = addr;
151 
152         /* set up the write */
153         *PCI_NP_CBE = cmd;
154 
155         /* execute the write by writing to NP_WDATA */
156         *PCI_NP_WDATA = data;
157 
158         if(check_master_abort())
159                 retval = 1;
160 
161         raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
162         return retval;
163 }
164 
165 static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
166 {
167         u32 addr;
168         if (!bus_num) {
169                 /* type 0 */
170                 addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) | 
171                     (where & ~3);       
172         } else {
173                 /* type 1 */
174                 addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) | 
175                         ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
176         }
177         return addr;
178 }
179 
180 /*
181  * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
182  * 0 and 3 are not valid indexes...
183  */
184 static u32 bytemask[] = {
185         /**/   0,
186         /*1*/   0xff,
187         /*2*/   0xffff,
188         /*3*/   0,
189         /*4*/   0xffffffff,
190 };
191 
192 static u32 local_byte_lane_enable_bits(u32 n, int size)
193 {
194         if (size == 1)
195                 return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
196         if (size == 2)
197                 return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
198         if (size == 4)
199                 return 0;
200         return 0xffffffff;
201 }
202 
203 static int local_read_config(int where, int size, u32 *value)
204 { 
205         u32 n, data;
206         pr_debug("local_read_config from %d size %d\n", where, size);
207         n = where % 4;
208         crp_read(where & ~3, &data);
209         *value = (data >> (8*n)) & bytemask[size];
210         pr_debug("local_read_config read %#x\n", *value);
211         return PCIBIOS_SUCCESSFUL;
212 }
213 
214 static int local_write_config(int where, int size, u32 value)
215 {
216         u32 n, byte_enables, data;
217         pr_debug("local_write_config %#x to %d size %d\n", value, where, size);
218         n = where % 4;
219         byte_enables = local_byte_lane_enable_bits(n, size);
220         if (byte_enables == 0xffffffff)
221                 return PCIBIOS_BAD_REGISTER_NUMBER;
222         data = value << (8*n);
223         crp_write((where & ~3) | byte_enables, data);
224         return PCIBIOS_SUCCESSFUL;
225 }
226 
227 static u32 byte_lane_enable_bits(u32 n, int size)
228 {
229         if (size == 1)
230                 return (0xf & ~BIT(n)) << 4;
231         if (size == 2)
232                 return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
233         if (size == 4)
234                 return 0;
235         return 0xffffffff;
236 }
237 
238 static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
239 {
240         u32 n, byte_enables, addr, data;
241         u8 bus_num = bus->number;
242 
243         pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
244                 bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
245 
246         *value = 0xffffffff;
247         n = where % 4;
248         byte_enables = byte_lane_enable_bits(n, size);
249         if (byte_enables == 0xffffffff)
250                 return PCIBIOS_BAD_REGISTER_NUMBER;
251 
252         addr = ixp4xx_config_addr(bus_num, devfn, where);
253         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data))
254                 return PCIBIOS_DEVICE_NOT_FOUND;
255 
256         *value = (data >> (8*n)) & bytemask[size];
257         pr_debug("read_config_byte read %#x\n", *value);
258         return PCIBIOS_SUCCESSFUL;
259 }
260 
261 static int ixp4xx_pci_write_config(struct pci_bus *bus,  unsigned int devfn, int where, int size, u32 value)
262 {
263         u32 n, byte_enables, addr, data;
264         u8 bus_num = bus->number;
265 
266         pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
267                 size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
268 
269         n = where % 4;
270         byte_enables = byte_lane_enable_bits(n, size);
271         if (byte_enables == 0xffffffff)
272                 return PCIBIOS_BAD_REGISTER_NUMBER;
273 
274         addr = ixp4xx_config_addr(bus_num, devfn, where);
275         data = value << (8*n);
276         if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data))
277                 return PCIBIOS_DEVICE_NOT_FOUND;
278 
279         return PCIBIOS_SUCCESSFUL;
280 }
281 
282 struct pci_ops ixp4xx_ops = {
283         .read =  ixp4xx_pci_read_config,
284         .write = ixp4xx_pci_write_config,
285 };
286 
287 /*
288  * PCI abort handler
289  */
290 static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
291 {
292         u32 isr, status;
293 
294         isr = *PCI_ISR;
295         local_read_config(PCI_STATUS, 2, &status);
296         pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, "
297                 "status = %#x\n", addr, isr, status);
298 
299         /* make sure the Master Abort bit is reset */    
300         *PCI_ISR = PCI_ISR_PFE;
301         status |= PCI_STATUS_REC_MASTER_ABORT;
302         local_write_config(PCI_STATUS, 2, status);
303 
304         /*
305          * If it was an imprecise abort, then we need to correct the
306          * return address to be _after_ the instruction.
307          */
308         if (fsr & (1 << 10))
309                 regs->ARM_pc += 4;
310 
311         return 0;
312 }
313 
314 void __init ixp4xx_pci_preinit(void)
315 {
316         unsigned long cpuid = read_cpuid_id();
317 
318 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
319         pcibios_min_mem = 0x10000000; /* 1 GB of indirect PCI MMIO space */
320 #else
321         pcibios_min_mem = 0x48000000; /* 64 MB of PCI MMIO space */
322 #endif
323         /*
324          * Determine which PCI read method to use.
325          * Rev 0 IXP425 requires workaround.
326          */
327         if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
328                 printk("PCI: IXP42x A0 silicon detected - "
329                         "PCI Non-Prefetch Workaround Enabled\n");
330                 ixp4xx_pci_read = ixp4xx_pci_read_errata;
331         } else
332                 ixp4xx_pci_read = ixp4xx_pci_read_no_errata;
333 
334 
335         /* hook in our fault handler for PCI errors */
336         hook_fault_code(16+6, abort_handler, SIGBUS, 0,
337                         "imprecise external abort");
338 
339         pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
340 
341         /*
342          * We use identity AHB->PCI address translation
343          * in the 0x48000000 to 0x4bffffff address space
344          */
345         *PCI_PCIMEMBASE = 0x48494A4B;
346 
347         /*
348          * We also use identity PCI->AHB address translation
349          * in 4 16MB BARs that begin at the physical memory start
350          */
351         *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
352                 ((PHYS_OFFSET & 0xFF000000) >> 8) +
353                 ((PHYS_OFFSET & 0xFF000000) >> 16) +
354                 ((PHYS_OFFSET & 0xFF000000) >> 24) +
355                 0x00010203;
356 
357         if (*PCI_CSR & PCI_CSR_HOST) {
358                 printk("PCI: IXP4xx is host\n");
359 
360                 pr_debug("setup BARs in controller\n");
361 
362                 /*
363                  * We configure the PCI inbound memory windows to be
364                  * 1:1 mapped to SDRAM
365                  */
366                 local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
367                 local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
368                 local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
369                 local_write_config(PCI_BASE_ADDRESS_3, 4,
370                                         PHYS_OFFSET + SZ_32M + SZ_16M);
371 
372                 /*
373                  * Enable CSR window at 64 MiB to allow PCI masters
374                  * to continue prefetching past 64 MiB boundary.
375                  */
376                 local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);
377 
378                 /*
379                  * Enable the IO window to be way up high, at 0xfffffc00
380                  */
381                 local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
382                 local_write_config(0x40, 4, 0x000080FF); /* No TRDY time limit */
383         } else {
384                 printk("PCI: IXP4xx is target - No bus scan performed\n");
385         }
386 
387         printk("PCI: IXP4xx Using %s access for memory space\n",
388 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
389                         "direct"
390 #else
391                         "indirect"
392 #endif
393                 );
394 
395         pr_debug("clear error bits in ISR\n");
396         *PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
397 
398         /*
399          * Set Initialize Complete in PCI Control Register: allow IXP4XX to
400          * respond to PCI configuration cycles. Specify that the AHB bus is
401          * operating in big endian mode. Set up byte lane swapping between 
402          * little-endian PCI and the big-endian AHB bus 
403          */
404 #ifdef __ARMEB__
405         *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
406 #else
407         *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE;
408 #endif
409 
410         pr_debug("DONE\n");
411 }
412 
413 int ixp4xx_setup(int nr, struct pci_sys_data *sys)
414 {
415         struct resource *res;
416 
417         if (nr >= 1)
418                 return 0;
419 
420         res = kcalloc(2, sizeof(*res), GFP_KERNEL);
421         if (res == NULL) {
422                 /* 
423                  * If we're out of memory this early, something is wrong,
424                  * so we might as well catch it here.
425                  */
426                 panic("PCI: unable to allocate resources?\n");
427         }
428 
429         local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
430 
431         res[0].name = "PCI I/O Space";
432         res[0].start = 0x00000000;
433         res[0].end = 0x0000ffff;
434         res[0].flags = IORESOURCE_IO;
435 
436         res[1].name = "PCI Memory Space";
437         res[1].start = PCIBIOS_MIN_MEM;
438         res[1].end = PCIBIOS_MAX_MEM;
439         res[1].flags = IORESOURCE_MEM;
440 
441         request_resource(&ioport_resource, &res[0]);
442         request_resource(&iomem_resource, &res[1]);
443 
444         pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
445         pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
446 
447         return 1;
448 }
449 
450 EXPORT_SYMBOL(ixp4xx_pci_read);
451 EXPORT_SYMBOL(ixp4xx_pci_write);
452 

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