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Linux/arch/arm/mach-mmp/mmp2.c

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  1 /*
  2  * linux/arch/arm/mach-mmp/mmp2.c
  3  *
  4  * code name MMP2
  5  *
  6  * Copyright (C) 2009 Marvell International Ltd.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License version 2 as
 10  * published by the Free Software Foundation.
 11  */
 12 #include <linux/clk/mmp.h>
 13 #include <linux/module.h>
 14 #include <linux/kernel.h>
 15 #include <linux/init.h>
 16 #include <linux/io.h>
 17 #include <linux/irq.h>
 18 #include <linux/irqchip/mmp.h>
 19 #include <linux/platform_device.h>
 20 
 21 #include <asm/hardware/cache-tauros2.h>
 22 
 23 #include <asm/mach/time.h>
 24 #include "addr-map.h"
 25 #include "regs-apbc.h"
 26 #include "cputype.h"
 27 #include "irqs.h"
 28 #include "mfp.h"
 29 #include "devices.h"
 30 #include "mmp2.h"
 31 #include "pm-mmp2.h"
 32 
 33 #include "common.h"
 34 
 35 #define MFPR_VIRT_BASE  (APB_VIRT_BASE + 0x1e000)
 36 
 37 static struct mfp_addr_map mmp2_addr_map[] __initdata = {
 38 
 39         MFP_ADDR_X(GPIO0, GPIO58, 0x54),
 40         MFP_ADDR_X(GPIO59, GPIO73, 0x280),
 41         MFP_ADDR_X(GPIO74, GPIO101, 0x170),
 42 
 43         MFP_ADDR(GPIO102, 0x0),
 44         MFP_ADDR(GPIO103, 0x4),
 45         MFP_ADDR(GPIO104, 0x1fc),
 46         MFP_ADDR(GPIO105, 0x1f8),
 47         MFP_ADDR(GPIO106, 0x1f4),
 48         MFP_ADDR(GPIO107, 0x1f0),
 49         MFP_ADDR(GPIO108, 0x21c),
 50         MFP_ADDR(GPIO109, 0x218),
 51         MFP_ADDR(GPIO110, 0x214),
 52         MFP_ADDR(GPIO111, 0x200),
 53         MFP_ADDR(GPIO112, 0x244),
 54         MFP_ADDR(GPIO113, 0x25c),
 55         MFP_ADDR(GPIO114, 0x164),
 56         MFP_ADDR_X(GPIO115, GPIO122, 0x260),
 57 
 58         MFP_ADDR(GPIO123, 0x148),
 59         MFP_ADDR_X(GPIO124, GPIO141, 0xc),
 60 
 61         MFP_ADDR(GPIO142, 0x8),
 62         MFP_ADDR_X(GPIO143, GPIO151, 0x220),
 63         MFP_ADDR_X(GPIO152, GPIO153, 0x248),
 64         MFP_ADDR_X(GPIO154, GPIO155, 0x254),
 65         MFP_ADDR_X(GPIO156, GPIO159, 0x14c),
 66 
 67         MFP_ADDR(GPIO160, 0x250),
 68         MFP_ADDR(GPIO161, 0x210),
 69         MFP_ADDR(GPIO162, 0x20c),
 70         MFP_ADDR(GPIO163, 0x208),
 71         MFP_ADDR(GPIO164, 0x204),
 72         MFP_ADDR(GPIO165, 0x1ec),
 73         MFP_ADDR(GPIO166, 0x1e8),
 74         MFP_ADDR(GPIO167, 0x1e4),
 75         MFP_ADDR(GPIO168, 0x1e0),
 76 
 77         MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140),
 78         MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc),
 79 
 80         MFP_ADDR(PMIC_INT, 0x2c4),
 81         MFP_ADDR(CLK_REQ, 0x160),
 82 
 83         MFP_ADDR_END,
 84 };
 85 
 86 void mmp2_clear_pmic_int(void)
 87 {
 88         void __iomem *mfpr_pmic;
 89         unsigned long data;
 90 
 91         mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4;
 92         data = __raw_readl(mfpr_pmic);
 93         __raw_writel(data | (1 << 6), mfpr_pmic);
 94         __raw_writel(data, mfpr_pmic);
 95 }
 96 
 97 void __init mmp2_init_irq(void)
 98 {
 99         mmp2_init_icu();
100 #ifdef CONFIG_PM
101         icu_irq_chip.irq_set_wake = mmp2_set_wake;
102 #endif
103 }
104 
105 static int __init mmp2_init(void)
106 {
107         if (cpu_is_mmp2()) {
108 #ifdef CONFIG_CACHE_TAUROS2
109                 tauros2_init(0);
110 #endif
111                 mfp_init_base(MFPR_VIRT_BASE);
112                 mfp_init_addr(mmp2_addr_map);
113                 mmp2_clk_init(APB_PHYS_BASE + 0x50000,
114                               AXI_PHYS_BASE + 0x82800,
115                               APB_PHYS_BASE + 0x15000);
116         }
117 
118         return 0;
119 }
120 postcore_initcall(mmp2_init);
121 
122 #define APBC_TIMERS     APBC_REG(0x024)
123 
124 void __init mmp2_timer_init(void)
125 {
126         unsigned long clk_rst;
127 
128         __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
129 
130         /*
131          * enable bus/functional clock, enable 6.5MHz (divider 4),
132          * release reset
133          */
134         clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
135         __raw_writel(clk_rst, APBC_TIMERS);
136 
137         timer_init(IRQ_MMP2_TIMER1);
138 }
139 
140 /* on-chip devices */
141 MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5);
142 MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21);
143 MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23);
144 MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19);
145 MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70);
146 MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70);
147 MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70);
148 MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
149 MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
150 MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
151 MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
152 MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120);
153 MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120);
154 MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120);
155 MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120);
156 MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000);
157 /* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */
158 MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000);
159 
160 struct resource mmp2_resource_gpio[] = {
161         {
162                 .start  = 0xd4019000,
163                 .end    = 0xd4019fff,
164                 .flags  = IORESOURCE_MEM,
165         }, {
166                 .start  = IRQ_MMP2_GPIO,
167                 .end    = IRQ_MMP2_GPIO,
168                 .name   = "gpio_mux",
169                 .flags  = IORESOURCE_IRQ,
170         },
171 };
172 
173 struct platform_device mmp2_device_gpio = {
174         .name           = "mmp2-gpio",
175         .id             = -1,
176         .num_resources  = ARRAY_SIZE(mmp2_resource_gpio),
177         .resource       = mmp2_resource_gpio,
178 };
179 

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