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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-msm/timer.c

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  1 /*
  2  *
  3  * Copyright (C) 2007 Google, Inc.
  4  * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
  5  *
  6  * This software is licensed under the terms of the GNU General Public
  7  * License version 2, as published by the Free Software Foundation, and
  8  * may be copied, distributed, and modified under those terms.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  *
 15  */
 16 
 17 #include <linux/clocksource.h>
 18 #include <linux/clockchips.h>
 19 #include <linux/init.h>
 20 #include <linux/interrupt.h>
 21 #include <linux/irq.h>
 22 #include <linux/io.h>
 23 #include <linux/of.h>
 24 #include <linux/of_address.h>
 25 #include <linux/of_irq.h>
 26 
 27 #include <asm/mach/time.h>
 28 #include <asm/localtimer.h>
 29 #include <asm/sched_clock.h>
 30 
 31 #include "common.h"
 32 
 33 #define TIMER_MATCH_VAL         0x0000
 34 #define TIMER_COUNT_VAL         0x0004
 35 #define TIMER_ENABLE            0x0008
 36 #define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
 37 #define TIMER_ENABLE_EN                 BIT(0)
 38 #define TIMER_CLEAR             0x000C
 39 #define DGT_CLK_CTL_DIV_4       0x3
 40 
 41 #define GPT_HZ 32768
 42 
 43 #define MSM_DGT_SHIFT 5
 44 
 45 static void __iomem *event_base;
 46 
 47 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
 48 {
 49         struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
 50         /* Stop the timer tick */
 51         if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
 52                 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
 53                 ctrl &= ~TIMER_ENABLE_EN;
 54                 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
 55         }
 56         evt->event_handler(evt);
 57         return IRQ_HANDLED;
 58 }
 59 
 60 static int msm_timer_set_next_event(unsigned long cycles,
 61                                     struct clock_event_device *evt)
 62 {
 63         u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
 64 
 65         ctrl &= ~TIMER_ENABLE_EN;
 66         writel_relaxed(ctrl, event_base + TIMER_ENABLE);
 67 
 68         writel_relaxed(ctrl, event_base + TIMER_CLEAR);
 69         writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
 70         writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
 71         return 0;
 72 }
 73 
 74 static void msm_timer_set_mode(enum clock_event_mode mode,
 75                               struct clock_event_device *evt)
 76 {
 77         u32 ctrl;
 78 
 79         ctrl = readl_relaxed(event_base + TIMER_ENABLE);
 80         ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
 81 
 82         switch (mode) {
 83         case CLOCK_EVT_MODE_RESUME:
 84         case CLOCK_EVT_MODE_PERIODIC:
 85                 break;
 86         case CLOCK_EVT_MODE_ONESHOT:
 87                 /* Timer is enabled in set_next_event */
 88                 break;
 89         case CLOCK_EVT_MODE_UNUSED:
 90         case CLOCK_EVT_MODE_SHUTDOWN:
 91                 break;
 92         }
 93         writel_relaxed(ctrl, event_base + TIMER_ENABLE);
 94 }
 95 
 96 static struct clock_event_device msm_clockevent = {
 97         .name           = "gp_timer",
 98         .features       = CLOCK_EVT_FEAT_ONESHOT,
 99         .rating         = 200,
100         .set_next_event = msm_timer_set_next_event,
101         .set_mode       = msm_timer_set_mode,
102 };
103 
104 static union {
105         struct clock_event_device *evt;
106         struct clock_event_device * __percpu *percpu_evt;
107 } msm_evt;
108 
109 static void __iomem *source_base;
110 
111 static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
112 {
113         return readl_relaxed(source_base + TIMER_COUNT_VAL);
114 }
115 
116 static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
117 {
118         /*
119          * Shift timer count down by a constant due to unreliable lower bits
120          * on some targets.
121          */
122         return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
123 }
124 
125 static struct clocksource msm_clocksource = {
126         .name   = "dg_timer",
127         .rating = 300,
128         .read   = msm_read_timer_count,
129         .mask   = CLOCKSOURCE_MASK(32),
130         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
131 };
132 
133 #ifdef CONFIG_LOCAL_TIMERS
134 static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
135 {
136         /* Use existing clock_event for cpu 0 */
137         if (!smp_processor_id())
138                 return 0;
139 
140         writel_relaxed(0, event_base + TIMER_ENABLE);
141         writel_relaxed(0, event_base + TIMER_CLEAR);
142         writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
143         evt->irq = msm_clockevent.irq;
144         evt->name = "local_timer";
145         evt->features = msm_clockevent.features;
146         evt->rating = msm_clockevent.rating;
147         evt->set_mode = msm_timer_set_mode;
148         evt->set_next_event = msm_timer_set_next_event;
149 
150         *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
151         clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
152         enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
153         return 0;
154 }
155 
156 static void msm_local_timer_stop(struct clock_event_device *evt)
157 {
158         evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
159         disable_percpu_irq(evt->irq);
160 }
161 
162 static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
163         .setup  = msm_local_timer_setup,
164         .stop   = msm_local_timer_stop,
165 };
166 #endif /* CONFIG_LOCAL_TIMERS */
167 
168 static notrace u32 msm_sched_clock_read(void)
169 {
170         return msm_clocksource.read(&msm_clocksource);
171 }
172 
173 static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
174                                   bool percpu)
175 {
176         struct clock_event_device *ce = &msm_clockevent;
177         struct clocksource *cs = &msm_clocksource;
178         int res;
179 
180         writel_relaxed(0, event_base + TIMER_ENABLE);
181         writel_relaxed(0, event_base + TIMER_CLEAR);
182         writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
183         ce->cpumask = cpumask_of(0);
184         ce->irq = irq;
185 
186         clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
187         if (percpu) {
188                 msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
189                 if (!msm_evt.percpu_evt) {
190                         pr_err("memory allocation failed for %s\n", ce->name);
191                         goto err;
192                 }
193                 *__this_cpu_ptr(msm_evt.percpu_evt) = ce;
194                 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
195                                          ce->name, msm_evt.percpu_evt);
196                 if (!res) {
197                         enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
198 #ifdef CONFIG_LOCAL_TIMERS
199                         local_timer_register(&msm_local_timer_ops);
200 #endif
201                 }
202         } else {
203                 msm_evt.evt = ce;
204                 res = request_irq(ce->irq, msm_timer_interrupt,
205                                   IRQF_TIMER | IRQF_NOBALANCING |
206                                   IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
207         }
208 
209         if (res)
210                 pr_err("request_irq failed for %s\n", ce->name);
211 err:
212         writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
213         res = clocksource_register_hz(cs, dgt_hz);
214         if (res)
215                 pr_err("clocksource_register failed\n");
216         setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
217 }
218 
219 #ifdef CONFIG_OF
220 static const struct of_device_id msm_dgt_match[] __initconst = {
221         { .compatible = "qcom,msm-dgt" },
222         { },
223 };
224 
225 static const struct of_device_id msm_gpt_match[] __initconst = {
226         { .compatible = "qcom,msm-gpt" },
227         { },
228 };
229 
230 void __init msm_dt_timer_init(void)
231 {
232         struct device_node *np;
233         u32 freq;
234         int irq;
235         struct resource res;
236         u32 percpu_offset;
237         void __iomem *dgt_clk_ctl;
238 
239         np = of_find_matching_node(NULL, msm_gpt_match);
240         if (!np) {
241                 pr_err("Can't find GPT DT node\n");
242                 return;
243         }
244 
245         event_base = of_iomap(np, 0);
246         if (!event_base) {
247                 pr_err("Failed to map event base\n");
248                 return;
249         }
250 
251         irq = irq_of_parse_and_map(np, 0);
252         if (irq <= 0) {
253                 pr_err("Can't get irq\n");
254                 return;
255         }
256         of_node_put(np);
257 
258         np = of_find_matching_node(NULL, msm_dgt_match);
259         if (!np) {
260                 pr_err("Can't find DGT DT node\n");
261                 return;
262         }
263 
264         if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
265                 percpu_offset = 0;
266 
267         if (of_address_to_resource(np, 0, &res)) {
268                 pr_err("Failed to parse DGT resource\n");
269                 return;
270         }
271 
272         source_base = ioremap(res.start + percpu_offset, resource_size(&res));
273         if (!source_base) {
274                 pr_err("Failed to map source base\n");
275                 return;
276         }
277 
278         if (!of_address_to_resource(np, 1, &res)) {
279                 dgt_clk_ctl = ioremap(res.start + percpu_offset,
280                                       resource_size(&res));
281                 if (!dgt_clk_ctl) {
282                         pr_err("Failed to map DGT control base\n");
283                         return;
284                 }
285                 writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
286                 iounmap(dgt_clk_ctl);
287         }
288 
289         if (of_property_read_u32(np, "clock-frequency", &freq)) {
290                 pr_err("Unknown frequency\n");
291                 return;
292         }
293         of_node_put(np);
294 
295         msm_timer_init(freq, 32, irq, !!percpu_offset);
296 }
297 #endif
298 
299 static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
300 {
301         event_base = ioremap(event, SZ_64);
302         if (!event_base) {
303                 pr_err("Failed to map event base\n");
304                 return 1;
305         }
306         source_base = ioremap(source, SZ_64);
307         if (!source_base) {
308                 pr_err("Failed to map source base\n");
309                 return 1;
310         }
311         return 0;
312 }
313 
314 void __init msm7x01_timer_init(void)
315 {
316         struct clocksource *cs = &msm_clocksource;
317 
318         if (msm_timer_map(0xc0100000, 0xc0100010))
319                 return;
320         cs->read = msm_read_timer_count_shift;
321         cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
322         /* 600 KHz */
323         msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
324                         false);
325 }
326 
327 void __init msm7x30_timer_init(void)
328 {
329         if (msm_timer_map(0xc0100004, 0xc0100024))
330                 return;
331         msm_timer_init(24576000 / 4, 32, 1, false);
332 }
333 
334 void __init qsd8x50_timer_init(void)
335 {
336         if (msm_timer_map(0xAC100000, 0xAC100010))
337                 return;
338         msm_timer_init(19200000 / 4, 32, 7, false);
339 }
340 

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