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Linux/arch/arm/mach-mv78xx0/common.c

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  1 /*
  2  * arch/arm/mach-mv78xx0/common.c
  3  *
  4  * Core functions for Marvell MV78xx0 SoCs
  5  *
  6  * This file is licensed under the terms of the GNU General Public
  7  * License version 2.  This program is licensed "as is" without any
  8  * warranty of any kind, whether express or implied.
  9  */
 10 
 11 #include <linux/kernel.h>
 12 #include <linux/init.h>
 13 #include <linux/platform_device.h>
 14 #include <linux/serial_8250.h>
 15 #include <linux/ata_platform.h>
 16 #include <linux/clk-provider.h>
 17 #include <linux/ethtool.h>
 18 #include <asm/hardware/cache-feroceon-l2.h>
 19 #include <asm/mach/map.h>
 20 #include <asm/mach/time.h>
 21 #include <linux/platform_data/usb-ehci-orion.h>
 22 #include <linux/platform_data/mtd-orion_nand.h>
 23 #include <plat/time.h>
 24 #include <plat/common.h>
 25 #include <plat/addr-map.h>
 26 #include "mv78xx0.h"
 27 #include "bridge-regs.h"
 28 #include "common.h"
 29 
 30 static int get_tclk(void);
 31 
 32 /*****************************************************************************
 33  * Common bits
 34  ****************************************************************************/
 35 int mv78xx0_core_index(void)
 36 {
 37         u32 extra;
 38 
 39         /*
 40          * Read Extra Features register.
 41          */
 42         __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
 43 
 44         return !!(extra & 0x00004000);
 45 }
 46 
 47 static int get_hclk(void)
 48 {
 49         int hclk;
 50 
 51         /*
 52          * HCLK tick rate is configured by DEV_D[7:5] pins.
 53          */
 54         switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
 55         case 0:
 56                 hclk = 166666667;
 57                 break;
 58         case 1:
 59                 hclk = 200000000;
 60                 break;
 61         case 2:
 62                 hclk = 266666667;
 63                 break;
 64         case 3:
 65                 hclk = 333333333;
 66                 break;
 67         case 4:
 68                 hclk = 400000000;
 69                 break;
 70         default:
 71                 panic("unknown HCLK PLL setting: %.8x\n",
 72                         readl(SAMPLE_AT_RESET_LOW));
 73         }
 74 
 75         return hclk;
 76 }
 77 
 78 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
 79 {
 80         u32 cfg;
 81 
 82         /*
 83          * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
 84          * PCLK/L2CLK by bits [19:14].
 85          */
 86         if (core_index == 0) {
 87                 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
 88         } else {
 89                 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
 90         }
 91 
 92         /*
 93          * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
 94          * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
 95          */
 96         *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
 97 
 98         /*
 99          * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
100          * ratio (1, 2, 3).
101          */
102         *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
103 }
104 
105 static int get_tclk(void)
106 {
107         int tclk_freq;
108 
109         /*
110          * TCLK tick rate is configured by DEV_A[2:0] strap pins.
111          */
112         switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
113         case 1:
114                 tclk_freq = 166666667;
115                 break;
116         case 3:
117                 tclk_freq = 200000000;
118                 break;
119         default:
120                 panic("unknown TCLK PLL setting: %.8x\n",
121                         readl(SAMPLE_AT_RESET_HIGH));
122         }
123 
124         return tclk_freq;
125 }
126 
127 
128 /*****************************************************************************
129  * I/O Address Mapping
130  ****************************************************************************/
131 static struct map_desc mv78xx0_io_desc[] __initdata = {
132         {
133                 .virtual        = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
134                 .pfn            = 0,
135                 .length         = MV78XX0_CORE_REGS_SIZE,
136                 .type           = MT_DEVICE,
137         }, {
138                 .virtual        = (unsigned long) MV78XX0_REGS_VIRT_BASE,
139                 .pfn            = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
140                 .length         = MV78XX0_REGS_SIZE,
141                 .type           = MT_DEVICE,
142         },
143 };
144 
145 void __init mv78xx0_map_io(void)
146 {
147         unsigned long phys;
148 
149         /*
150          * Map the right set of per-core registers depending on
151          * which core we are running on.
152          */
153         if (mv78xx0_core_index() == 0) {
154                 phys = MV78XX0_CORE0_REGS_PHYS_BASE;
155         } else {
156                 phys = MV78XX0_CORE1_REGS_PHYS_BASE;
157         }
158         mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
159 
160         iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
161 }
162 
163 
164 /*****************************************************************************
165  * CLK tree
166  ****************************************************************************/
167 static struct clk *tclk;
168 
169 static void __init clk_init(void)
170 {
171         tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, get_tclk());
172 
173         orion_clkdev_init(tclk);
174 }
175 
176 /*****************************************************************************
177  * EHCI
178  ****************************************************************************/
179 void __init mv78xx0_ehci0_init(void)
180 {
181         orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
182 }
183 
184 
185 /*****************************************************************************
186  * EHCI1
187  ****************************************************************************/
188 void __init mv78xx0_ehci1_init(void)
189 {
190         orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
191 }
192 
193 
194 /*****************************************************************************
195  * EHCI2
196  ****************************************************************************/
197 void __init mv78xx0_ehci2_init(void)
198 {
199         orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
200 }
201 
202 
203 /*****************************************************************************
204  * GE00
205  ****************************************************************************/
206 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
207 {
208         orion_ge00_init(eth_data,
209                         GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
210                         IRQ_MV78XX0_GE_ERR,
211                         MV643XX_TX_CSUM_DEFAULT_LIMIT);
212 }
213 
214 
215 /*****************************************************************************
216  * GE01
217  ****************************************************************************/
218 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
219 {
220         orion_ge01_init(eth_data,
221                         GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
222                         MV643XX_TX_CSUM_DEFAULT_LIMIT);
223 }
224 
225 
226 /*****************************************************************************
227  * GE10
228  ****************************************************************************/
229 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
230 {
231         u32 dev, rev;
232 
233         /*
234          * On the Z0, ge10 and ge11 are internally connected back
235          * to back, and not brought out.
236          */
237         mv78xx0_pcie_id(&dev, &rev);
238         if (dev == MV78X00_Z0_DEV_ID) {
239                 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
240                 eth_data->speed = SPEED_1000;
241                 eth_data->duplex = DUPLEX_FULL;
242         }
243 
244         orion_ge10_init(eth_data, GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM);
245 }
246 
247 
248 /*****************************************************************************
249  * GE11
250  ****************************************************************************/
251 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
252 {
253         u32 dev, rev;
254 
255         /*
256          * On the Z0, ge10 and ge11 are internally connected back
257          * to back, and not brought out.
258          */
259         mv78xx0_pcie_id(&dev, &rev);
260         if (dev == MV78X00_Z0_DEV_ID) {
261                 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
262                 eth_data->speed = SPEED_1000;
263                 eth_data->duplex = DUPLEX_FULL;
264         }
265 
266         orion_ge11_init(eth_data, GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM);
267 }
268 
269 /*****************************************************************************
270  * I2C
271  ****************************************************************************/
272 void __init mv78xx0_i2c_init(void)
273 {
274         orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
275         orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
276 }
277 
278 /*****************************************************************************
279  * SATA
280  ****************************************************************************/
281 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
282 {
283         orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
284 }
285 
286 
287 /*****************************************************************************
288  * UART0
289  ****************************************************************************/
290 void __init mv78xx0_uart0_init(void)
291 {
292         orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
293                          IRQ_MV78XX0_UART_0, tclk);
294 }
295 
296 
297 /*****************************************************************************
298  * UART1
299  ****************************************************************************/
300 void __init mv78xx0_uart1_init(void)
301 {
302         orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
303                          IRQ_MV78XX0_UART_1, tclk);
304 }
305 
306 
307 /*****************************************************************************
308  * UART2
309  ****************************************************************************/
310 void __init mv78xx0_uart2_init(void)
311 {
312         orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
313                          IRQ_MV78XX0_UART_2, tclk);
314 }
315 
316 /*****************************************************************************
317  * UART3
318  ****************************************************************************/
319 void __init mv78xx0_uart3_init(void)
320 {
321         orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
322                          IRQ_MV78XX0_UART_3, tclk);
323 }
324 
325 /*****************************************************************************
326  * Time handling
327  ****************************************************************************/
328 void __init mv78xx0_init_early(void)
329 {
330         orion_time_set_base(TIMER_VIRT_BASE);
331         if (mv78xx0_core_index() == 0)
332                 mvebu_mbus_init("marvell,mv78xx0-mbus",
333                                 BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ,
334                                 DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ);
335         else
336                 mvebu_mbus_init("marvell,mv78xx0-mbus",
337                                 BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ,
338                                 DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ);
339 }
340 
341 void __ref mv78xx0_timer_init(void)
342 {
343         orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
344                         IRQ_MV78XX0_TIMER_1, get_tclk());
345 }
346 
347 
348 /*****************************************************************************
349  * General
350  ****************************************************************************/
351 static char * __init mv78xx0_id(void)
352 {
353         u32 dev, rev;
354 
355         mv78xx0_pcie_id(&dev, &rev);
356 
357         if (dev == MV78X00_Z0_DEV_ID) {
358                 if (rev == MV78X00_REV_Z0)
359                         return "MV78X00-Z0";
360                 else
361                         return "MV78X00-Rev-Unsupported";
362         } else if (dev == MV78100_DEV_ID) {
363                 if (rev == MV78100_REV_A0)
364                         return "MV78100-A0";
365                 else if (rev == MV78100_REV_A1)
366                         return "MV78100-A1";
367                 else
368                         return "MV78100-Rev-Unsupported";
369         } else if (dev == MV78200_DEV_ID) {
370                 if (rev == MV78100_REV_A0)
371                         return "MV78200-A0";
372                 else
373                         return "MV78200-Rev-Unsupported";
374         } else {
375                 return "Device-Unknown";
376         }
377 }
378 
379 static int __init is_l2_writethrough(void)
380 {
381         return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
382 }
383 
384 void __init mv78xx0_init(void)
385 {
386         int core_index;
387         int hclk;
388         int pclk;
389         int l2clk;
390 
391         core_index = mv78xx0_core_index();
392         hclk = get_hclk();
393         get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
394 
395         printk(KERN_INFO "%s ", mv78xx0_id());
396         printk("core #%d, ", core_index);
397         printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
398         printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
399         printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
400         printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
401 
402         if (IS_ENABLED(CONFIG_CACHE_FEROCEON_L2))
403                 feroceon_l2_init(is_l2_writethrough());
404 
405         /* Setup root of clk tree */
406         clk_init();
407 }
408 
409 void mv78xx0_restart(enum reboot_mode mode, const char *cmd)
410 {
411         /*
412          * Enable soft reset to assert RSTOUTn.
413          */
414         writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
415 
416         /*
417          * Assert soft reset.
418          */
419         writel(SOFT_RESET, SYSTEM_SOFT_RESET);
420 
421         while (1)
422                 ;
423 }
424 

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