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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-omap1/dma.c

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  1 /*
  2  * OMAP1/OMAP7xx - specific DMA driver
  3  *
  4  * Copyright (C) 2003 - 2008 Nokia Corporation
  5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
  6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
  7  * Graphics DMA and LCD DMA graphics tranformations
  8  * by Imre Deak <imre.deak@nokia.com>
  9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
 10  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
 11  *
 12  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 13  * Converted DMA library into platform driver
 14  *                   - G, Manjunath Kondaiah <manjugk@ti.com>
 15  *
 16  * This program is free software; you can redistribute it and/or modify
 17  * it under the terms of the GNU General Public License version 2 as
 18  * published by the Free Software Foundation.
 19  */
 20 
 21 #include <linux/err.h>
 22 #include <linux/slab.h>
 23 #include <linux/module.h>
 24 #include <linux/init.h>
 25 #include <linux/device.h>
 26 #include <linux/io.h>
 27 #include <linux/dma-mapping.h>
 28 #include <linux/dmaengine.h>
 29 #include <linux/omap-dma.h>
 30 #include <mach/tc.h>
 31 
 32 #include "soc.h"
 33 
 34 #define OMAP1_DMA_BASE                  (0xfffed800)
 35 #define OMAP1_LOGICAL_DMA_CH_COUNT      17
 36 
 37 static u32 enable_1510_mode;
 38 
 39 static const struct omap_dma_reg reg_map[] = {
 40         [GCR]           = { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
 41         [GSCR]          = { 0x0404, 0x00, OMAP_DMA_REG_16BIT },
 42         [GRST1]         = { 0x0408, 0x00, OMAP_DMA_REG_16BIT },
 43         [HW_ID]         = { 0x0442, 0x00, OMAP_DMA_REG_16BIT },
 44         [PCH2_ID]       = { 0x0444, 0x00, OMAP_DMA_REG_16BIT },
 45         [PCH0_ID]       = { 0x0446, 0x00, OMAP_DMA_REG_16BIT },
 46         [PCH1_ID]       = { 0x0448, 0x00, OMAP_DMA_REG_16BIT },
 47         [PCHG_ID]       = { 0x044a, 0x00, OMAP_DMA_REG_16BIT },
 48         [PCHD_ID]       = { 0x044c, 0x00, OMAP_DMA_REG_16BIT },
 49         [CAPS_0]        = { 0x044e, 0x00, OMAP_DMA_REG_2X16BIT },
 50         [CAPS_1]        = { 0x0452, 0x00, OMAP_DMA_REG_2X16BIT },
 51         [CAPS_2]        = { 0x0456, 0x00, OMAP_DMA_REG_16BIT },
 52         [CAPS_3]        = { 0x0458, 0x00, OMAP_DMA_REG_16BIT },
 53         [CAPS_4]        = { 0x045a, 0x00, OMAP_DMA_REG_16BIT },
 54         [PCH2_SR]       = { 0x0460, 0x00, OMAP_DMA_REG_16BIT },
 55         [PCH0_SR]       = { 0x0480, 0x00, OMAP_DMA_REG_16BIT },
 56         [PCH1_SR]       = { 0x0482, 0x00, OMAP_DMA_REG_16BIT },
 57         [PCHD_SR]       = { 0x04c0, 0x00, OMAP_DMA_REG_16BIT },
 58 
 59         /* Common Registers */
 60         [CSDP]          = { 0x0000, 0x40, OMAP_DMA_REG_16BIT },
 61         [CCR]           = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
 62         [CICR]          = { 0x0004, 0x40, OMAP_DMA_REG_16BIT },
 63         [CSR]           = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
 64         [CEN]           = { 0x0010, 0x40, OMAP_DMA_REG_16BIT },
 65         [CFN]           = { 0x0012, 0x40, OMAP_DMA_REG_16BIT },
 66         [CSFI]          = { 0x0014, 0x40, OMAP_DMA_REG_16BIT },
 67         [CSEI]          = { 0x0016, 0x40, OMAP_DMA_REG_16BIT },
 68         [CPC]           = { 0x0018, 0x40, OMAP_DMA_REG_16BIT }, /* 15xx only */
 69         [CSAC]          = { 0x0018, 0x40, OMAP_DMA_REG_16BIT },
 70         [CDAC]          = { 0x001a, 0x40, OMAP_DMA_REG_16BIT },
 71         [CDEI]          = { 0x001c, 0x40, OMAP_DMA_REG_16BIT },
 72         [CDFI]          = { 0x001e, 0x40, OMAP_DMA_REG_16BIT },
 73         [CLNK_CTRL]     = { 0x0028, 0x40, OMAP_DMA_REG_16BIT },
 74 
 75         /* Channel specific register offsets */
 76         [CSSA]          = { 0x0008, 0x40, OMAP_DMA_REG_2X16BIT },
 77         [CDSA]          = { 0x000c, 0x40, OMAP_DMA_REG_2X16BIT },
 78         [COLOR]         = { 0x0020, 0x40, OMAP_DMA_REG_2X16BIT },
 79         [CCR2]          = { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
 80         [LCH_CTRL]      = { 0x002a, 0x40, OMAP_DMA_REG_16BIT },
 81 };
 82 
 83 static struct resource res[] __initdata = {
 84         [0] = {
 85                 .start  = OMAP1_DMA_BASE,
 86                 .end    = OMAP1_DMA_BASE + SZ_2K - 1,
 87                 .flags  = IORESOURCE_MEM,
 88         },
 89         [1] = {
 90                 .name   = "",
 91                 .start  = INT_DMA_CH0_6,
 92                 .flags  = IORESOURCE_IRQ,
 93         },
 94         [2] = {
 95                 .name   = "1",
 96                 .start  = INT_DMA_CH1_7,
 97                 .flags  = IORESOURCE_IRQ,
 98         },
 99         [3] = {
100                 .name   = "2",
101                 .start  = INT_DMA_CH2_8,
102                 .flags  = IORESOURCE_IRQ,
103         },
104         [4] = {
105                 .name   = "3",
106                 .start  = INT_DMA_CH3,
107                 .flags  = IORESOURCE_IRQ,
108         },
109         [5] = {
110                 .name   = "4",
111                 .start  = INT_DMA_CH4,
112                 .flags  = IORESOURCE_IRQ,
113         },
114         [6] = {
115                 .name   = "5",
116                 .start  = INT_DMA_CH5,
117                 .flags  = IORESOURCE_IRQ,
118         },
119         /* Handled in lcd_dma.c */
120         [7] = {
121                 .name   = "6",
122                 .start  = INT_1610_DMA_CH6,
123                 .flags  = IORESOURCE_IRQ,
124         },
125         /* irq's for omap16xx and omap7xx */
126         [8] = {
127                 .name   = "7",
128                 .start  = INT_1610_DMA_CH7,
129                 .flags  = IORESOURCE_IRQ,
130         },
131         [9] = {
132                 .name   = "8",
133                 .start  = INT_1610_DMA_CH8,
134                 .flags  = IORESOURCE_IRQ,
135         },
136         [10] = {
137                 .name  = "9",
138                 .start = INT_1610_DMA_CH9,
139                 .flags = IORESOURCE_IRQ,
140         },
141         [11] = {
142                 .name  = "10",
143                 .start = INT_1610_DMA_CH10,
144                 .flags = IORESOURCE_IRQ,
145         },
146         [12] = {
147                 .name  = "11",
148                 .start = INT_1610_DMA_CH11,
149                 .flags = IORESOURCE_IRQ,
150         },
151         [13] = {
152                 .name  = "12",
153                 .start = INT_1610_DMA_CH12,
154                 .flags = IORESOURCE_IRQ,
155         },
156         [14] = {
157                 .name  = "13",
158                 .start = INT_1610_DMA_CH13,
159                 .flags = IORESOURCE_IRQ,
160         },
161         [15] = {
162                 .name  = "14",
163                 .start = INT_1610_DMA_CH14,
164                 .flags = IORESOURCE_IRQ,
165         },
166         [16] = {
167                 .name  = "15",
168                 .start = INT_1610_DMA_CH15,
169                 .flags = IORESOURCE_IRQ,
170         },
171         [17] = {
172                 .name  = "16",
173                 .start = INT_DMA_LCD,
174                 .flags = IORESOURCE_IRQ,
175         },
176 };
177 
178 static void __iomem *dma_base;
179 static inline void dma_write(u32 val, int reg, int lch)
180 {
181         void __iomem *addr = dma_base;
182 
183         addr += reg_map[reg].offset;
184         addr += reg_map[reg].stride * lch;
185 
186         __raw_writew(val, addr);
187         if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
188                 __raw_writew(val >> 16, addr + 2);
189 }
190 
191 static inline u32 dma_read(int reg, int lch)
192 {
193         void __iomem *addr = dma_base;
194         uint32_t val;
195 
196         addr += reg_map[reg].offset;
197         addr += reg_map[reg].stride * lch;
198 
199         val = __raw_readw(addr);
200         if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
201                 val |= __raw_readw(addr + 2) << 16;
202 
203         return val;
204 }
205 
206 static void omap1_clear_lch_regs(int lch)
207 {
208         int i;
209 
210         for (i = CPC; i <= COLOR; i += 1)
211                 dma_write(0, i, lch);
212 }
213 
214 static void omap1_clear_dma(int lch)
215 {
216         u32 l;
217 
218         l = dma_read(CCR, lch);
219         l &= ~OMAP_DMA_CCR_EN;
220         dma_write(l, CCR, lch);
221 
222         /* Clear pending interrupts */
223         l = dma_read(CSR, lch);
224 }
225 
226 static void omap1_show_dma_caps(void)
227 {
228         if (enable_1510_mode) {
229                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
230         } else {
231                 u16 w;
232                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
233                                                         dma_read(HW_ID, 0));
234                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
235                         dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
236                         dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
237                         dma_read(CAPS_4, 0));
238 
239                 /* Disable OMAP 3.0/3.1 compatibility mode. */
240                 w = dma_read(GSCR, 0);
241                 w |= 1 << 3;
242                 dma_write(w, GSCR, 0);
243         }
244         return;
245 }
246 
247 static unsigned configure_dma_errata(void)
248 {
249         unsigned errata = 0;
250 
251         /*
252          * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
253          * read before the DMA controller finished disabling the channel.
254          */
255         if (!cpu_is_omap15xx())
256                 SET_DMA_ERRATA(DMA_ERRATA_3_3);
257 
258         return errata;
259 }
260 
261 static const struct platform_device_info omap_dma_dev_info = {
262         .name = "omap-dma-engine",
263         .id = -1,
264         .dma_mask = DMA_BIT_MASK(32),
265         .res = res,
266         .num_res = 1,
267 };
268 
269 /* OMAP730, OMAP850 */
270 static const struct dma_slave_map omap7xx_sdma_map[] = {
271         { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) },
272         { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) },
273         { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(10) },
274         { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(11) },
275         { "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) },
276         { "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) },
277         { "omap_udc", "rx0", SDMA_FILTER_PARAM(26) },
278         { "omap_udc", "rx1", SDMA_FILTER_PARAM(27) },
279         { "omap_udc", "rx2", SDMA_FILTER_PARAM(28) },
280         { "omap_udc", "tx0", SDMA_FILTER_PARAM(29) },
281         { "omap_udc", "tx1", SDMA_FILTER_PARAM(30) },
282         { "omap_udc", "tx2", SDMA_FILTER_PARAM(31) },
283 };
284 
285 /* OMAP1510, OMAP1610*/
286 static const struct dma_slave_map omap1xxx_sdma_map[] = {
287         { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) },
288         { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) },
289         { "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(10) },
290         { "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(11) },
291         { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(16) },
292         { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(17) },
293         { "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) },
294         { "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) },
295         { "omap_udc", "rx0", SDMA_FILTER_PARAM(26) },
296         { "omap_udc", "rx1", SDMA_FILTER_PARAM(27) },
297         { "omap_udc", "rx2", SDMA_FILTER_PARAM(28) },
298         { "omap_udc", "tx0", SDMA_FILTER_PARAM(29) },
299         { "omap_udc", "tx1", SDMA_FILTER_PARAM(30) },
300         { "omap_udc", "tx2", SDMA_FILTER_PARAM(31) },
301         { "mmci-omap.1", "tx", SDMA_FILTER_PARAM(54) },
302         { "mmci-omap.1", "rx", SDMA_FILTER_PARAM(55) },
303 };
304 
305 static struct omap_system_dma_plat_info dma_plat_info __initdata = {
306         .reg_map        = reg_map,
307         .channel_stride = 0x40,
308         .show_dma_caps  = omap1_show_dma_caps,
309         .clear_lch_regs = omap1_clear_lch_regs,
310         .clear_dma      = omap1_clear_dma,
311         .dma_write      = dma_write,
312         .dma_read       = dma_read,
313 };
314 
315 static int __init omap1_system_dma_init(void)
316 {
317         struct omap_system_dma_plat_info        p;
318         struct omap_dma_dev_attr                *d;
319         struct platform_device                  *pdev, *dma_pdev;
320         int ret;
321 
322         pdev = platform_device_alloc("omap_dma_system", 0);
323         if (!pdev) {
324                 pr_err("%s: Unable to device alloc for dma\n",
325                         __func__);
326                 return -ENOMEM;
327         }
328 
329         dma_base = ioremap(res[0].start, resource_size(&res[0]));
330         if (!dma_base) {
331                 pr_err("%s: Unable to ioremap\n", __func__);
332                 ret = -ENODEV;
333                 goto exit_device_put;
334         }
335 
336         ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
337         if (ret) {
338                 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
339                         __func__, pdev->name, pdev->id);
340                 goto exit_iounmap;
341         }
342 
343         d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
344         if (!d) {
345                 dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
346                         __func__, pdev->name);
347                 ret = -ENOMEM;
348                 goto exit_iounmap;
349         }
350 
351         d->lch_count            = OMAP1_LOGICAL_DMA_CH_COUNT;
352 
353         /* Valid attributes for omap1 plus processors */
354         if (cpu_is_omap15xx())
355                 d->dev_caps = ENABLE_1510_MODE;
356         enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
357 
358         if (cpu_is_omap16xx())
359                 d->dev_caps = ENABLE_16XX_MODE;
360 
361         d->dev_caps             |= SRC_PORT;
362         d->dev_caps             |= DST_PORT;
363         d->dev_caps             |= SRC_INDEX;
364         d->dev_caps             |= DST_INDEX;
365         d->dev_caps             |= IS_BURST_ONLY4;
366         d->dev_caps             |= CLEAR_CSR_ON_READ;
367         d->dev_caps             |= IS_WORD_16;
368 
369         if (cpu_is_omap15xx())
370                 d->chan_count = 9;
371         else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
372                 if (!(d->dev_caps & ENABLE_1510_MODE))
373                         d->chan_count = 16;
374                 else
375                         d->chan_count = 9;
376         }
377 
378         p = dma_plat_info;
379         p.dma_attr = d;
380         p.errata = configure_dma_errata();
381 
382         if (cpu_is_omap7xx()) {
383                 p.slave_map = omap7xx_sdma_map;
384                 p.slavecnt = ARRAY_SIZE(omap7xx_sdma_map);
385         } else {
386                 p.slave_map = omap1xxx_sdma_map;
387                 p.slavecnt = ARRAY_SIZE(omap1xxx_sdma_map);
388         }
389 
390         ret = platform_device_add_data(pdev, &p, sizeof(p));
391         if (ret) {
392                 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
393                         __func__, pdev->name, pdev->id);
394                 goto exit_release_d;
395         }
396 
397         ret = platform_device_add(pdev);
398         if (ret) {
399                 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
400                         __func__, pdev->name, pdev->id);
401                 goto exit_release_d;
402         }
403 
404         dma_pdev = platform_device_register_full(&omap_dma_dev_info);
405         if (IS_ERR(dma_pdev)) {
406                 ret = PTR_ERR(dma_pdev);
407                 goto exit_release_pdev;
408         }
409 
410         return ret;
411 
412 exit_release_pdev:
413         platform_device_del(pdev);
414 exit_release_d:
415         kfree(d);
416 exit_iounmap:
417         iounmap(dma_base);
418 exit_device_put:
419         platform_device_put(pdev);
420 
421         return ret;
422 }
423 arch_initcall(omap1_system_dma_init);
424 

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