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Linux/arch/arm/mach-omap1/irq.c

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  1 /*
  2  * linux/arch/arm/mach-omap1/irq.c
  3  *
  4  * Interrupt handler for all OMAP boards
  5  *
  6  * Copyright (C) 2004 Nokia Corporation
  7  * Written by Tony Lindgren <tony@atomide.com>
  8  * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
  9  *
 10  * Completely re-written to support various OMAP chips with bank specific
 11  * interrupt handlers.
 12  *
 13  * Some snippets of the code taken from the older OMAP interrupt handler
 14  * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
 15  *
 16  * GPIO interrupt handler moved to gpio.c by Juha Yrjola
 17  *
 18  * This program is free software; you can redistribute it and/or modify it
 19  * under the terms of the GNU General Public License as published by the
 20  * Free Software Foundation; either version 2 of the License, or (at your
 21  * option) any later version.
 22  *
 23  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
 26  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 29  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 30  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 33  *
 34  * You should have received a copy of the  GNU General Public License along
 35  * with this program; if not, write  to the Free Software Foundation, Inc.,
 36  * 675 Mass Ave, Cambridge, MA 02139, USA.
 37  */
 38 
 39 #include <linux/init.h>
 40 #include <linux/module.h>
 41 #include <linux/sched.h>
 42 #include <linux/interrupt.h>
 43 #include <linux/io.h>
 44 
 45 #include <mach/hardware.h>
 46 #include <asm/irq.h>
 47 #include <asm/mach/irq.h>
 48 #include <mach/gpio.h>
 49 #include <plat/cpu.h>
 50 
 51 #define IRQ_BANK(irq) ((irq) >> 5)
 52 #define IRQ_BIT(irq)  ((irq) & 0x1f)
 53 
 54 struct omap_irq_bank {
 55         unsigned long base_reg;
 56         unsigned long trigger_map;
 57         unsigned long wake_enable;
 58 };
 59 
 60 u32 omap_irq_flags;
 61 static unsigned int irq_bank_count;
 62 static struct omap_irq_bank *irq_banks;
 63 
 64 static inline unsigned int irq_bank_readl(int bank, int offset)
 65 {
 66         return omap_readl(irq_banks[bank].base_reg + offset);
 67 }
 68 
 69 static inline void irq_bank_writel(unsigned long value, int bank, int offset)
 70 {
 71         omap_writel(value, irq_banks[bank].base_reg + offset);
 72 }
 73 
 74 static void omap_ack_irq(struct irq_data *d)
 75 {
 76         if (d->irq > 31)
 77                 omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
 78 
 79         omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
 80 }
 81 
 82 static void omap_mask_irq(struct irq_data *d)
 83 {
 84         int bank = IRQ_BANK(d->irq);
 85         u32 l;
 86 
 87         l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
 88         l |= 1 << IRQ_BIT(d->irq);
 89         omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
 90 }
 91 
 92 static void omap_unmask_irq(struct irq_data *d)
 93 {
 94         int bank = IRQ_BANK(d->irq);
 95         u32 l;
 96 
 97         l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
 98         l &= ~(1 << IRQ_BIT(d->irq));
 99         omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
100 }
101 
102 static void omap_mask_ack_irq(struct irq_data *d)
103 {
104         omap_mask_irq(d);
105         omap_ack_irq(d);
106 }
107 
108 static int omap_wake_irq(struct irq_data *d, unsigned int enable)
109 {
110         int bank = IRQ_BANK(d->irq);
111 
112         if (enable)
113                 irq_banks[bank].wake_enable |= IRQ_BIT(d->irq);
114         else
115                 irq_banks[bank].wake_enable &= ~IRQ_BIT(d->irq);
116 
117         return 0;
118 }
119 
120 
121 /*
122  * Allows tuning the IRQ type and priority
123  *
124  * NOTE: There is currently no OMAP fiq handler for Linux. Read the
125  *       mailing list threads on FIQ handlers if you are planning to
126  *       add a FIQ handler for OMAP.
127  */
128 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
129 {
130         signed int bank;
131         unsigned long val, offset;
132 
133         bank = IRQ_BANK(irq);
134         /* FIQ is only available on bank 0 interrupts */
135         fiq = bank ? 0 : (fiq & 0x1);
136         val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
137         offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
138         irq_bank_writel(val, bank, offset);
139 }
140 
141 #if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
142 static struct omap_irq_bank omap7xx_irq_banks[] = {
143         { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3f8e22f },
144         { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb9c1f2 },
145         { .base_reg = OMAP_IH2_BASE + 0x100,    .trigger_map = 0x800040f3 },
146 };
147 #endif
148 
149 #ifdef CONFIG_ARCH_OMAP15XX
150 static struct omap_irq_bank omap1510_irq_banks[] = {
151         { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3febfff },
152         { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xffbfffed },
153 };
154 static struct omap_irq_bank omap310_irq_banks[] = {
155         { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3faefc3 },
156         { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0x65b3c061 },
157 };
158 #endif
159 
160 #if defined(CONFIG_ARCH_OMAP16XX)
161 
162 static struct omap_irq_bank omap1610_irq_banks[] = {
163         { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3fefe8f },
164         { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb7c1fd },
165         { .base_reg = OMAP_IH2_BASE + 0x100,    .trigger_map = 0xffffb7ff },
166         { .base_reg = OMAP_IH2_BASE + 0x200,    .trigger_map = 0xffffffff },
167 };
168 #endif
169 
170 static struct irq_chip omap_irq_chip = {
171         .name           = "MPU",
172         .irq_ack        = omap_mask_ack_irq,
173         .irq_mask       = omap_mask_irq,
174         .irq_unmask     = omap_unmask_irq,
175         .irq_set_wake   = omap_wake_irq,
176 };
177 
178 void __init omap_init_irq(void)
179 {
180         int i, j;
181 
182 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
183         if (cpu_is_omap7xx()) {
184                 omap_irq_flags = INT_7XX_IH2_IRQ;
185                 irq_banks = omap7xx_irq_banks;
186                 irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
187         }
188 #endif
189 #ifdef CONFIG_ARCH_OMAP15XX
190         if (cpu_is_omap1510()) {
191                 omap_irq_flags = INT_1510_IH2_IRQ;
192                 irq_banks = omap1510_irq_banks;
193                 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
194         }
195         if (cpu_is_omap310()) {
196                 omap_irq_flags = INT_1510_IH2_IRQ;
197                 irq_banks = omap310_irq_banks;
198                 irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
199         }
200 #endif
201 #if defined(CONFIG_ARCH_OMAP16XX)
202         if (cpu_is_omap16xx()) {
203                 omap_irq_flags = INT_1510_IH2_IRQ;
204                 irq_banks = omap1610_irq_banks;
205                 irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
206         }
207 #endif
208         printk("Total of %i interrupts in %i interrupt banks\n",
209                irq_bank_count * 32, irq_bank_count);
210 
211         /* Mask and clear all interrupts */
212         for (i = 0; i < irq_bank_count; i++) {
213                 irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
214                 irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
215         }
216 
217         /* Clear any pending interrupts */
218         irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
219         irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
220 
221         /* Enable interrupts in global mask */
222         if (cpu_is_omap7xx())
223                 irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
224 
225         /* Install the interrupt handlers for each bank */
226         for (i = 0; i < irq_bank_count; i++) {
227                 for (j = i * 32; j < (i + 1) * 32; j++) {
228                         int irq_trigger;
229 
230                         irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
231                         omap_irq_set_cfg(j, 0, 0, irq_trigger);
232 
233                         irq_set_chip_and_handler(j, &omap_irq_chip,
234                                                  handle_level_irq);
235                         set_irq_flags(j, IRQF_VALID);
236                 }
237         }
238 
239         /* Unmask level 2 handler */
240 
241         if (cpu_is_omap7xx())
242                 omap_unmask_irq(irq_get_irq_data(INT_7XX_IH2_IRQ));
243         else if (cpu_is_omap15xx())
244                 omap_unmask_irq(irq_get_irq_data(INT_1510_IH2_IRQ));
245         else if (cpu_is_omap16xx())
246                 omap_unmask_irq(irq_get_irq_data(INT_1610_IH2_IRQ));
247 }
248 

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