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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-omap2/control.c

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  1 /*
  2  * OMAP2/3 System Control Module register access
  3  *
  4  * Copyright (C) 2007, 2012 Texas Instruments, Inc.
  5  * Copyright (C) 2007 Nokia Corporation
  6  *
  7  * Written by Paul Walmsley
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 #undef DEBUG
 14 
 15 #include <linux/kernel.h>
 16 #include <linux/io.h>
 17 #include <linux/of_address.h>
 18 #include <linux/regmap.h>
 19 #include <linux/mfd/syscon.h>
 20 
 21 #include "soc.h"
 22 #include "iomap.h"
 23 #include "common.h"
 24 #include "cm-regbits-34xx.h"
 25 #include "prm-regbits-34xx.h"
 26 #include "prm3xxx.h"
 27 #include "cm3xxx.h"
 28 #include "sdrc.h"
 29 #include "pm.h"
 30 #include "control.h"
 31 #include "clock.h"
 32 
 33 /* Used by omap3_ctrl_save_padconf() */
 34 #define START_PADCONF_SAVE              0x2
 35 #define PADCONF_SAVE_DONE               0x1
 36 
 37 static void __iomem *omap2_ctrl_base;
 38 static s16 omap2_ctrl_offset;
 39 
 40 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 41 struct omap3_scratchpad {
 42         u32 boot_config_ptr;
 43         u32 public_restore_ptr;
 44         u32 secure_ram_restore_ptr;
 45         u32 sdrc_module_semaphore;
 46         u32 prcm_block_offset;
 47         u32 sdrc_block_offset;
 48 };
 49 
 50 struct omap3_scratchpad_prcm_block {
 51         u32 prm_contents[2];
 52         u32 cm_contents[11];
 53         u32 prcm_block_size;
 54 };
 55 
 56 struct omap3_scratchpad_sdrc_block {
 57         u16 sysconfig;
 58         u16 cs_cfg;
 59         u16 sharing;
 60         u16 err_type;
 61         u32 dll_a_ctrl;
 62         u32 dll_b_ctrl;
 63         u32 power;
 64         u32 cs_0;
 65         u32 mcfg_0;
 66         u16 mr_0;
 67         u16 emr_1_0;
 68         u16 emr_2_0;
 69         u16 emr_3_0;
 70         u32 actim_ctrla_0;
 71         u32 actim_ctrlb_0;
 72         u32 rfr_ctrl_0;
 73         u32 cs_1;
 74         u32 mcfg_1;
 75         u16 mr_1;
 76         u16 emr_1_1;
 77         u16 emr_2_1;
 78         u16 emr_3_1;
 79         u32 actim_ctrla_1;
 80         u32 actim_ctrlb_1;
 81         u32 rfr_ctrl_1;
 82         u16 dcdl_1_ctrl;
 83         u16 dcdl_2_ctrl;
 84         u32 flags;
 85         u32 block_size;
 86 };
 87 
 88 void *omap3_secure_ram_storage;
 89 
 90 /*
 91  * This is used to store ARM registers in SDRAM before attempting
 92  * an MPU OFF. The save and restore happens from the SRAM sleep code.
 93  * The address is stored in scratchpad, so that it can be used
 94  * during the restore path.
 95  */
 96 u32 omap3_arm_context[128];
 97 
 98 struct omap3_control_regs {
 99         u32 sysconfig;
100         u32 devconf0;
101         u32 mem_dftrw0;
102         u32 mem_dftrw1;
103         u32 msuspendmux_0;
104         u32 msuspendmux_1;
105         u32 msuspendmux_2;
106         u32 msuspendmux_3;
107         u32 msuspendmux_4;
108         u32 msuspendmux_5;
109         u32 sec_ctrl;
110         u32 devconf1;
111         u32 csirxfe;
112         u32 iva2_bootaddr;
113         u32 iva2_bootmod;
114         u32 wkup_ctrl;
115         u32 debobs_0;
116         u32 debobs_1;
117         u32 debobs_2;
118         u32 debobs_3;
119         u32 debobs_4;
120         u32 debobs_5;
121         u32 debobs_6;
122         u32 debobs_7;
123         u32 debobs_8;
124         u32 prog_io0;
125         u32 prog_io1;
126         u32 dss_dpll_spreading;
127         u32 core_dpll_spreading;
128         u32 per_dpll_spreading;
129         u32 usbhost_dpll_spreading;
130         u32 pbias_lite;
131         u32 temp_sensor;
132         u32 sramldo4;
133         u32 sramldo5;
134         u32 csi;
135         u32 padconf_sys_nirq;
136 };
137 
138 static struct omap3_control_regs control_context;
139 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
140 
141 void __init omap2_set_globals_control(void __iomem *ctrl)
142 {
143         omap2_ctrl_base = ctrl;
144 }
145 
146 u8 omap_ctrl_readb(u16 offset)
147 {
148         u32 val;
149         u8 byte_offset = offset & 0x3;
150 
151         val = omap_ctrl_readl(offset);
152 
153         return (val >> (byte_offset * 8)) & 0xff;
154 }
155 
156 u16 omap_ctrl_readw(u16 offset)
157 {
158         u32 val;
159         u16 byte_offset = offset & 0x2;
160 
161         val = omap_ctrl_readl(offset);
162 
163         return (val >> (byte_offset * 8)) & 0xffff;
164 }
165 
166 u32 omap_ctrl_readl(u16 offset)
167 {
168         offset &= 0xfffc;
169 
170         return readl_relaxed(omap2_ctrl_base + offset);
171 }
172 
173 void omap_ctrl_writeb(u8 val, u16 offset)
174 {
175         u32 tmp;
176         u8 byte_offset = offset & 0x3;
177 
178         tmp = omap_ctrl_readl(offset);
179 
180         tmp &= 0xffffffff ^ (0xff << (byte_offset * 8));
181         tmp |= val << (byte_offset * 8);
182 
183         omap_ctrl_writel(tmp, offset);
184 }
185 
186 void omap_ctrl_writew(u16 val, u16 offset)
187 {
188         u32 tmp;
189         u8 byte_offset = offset & 0x2;
190 
191         tmp = omap_ctrl_readl(offset);
192 
193         tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8));
194         tmp |= val << (byte_offset * 8);
195 
196         omap_ctrl_writel(tmp, offset);
197 }
198 
199 void omap_ctrl_writel(u32 val, u16 offset)
200 {
201         offset &= 0xfffc;
202         writel_relaxed(val, omap2_ctrl_base + offset);
203 }
204 
205 #ifdef CONFIG_ARCH_OMAP3
206 
207 /**
208  * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
209  * @bootmode: 8-bit value to pass to some boot code
210  *
211  * Set the bootmode in the scratchpad RAM.  This is used after the
212  * system restarts.  Not sure what actually uses this - it may be the
213  * bootloader, rather than the boot ROM - contrary to the preserved
214  * comment below.  No return value.
215  */
216 void omap3_ctrl_write_boot_mode(u8 bootmode)
217 {
218         u32 l;
219 
220         l = ('B' << 24) | ('M' << 16) | bootmode;
221 
222         /*
223          * Reserve the first word in scratchpad for communicating
224          * with the boot ROM. A pointer to a data structure
225          * describing the boot process can be stored there,
226          * cf. OMAP34xx TRM, Initialization / Software Booting
227          * Configuration.
228          *
229          * XXX This should use some omap_ctrl_writel()-type function
230          */
231         writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
232 }
233 
234 #endif
235 
236 /**
237  * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
238  * @bootaddr: physical address of the boot loader
239  *
240  * Set boot address for the boot loader of a supported processor
241  * when a power ON sequence occurs.
242  */
243 void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
244 {
245         u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
246                      cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
247                      cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
248                      soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
249                      0;
250 
251         if (!offset) {
252                 pr_err("%s: unsupported omap type\n", __func__);
253                 return;
254         }
255 
256         omap_ctrl_writel(bootaddr, offset);
257 }
258 
259 /**
260  * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
261  * @bootmode: 8-bit value to pass to some boot code
262  *
263  * Sets boot mode for the boot loader of a supported processor
264  * when a power ON sequence occurs.
265  */
266 void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
267 {
268         u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
269                      cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
270                      0;
271 
272         if (!offset) {
273                 pr_err("%s: unsupported omap type\n", __func__);
274                 return;
275         }
276 
277         omap_ctrl_writel(bootmode, offset);
278 }
279 
280 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
281 /*
282  * Clears the scratchpad contents in case of cold boot-
283  * called during bootup
284  */
285 void omap3_clear_scratchpad_contents(void)
286 {
287         u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
288         void __iomem *v_addr;
289         u32 offset = 0;
290 
291         v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
292         if (omap3xxx_prm_clear_global_cold_reset()) {
293                 for ( ; offset <= max_offset; offset += 0x4)
294                         writel_relaxed(0x0, (v_addr + offset));
295         }
296 }
297 
298 /* Populate the scratchpad structure with restore structure */
299 void omap3_save_scratchpad_contents(void)
300 {
301         void  __iomem *scratchpad_address;
302         u32 arm_context_addr;
303         struct omap3_scratchpad scratchpad_contents;
304         struct omap3_scratchpad_prcm_block prcm_block_contents;
305         struct omap3_scratchpad_sdrc_block sdrc_block_contents;
306 
307         /*
308          * Populate the Scratchpad contents
309          *
310          * The "get_*restore_pointer" functions are used to provide a
311          * physical restore address where the ROM code jumps while waking
312          * up from MPU OFF/OSWR state.
313          * The restore pointer is stored into the scratchpad.
314          */
315         scratchpad_contents.boot_config_ptr = 0x0;
316         if (cpu_is_omap3630())
317                 scratchpad_contents.public_restore_ptr =
318                         virt_to_phys(omap3_restore_3630);
319         else if (omap_rev() != OMAP3430_REV_ES3_0 &&
320                                         omap_rev() != OMAP3430_REV_ES3_1 &&
321                                         omap_rev() != OMAP3430_REV_ES3_1_2)
322                 scratchpad_contents.public_restore_ptr =
323                         virt_to_phys(omap3_restore);
324         else
325                 scratchpad_contents.public_restore_ptr =
326                         virt_to_phys(omap3_restore_es3);
327 
328         if (omap_type() == OMAP2_DEVICE_TYPE_GP)
329                 scratchpad_contents.secure_ram_restore_ptr = 0x0;
330         else
331                 scratchpad_contents.secure_ram_restore_ptr =
332                         (u32) __pa(omap3_secure_ram_storage);
333         scratchpad_contents.sdrc_module_semaphore = 0x0;
334         scratchpad_contents.prcm_block_offset = 0x2C;
335         scratchpad_contents.sdrc_block_offset = 0x64;
336 
337         /* Populate the PRCM block contents */
338         omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents);
339         omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
340 
341         prcm_block_contents.prcm_block_size = 0x0;
342 
343         /* Populate the SDRC block contents */
344         sdrc_block_contents.sysconfig =
345                         (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
346         sdrc_block_contents.cs_cfg =
347                         (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
348         sdrc_block_contents.sharing =
349                         (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
350         sdrc_block_contents.err_type =
351                         (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
352         sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
353         sdrc_block_contents.dll_b_ctrl = 0x0;
354         /*
355          * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
356          * be programed to issue automatic self refresh on timeout
357          * of AUTO_CNT = 1 prior to any transition to OFF mode.
358          */
359         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
360                         && (omap_rev() >= OMAP3430_REV_ES3_0))
361                 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
362                                 ~(SDRC_POWER_AUTOCOUNT_MASK|
363                                 SDRC_POWER_CLKCTRL_MASK)) |
364                                 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
365                                 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
366         else
367                 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
368 
369         sdrc_block_contents.cs_0 = 0x0;
370         sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
371         sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
372         sdrc_block_contents.emr_1_0 = 0x0;
373         sdrc_block_contents.emr_2_0 = 0x0;
374         sdrc_block_contents.emr_3_0 = 0x0;
375         sdrc_block_contents.actim_ctrla_0 =
376                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
377         sdrc_block_contents.actim_ctrlb_0 =
378                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
379         sdrc_block_contents.rfr_ctrl_0 =
380                         sdrc_read_reg(SDRC_RFR_CTRL_0);
381         sdrc_block_contents.cs_1 = 0x0;
382         sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
383         sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
384         sdrc_block_contents.emr_1_1 = 0x0;
385         sdrc_block_contents.emr_2_1 = 0x0;
386         sdrc_block_contents.emr_3_1 = 0x0;
387         sdrc_block_contents.actim_ctrla_1 =
388                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
389         sdrc_block_contents.actim_ctrlb_1 =
390                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
391         sdrc_block_contents.rfr_ctrl_1 =
392                         sdrc_read_reg(SDRC_RFR_CTRL_1);
393         sdrc_block_contents.dcdl_1_ctrl = 0x0;
394         sdrc_block_contents.dcdl_2_ctrl = 0x0;
395         sdrc_block_contents.flags = 0x0;
396         sdrc_block_contents.block_size = 0x0;
397 
398         arm_context_addr = virt_to_phys(omap3_arm_context);
399 
400         /* Copy all the contents to the scratchpad location */
401         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
402         memcpy_toio(scratchpad_address, &scratchpad_contents,
403                  sizeof(scratchpad_contents));
404         /* Scratchpad contents being 32 bits, a divide by 4 done here */
405         memcpy_toio(scratchpad_address +
406                 scratchpad_contents.prcm_block_offset,
407                 &prcm_block_contents, sizeof(prcm_block_contents));
408         memcpy_toio(scratchpad_address +
409                 scratchpad_contents.sdrc_block_offset,
410                 &sdrc_block_contents, sizeof(sdrc_block_contents));
411         /*
412          * Copies the address of the location in SDRAM where ARM
413          * registers get saved during a MPU OFF transition.
414          */
415         memcpy_toio(scratchpad_address +
416                 scratchpad_contents.sdrc_block_offset +
417                 sizeof(sdrc_block_contents), &arm_context_addr, 4);
418 }
419 
420 void omap3_control_save_context(void)
421 {
422         control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
423         control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
424         control_context.mem_dftrw0 =
425                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
426         control_context.mem_dftrw1 =
427                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
428         control_context.msuspendmux_0 =
429                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
430         control_context.msuspendmux_1 =
431                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
432         control_context.msuspendmux_2 =
433                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
434         control_context.msuspendmux_3 =
435                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
436         control_context.msuspendmux_4 =
437                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
438         control_context.msuspendmux_5 =
439                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
440         control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
441         control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
442         control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
443         control_context.iva2_bootaddr =
444                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
445         control_context.iva2_bootmod =
446                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
447         control_context.wkup_ctrl = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL);
448         control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
449         control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
450         control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
451         control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
452         control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
453         control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
454         control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
455         control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
456         control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
457         control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
458         control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
459         control_context.dss_dpll_spreading =
460                         omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
461         control_context.core_dpll_spreading =
462                         omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
463         control_context.per_dpll_spreading =
464                         omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
465         control_context.usbhost_dpll_spreading =
466                 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
467         control_context.pbias_lite =
468                         omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
469         control_context.temp_sensor =
470                         omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
471         control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
472         control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
473         control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
474         control_context.padconf_sys_nirq =
475                 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
476 }
477 
478 void omap3_control_restore_context(void)
479 {
480         omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
481         omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
482         omap_ctrl_writel(control_context.mem_dftrw0,
483                                         OMAP343X_CONTROL_MEM_DFTRW0);
484         omap_ctrl_writel(control_context.mem_dftrw1,
485                                         OMAP343X_CONTROL_MEM_DFTRW1);
486         omap_ctrl_writel(control_context.msuspendmux_0,
487                                         OMAP2_CONTROL_MSUSPENDMUX_0);
488         omap_ctrl_writel(control_context.msuspendmux_1,
489                                         OMAP2_CONTROL_MSUSPENDMUX_1);
490         omap_ctrl_writel(control_context.msuspendmux_2,
491                                         OMAP2_CONTROL_MSUSPENDMUX_2);
492         omap_ctrl_writel(control_context.msuspendmux_3,
493                                         OMAP2_CONTROL_MSUSPENDMUX_3);
494         omap_ctrl_writel(control_context.msuspendmux_4,
495                                         OMAP2_CONTROL_MSUSPENDMUX_4);
496         omap_ctrl_writel(control_context.msuspendmux_5,
497                                         OMAP2_CONTROL_MSUSPENDMUX_5);
498         omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
499         omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
500         omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
501         omap_ctrl_writel(control_context.iva2_bootaddr,
502                                         OMAP343X_CONTROL_IVA2_BOOTADDR);
503         omap_ctrl_writel(control_context.iva2_bootmod,
504                                         OMAP343X_CONTROL_IVA2_BOOTMOD);
505         omap_ctrl_writel(control_context.wkup_ctrl, OMAP34XX_CONTROL_WKUP_CTRL);
506         omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
507         omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
508         omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
509         omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
510         omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
511         omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
512         omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
513         omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
514         omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
515         omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
516         omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
517         omap_ctrl_writel(control_context.dss_dpll_spreading,
518                                         OMAP343X_CONTROL_DSS_DPLL_SPREADING);
519         omap_ctrl_writel(control_context.core_dpll_spreading,
520                                         OMAP343X_CONTROL_CORE_DPLL_SPREADING);
521         omap_ctrl_writel(control_context.per_dpll_spreading,
522                                         OMAP343X_CONTROL_PER_DPLL_SPREADING);
523         omap_ctrl_writel(control_context.usbhost_dpll_spreading,
524                                 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
525         omap_ctrl_writel(control_context.pbias_lite,
526                                         OMAP343X_CONTROL_PBIAS_LITE);
527         omap_ctrl_writel(control_context.temp_sensor,
528                                         OMAP343X_CONTROL_TEMP_SENSOR);
529         omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
530         omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
531         omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
532         omap_ctrl_writel(control_context.padconf_sys_nirq,
533                          OMAP343X_CONTROL_PADCONF_SYSNIRQ);
534 }
535 
536 void omap3630_ctrl_disable_rta(void)
537 {
538         if (!cpu_is_omap3630())
539                 return;
540         omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
541 }
542 
543 /**
544  * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
545  *
546  * Tell the SCM to start saving the padconf registers, then wait for
547  * the process to complete.  Returns 0 unconditionally, although it
548  * should also eventually be able to return -ETIMEDOUT, if the save
549  * does not complete.
550  *
551  * XXX This function is missing a timeout.  What should it be?
552  */
553 int omap3_ctrl_save_padconf(void)
554 {
555         u32 cpo;
556 
557         /* Save the padconf registers */
558         cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
559         cpo |= START_PADCONF_SAVE;
560         omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF);
561 
562         /* wait for the save to complete */
563         while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
564                  & PADCONF_SAVE_DONE))
565                 udelay(1);
566 
567         return 0;
568 }
569 
570 /**
571  * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
572  *
573  * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
574  * force disable IVA2 so that it does not prevent any low-power states.
575  */
576 static void __init omap3_ctrl_set_iva_bootmode_idle(void)
577 {
578         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
579                          OMAP343X_CONTROL_IVA2_BOOTMOD);
580 }
581 
582 /**
583  * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
584  *
585  * Sets up the pads controlling the stacked modem in such way that the
586  * device can enter idle.
587  */
588 static void __init omap3_ctrl_setup_d2d_padconf(void)
589 {
590         u16 mask, padconf;
591 
592         /*
593          * In a stand alone OMAP3430 where there is not a stacked
594          * modem for the D2D Idle Ack and D2D MStandby must be pulled
595          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
596          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
597          */
598         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
599         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
600         padconf |= mask;
601         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
602 
603         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
604         padconf |= mask;
605         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
606 }
607 
608 /**
609  * omap3_ctrl_init - does static initializations for control module
610  *
611  * Initializes system control module. This sets up the sysconfig autoidle,
612  * and sets up modem and iva2 so that they can be idled properly.
613  */
614 void __init omap3_ctrl_init(void)
615 {
616         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
617 
618         omap3_ctrl_set_iva_bootmode_idle();
619 
620         omap3_ctrl_setup_d2d_padconf();
621 }
622 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
623 
624 struct control_init_data {
625         int index;
626         s16 offset;
627 };
628 
629 static struct control_init_data ctrl_data = {
630         .index = TI_CLKM_CTRL,
631 };
632 
633 static const struct control_init_data omap2_ctrl_data = {
634         .index = TI_CLKM_CTRL,
635         .offset = -OMAP2_CONTROL_GENERAL,
636 };
637 
638 static const struct of_device_id omap_scrm_dt_match_table[] = {
639         { .compatible = "ti,am3-scm", .data = &ctrl_data },
640         { .compatible = "ti,am4-scm", .data = &ctrl_data },
641         { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
642         { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
643         { .compatible = "ti,dm814-scm", .data = &ctrl_data },
644         { .compatible = "ti,dm816-scrm", .data = &ctrl_data },
645         { .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
646         { .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
647         { .compatible = "ti,dra7-scm-core", .data = &ctrl_data },
648         { }
649 };
650 
651 /**
652  * omap2_control_base_init - initialize iomappings for the control driver
653  *
654  * Detects and initializes the iomappings for the control driver, based
655  * on the DT data. Returns 0 in success, negative error value
656  * otherwise.
657  */
658 int __init omap2_control_base_init(void)
659 {
660         struct device_node *np;
661         const struct of_device_id *match;
662         struct control_init_data *data;
663 
664         for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
665                 data = (struct control_init_data *)match->data;
666 
667                 omap2_ctrl_base = of_iomap(np, 0);
668                 if (!omap2_ctrl_base)
669                         return -ENOMEM;
670 
671                 omap2_ctrl_offset = data->offset;
672         }
673 
674         return 0;
675 }
676 
677 /**
678  * omap_control_init - low level init for the control driver
679  *
680  * Initializes the low level clock infrastructure for control driver.
681  * Returns 0 in success, negative error value in failure.
682  */
683 int __init omap_control_init(void)
684 {
685         struct device_node *np, *scm_conf;
686         const struct of_device_id *match;
687         const struct omap_prcm_init_data *data;
688         int ret;
689         struct regmap *syscon;
690 
691         for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
692                 data = match->data;
693 
694                 /*
695                  * Check if we have scm_conf node, if yes, use this to
696                  * access clock registers.
697                  */
698                 scm_conf = of_get_child_by_name(np, "scm_conf");
699 
700                 if (scm_conf) {
701                         syscon = syscon_node_to_regmap(scm_conf);
702 
703                         if (IS_ERR(syscon))
704                                 return PTR_ERR(syscon);
705 
706                         if (of_get_child_by_name(scm_conf, "clocks")) {
707                                 ret = omap2_clk_provider_init(scm_conf,
708                                                               data->index,
709                                                               syscon, NULL);
710                                 if (ret)
711                                         return ret;
712                         }
713                 } else {
714                         /* No scm_conf found, direct access */
715                         ret = omap2_clk_provider_init(np, data->index, NULL,
716                                                       omap2_ctrl_base);
717                         if (ret)
718                                 return ret;
719                 }
720         }
721 
722         return 0;
723 }
724 
725 /**
726  * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
727  *
728  * Legacy iomap init for clock provider. Needed only by legacy boot mode,
729  * where the base addresses are not parsed from DT, but still required
730  * by the clock driver to be setup properly.
731  */
732 void __init omap3_control_legacy_iomap_init(void)
733 {
734         omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
735 }
736 

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