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Linux/arch/arm/mach-omap2/omap4-common.c

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  1 /*
  2  * OMAP4 specific common source file.
  3  *
  4  * Copyright (C) 2010 Texas Instruments, Inc.
  5  * Author:
  6  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
  7  *
  8  *
  9  * This program is free software,you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 
 14 #include <linux/kernel.h>
 15 #include <linux/init.h>
 16 #include <linux/io.h>
 17 #include <linux/irq.h>
 18 #include <linux/irqchip.h>
 19 #include <linux/platform_device.h>
 20 #include <linux/memblock.h>
 21 #include <linux/of_irq.h>
 22 #include <linux/of_platform.h>
 23 #include <linux/export.h>
 24 #include <linux/irqchip/arm-gic.h>
 25 #include <linux/of_address.h>
 26 #include <linux/reboot.h>
 27 
 28 #include <asm/hardware/cache-l2x0.h>
 29 #include <asm/mach/map.h>
 30 #include <asm/memblock.h>
 31 #include <asm/smp_twd.h>
 32 
 33 #include "omap-wakeupgen.h"
 34 #include "soc.h"
 35 #include "iomap.h"
 36 #include "common.h"
 37 #include "mmc.h"
 38 #include "hsmmc.h"
 39 #include "prminst44xx.h"
 40 #include "prcm_mpu44xx.h"
 41 #include "omap4-sar-layout.h"
 42 #include "omap-secure.h"
 43 #include "sram.h"
 44 
 45 #ifdef CONFIG_CACHE_L2X0
 46 static void __iomem *l2cache_base;
 47 #endif
 48 
 49 static void __iomem *sar_ram_base;
 50 static void __iomem *gic_dist_base_addr;
 51 static void __iomem *twd_base;
 52 
 53 #define IRQ_LOCALTIMER          29
 54 
 55 #ifdef CONFIG_OMAP4_ERRATA_I688
 56 /* Used to implement memory barrier on DRAM path */
 57 #define OMAP4_DRAM_BARRIER_VA                   0xfe600000
 58 
 59 void __iomem *dram_sync, *sram_sync;
 60 
 61 static phys_addr_t paddr;
 62 static u32 size;
 63 
 64 void omap_bus_sync(void)
 65 {
 66         if (dram_sync && sram_sync) {
 67                 writel_relaxed(readl_relaxed(dram_sync), dram_sync);
 68                 writel_relaxed(readl_relaxed(sram_sync), sram_sync);
 69                 isb();
 70         }
 71 }
 72 EXPORT_SYMBOL(omap_bus_sync);
 73 
 74 /* Steal one page physical memory for barrier implementation */
 75 int __init omap_barrier_reserve_memblock(void)
 76 {
 77 
 78         size = ALIGN(PAGE_SIZE, SZ_1M);
 79         paddr = arm_memblock_steal(size, SZ_1M);
 80 
 81         return 0;
 82 }
 83 
 84 void __init omap_barriers_init(void)
 85 {
 86         struct map_desc dram_io_desc[1];
 87 
 88         dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
 89         dram_io_desc[0].pfn = __phys_to_pfn(paddr);
 90         dram_io_desc[0].length = size;
 91         dram_io_desc[0].type = MT_MEMORY_SO;
 92         iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
 93         dram_sync = (void __iomem *) dram_io_desc[0].virtual;
 94         sram_sync = (void __iomem *) OMAP4_SRAM_VA;
 95 
 96         pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
 97                 (long long) paddr, dram_io_desc[0].virtual);
 98 
 99 }
100 #else
101 void __init omap_barriers_init(void)
102 {}
103 #endif
104 
105 void __init gic_init_irq(void)
106 {
107         void __iomem *omap_irq_base;
108 
109         /* Static mapping, never released */
110         gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
111         BUG_ON(!gic_dist_base_addr);
112 
113         twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
114         BUG_ON(!twd_base);
115 
116         /* Static mapping, never released */
117         omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
118         BUG_ON(!omap_irq_base);
119 
120         omap_wakeupgen_init();
121 
122         gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
123 }
124 
125 void gic_dist_disable(void)
126 {
127         if (gic_dist_base_addr)
128                 __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
129 }
130 
131 bool gic_dist_disabled(void)
132 {
133         return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
134 }
135 
136 void gic_timer_retrigger(void)
137 {
138         u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
139         u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
140         u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
141 
142         if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
143                 /*
144                  * The local timer interrupt got lost while the distributor was
145                  * disabled.  Ack the pending interrupt, and retrigger it.
146                  */
147                 pr_warn("%s: lost localtimer interrupt\n", __func__);
148                 __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
149                 if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
150                         __raw_writel(1, twd_base + TWD_TIMER_COUNTER);
151                         twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
152                         __raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
153                 }
154         }
155 }
156 
157 #ifdef CONFIG_CACHE_L2X0
158 
159 void __iomem *omap4_get_l2cache_base(void)
160 {
161         return l2cache_base;
162 }
163 
164 static void omap4_l2x0_disable(void)
165 {
166         outer_flush_all();
167         /* Disable PL310 L2 Cache controller */
168         omap_smc1(0x102, 0x0);
169 }
170 
171 static void omap4_l2x0_set_debug(unsigned long val)
172 {
173         /* Program PL310 L2 Cache controller debug register */
174         omap_smc1(0x100, val);
175 }
176 
177 static int __init omap_l2_cache_init(void)
178 {
179         u32 aux_ctrl = 0;
180 
181         /*
182          * To avoid code running on other OMAPs in
183          * multi-omap builds
184          */
185         if (!cpu_is_omap44xx())
186                 return -ENODEV;
187 
188         /* Static mapping, never released */
189         l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
190         if (WARN_ON(!l2cache_base))
191                 return -ENOMEM;
192 
193         /*
194          * 16-way associativity, parity disabled
195          * Way size - 32KB (es1.0)
196          * Way size - 64KB (es2.0 +)
197          */
198         aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
199                         (0x1 << 25) |
200                         (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
201                         (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
202 
203         if (omap_rev() == OMAP4430_REV_ES1_0) {
204                 aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
205         } else {
206                 aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
207                         (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
208                         (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
209                         (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
210                         (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
211         }
212         if (omap_rev() != OMAP4430_REV_ES1_0)
213                 omap_smc1(0x109, aux_ctrl);
214 
215         /* Enable PL310 L2 Cache controller */
216         omap_smc1(0x102, 0x1);
217 
218         if (of_have_populated_dt())
219                 l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
220         else
221                 l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
222 
223         /*
224          * Override default outer_cache.disable with a OMAP4
225          * specific one
226         */
227         outer_cache.disable = omap4_l2x0_disable;
228         outer_cache.set_debug = omap4_l2x0_set_debug;
229 
230         return 0;
231 }
232 omap_early_initcall(omap_l2_cache_init);
233 #endif
234 
235 void __iomem *omap4_get_sar_ram_base(void)
236 {
237         return sar_ram_base;
238 }
239 
240 /*
241  * SAR RAM used to save and restore the HW
242  * context in low power modes
243  */
244 static int __init omap4_sar_ram_init(void)
245 {
246         unsigned long sar_base;
247 
248         /*
249          * To avoid code running on other OMAPs in
250          * multi-omap builds
251          */
252         if (cpu_is_omap44xx())
253                 sar_base = OMAP44XX_SAR_RAM_BASE;
254         else if (soc_is_omap54xx())
255                 sar_base = OMAP54XX_SAR_RAM_BASE;
256         else
257                 return -ENOMEM;
258 
259         /* Static mapping, never released */
260         sar_ram_base = ioremap(sar_base, SZ_16K);
261         if (WARN_ON(!sar_ram_base))
262                 return -ENOMEM;
263 
264         return 0;
265 }
266 omap_early_initcall(omap4_sar_ram_init);
267 
268 void __init omap_gic_of_init(void)
269 {
270         struct device_node *np;
271 
272         /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
273         if (!cpu_is_omap446x())
274                 goto skip_errata_init;
275 
276         np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
277         gic_dist_base_addr = of_iomap(np, 0);
278         WARN_ON(!gic_dist_base_addr);
279 
280         np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
281         twd_base = of_iomap(np, 0);
282         WARN_ON(!twd_base);
283 
284 skip_errata_init:
285         omap_wakeupgen_init();
286         irqchip_init();
287 }
288 
289 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
290 static int omap4_twl6030_hsmmc_late_init(struct device *dev)
291 {
292         int irq = 0;
293         struct platform_device *pdev = container_of(dev,
294                                 struct platform_device, dev);
295         struct omap_mmc_platform_data *pdata = dev->platform_data;
296 
297         /* Setting MMC1 Card detect Irq */
298         if (pdev->id == 0) {
299                 irq = twl6030_mmc_card_detect_config();
300                 if (irq < 0) {
301                         dev_err(dev, "%s: Error card detect config(%d)\n",
302                                 __func__, irq);
303                         return irq;
304                 }
305                 pdata->slots[0].card_detect_irq = irq;
306                 pdata->slots[0].card_detect = twl6030_mmc_card_detect;
307         }
308         return 0;
309 }
310 
311 static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
312 {
313         struct omap_mmc_platform_data *pdata;
314 
315         /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
316         if (!dev) {
317                 pr_err("Failed %s\n", __func__);
318                 return;
319         }
320         pdata = dev->platform_data;
321         pdata->init =   omap4_twl6030_hsmmc_late_init;
322 }
323 
324 int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
325 {
326         struct omap2_hsmmc_info *c;
327 
328         omap_hsmmc_init(controllers);
329         for (c = controllers; c->mmc; c++) {
330                 /* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
331                 if (!c->pdev)
332                         continue;
333                 omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
334         }
335 
336         return 0;
337 }
338 #else
339 int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
340 {
341         return 0;
342 }
343 #endif
344 

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