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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

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  1 /*
  2  *
  3  * Copyright (C) 2013 Texas Instruments Incorporated
  4  *
  5  * Hwmod common for AM335x and AM43x
  6  *
  7  * This program is free software; you can redistribute it and/or
  8  * modify it under the terms of the GNU General Public License as
  9  * published by the Free Software Foundation version 2.
 10  *
 11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 12  * kind, whether express or implied; without even the implied warranty
 13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 14  * GNU General Public License for more details.
 15  */
 16 
 17 #include <linux/types.h>
 18 
 19 #include <linux/platform_data/hsmmc-omap.h>
 20 #include "omap_hwmod.h"
 21 #include "i2c.h"
 22 #include "wd_timer.h"
 23 #include "cm33xx.h"
 24 #include "prm33xx.h"
 25 #include "omap_hwmod_33xx_43xx_common_data.h"
 26 #include "prcm43xx.h"
 27 #include "common.h"
 28 
 29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
 30 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
 31 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
 32 #define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
 33 
 34 /*
 35  * 'l3' class
 36  * instance(s): l3_main, l3_s, l3_instr
 37  */
 38 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
 39         .name           = "l3",
 40 };
 41 
 42 struct omap_hwmod am33xx_l3_main_hwmod = {
 43         .name           = "l3_main",
 44         .class          = &am33xx_l3_hwmod_class,
 45         .clkdm_name     = "l3_clkdm",
 46         .flags          = HWMOD_INIT_NO_IDLE,
 47         .main_clk       = "l3_gclk",
 48         .prcm           = {
 49                 .omap4  = {
 50                         .modulemode     = MODULEMODE_SWCTRL,
 51                 },
 52         },
 53 };
 54 
 55 /* l3_s */
 56 struct omap_hwmod am33xx_l3_s_hwmod = {
 57         .name           = "l3_s",
 58         .class          = &am33xx_l3_hwmod_class,
 59         .clkdm_name     = "l3s_clkdm",
 60 };
 61 
 62 /* l3_instr */
 63 struct omap_hwmod am33xx_l3_instr_hwmod = {
 64         .name           = "l3_instr",
 65         .class          = &am33xx_l3_hwmod_class,
 66         .clkdm_name     = "l3_clkdm",
 67         .flags          = HWMOD_INIT_NO_IDLE,
 68         .main_clk       = "l3_gclk",
 69         .prcm           = {
 70                 .omap4  = {
 71                         .modulemode     = MODULEMODE_SWCTRL,
 72                 },
 73         },
 74 };
 75 
 76 /*
 77  * 'l4' class
 78  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
 79  */
 80 struct omap_hwmod_class am33xx_l4_hwmod_class = {
 81         .name           = "l4",
 82 };
 83 
 84 /* l4_ls */
 85 struct omap_hwmod am33xx_l4_ls_hwmod = {
 86         .name           = "l4_ls",
 87         .class          = &am33xx_l4_hwmod_class,
 88         .clkdm_name     = "l4ls_clkdm",
 89         .flags          = HWMOD_INIT_NO_IDLE,
 90         .main_clk       = "l4ls_gclk",
 91         .prcm           = {
 92                 .omap4  = {
 93                         .modulemode     = MODULEMODE_SWCTRL,
 94                 },
 95         },
 96 };
 97 
 98 /* l4_wkup */
 99 struct omap_hwmod am33xx_l4_wkup_hwmod = {
100         .name           = "l4_wkup",
101         .class          = &am33xx_l4_hwmod_class,
102         .clkdm_name     = "l4_wkup_clkdm",
103         .flags          = HWMOD_INIT_NO_IDLE,
104         .prcm           = {
105                 .omap4  = {
106                         .modulemode     = MODULEMODE_SWCTRL,
107                 },
108         },
109 };
110 
111 /*
112  * 'mpu' class
113  */
114 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
115         .name   = "mpu",
116 };
117 
118 struct omap_hwmod am33xx_mpu_hwmod = {
119         .name           = "mpu",
120         .class          = &am33xx_mpu_hwmod_class,
121         .clkdm_name     = "mpu_clkdm",
122         .flags          = HWMOD_INIT_NO_IDLE,
123         .main_clk       = "dpll_mpu_m2_ck",
124         .prcm           = {
125                 .omap4  = {
126                         .modulemode     = MODULEMODE_SWCTRL,
127                 },
128         },
129 };
130 
131 /*
132  * 'wakeup m3' class
133  * Wakeup controller sub-system under wakeup domain
134  */
135 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
136         .name           = "wkup_m3",
137 };
138 
139 /*
140  * 'pru-icss' class
141  * Programmable Real-Time Unit and Industrial Communication Subsystem
142  */
143 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
144         .name   = "pruss",
145 };
146 
147 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
148         { .name = "pruss", .rst_shift = 1 },
149 };
150 
151 /* pru-icss */
152 /* Pseudo hwmod for reset control purpose only */
153 struct omap_hwmod am33xx_pruss_hwmod = {
154         .name           = "pruss",
155         .class          = &am33xx_pruss_hwmod_class,
156         .clkdm_name     = "pruss_ocp_clkdm",
157         .main_clk       = "pruss_ocp_gclk",
158         .prcm           = {
159                 .omap4  = {
160                         .modulemode     = MODULEMODE_SWCTRL,
161                 },
162         },
163         .rst_lines      = am33xx_pruss_resets,
164         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
165 };
166 
167 /* gfx */
168 /* Pseudo hwmod for reset control purpose only */
169 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
170         .name   = "gfx",
171 };
172 
173 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
174         { .name = "gfx", .rst_shift = 0, .st_shift = 0},
175 };
176 
177 struct omap_hwmod am33xx_gfx_hwmod = {
178         .name           = "gfx",
179         .class          = &am33xx_gfx_hwmod_class,
180         .clkdm_name     = "gfx_l3_clkdm",
181         .main_clk       = "gfx_fck_div_ck",
182         .prcm           = {
183                 .omap4  = {
184                         .modulemode     = MODULEMODE_SWCTRL,
185                 },
186         },
187         .rst_lines      = am33xx_gfx_resets,
188         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
189 };
190 
191 /*
192  * 'prcm' class
193  * power and reset manager (whole prcm infrastructure)
194  */
195 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
196         .name   = "prcm",
197 };
198 
199 /* prcm */
200 struct omap_hwmod am33xx_prcm_hwmod = {
201         .name           = "prcm",
202         .class          = &am33xx_prcm_hwmod_class,
203         .clkdm_name     = "l4_wkup_clkdm",
204 };
205 
206 /*
207  * 'emif' class
208  * instance(s): emif
209  */
210 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
211         .rev_offs       = 0x0000,
212 };
213 
214 struct omap_hwmod_class am33xx_emif_hwmod_class = {
215         .name           = "emif",
216         .sysc           = &am33xx_emif_sysc,
217 };
218 
219 /*
220  * 'aes0' class
221  */
222 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
223         .rev_offs       = 0x80,
224         .sysc_offs      = 0x84,
225         .syss_offs      = 0x88,
226         .sysc_flags     = SYSS_HAS_RESET_STATUS,
227 };
228 
229 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
230         .name           = "aes0",
231         .sysc           = &am33xx_aes0_sysc,
232 };
233 
234 struct omap_hwmod am33xx_aes0_hwmod = {
235         .name           = "aes",
236         .class          = &am33xx_aes0_hwmod_class,
237         .clkdm_name     = "l3_clkdm",
238         .main_clk       = "aes0_fck",
239         .prcm           = {
240                 .omap4  = {
241                         .modulemode     = MODULEMODE_SWCTRL,
242                 },
243         },
244 };
245 
246 /* sha0 HIB2 (the 'P' (public) device) */
247 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
248         .rev_offs       = 0x100,
249         .sysc_offs      = 0x110,
250         .syss_offs      = 0x114,
251         .sysc_flags     = SYSS_HAS_RESET_STATUS,
252 };
253 
254 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
255         .name           = "sha0",
256         .sysc           = &am33xx_sha0_sysc,
257 };
258 
259 struct omap_hwmod am33xx_sha0_hwmod = {
260         .name           = "sham",
261         .class          = &am33xx_sha0_hwmod_class,
262         .clkdm_name     = "l3_clkdm",
263         .main_clk       = "l3_gclk",
264         .prcm           = {
265                 .omap4  = {
266                         .modulemode     = MODULEMODE_SWCTRL,
267                 },
268         },
269 };
270 
271 /* rng */
272 static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
273         .rev_offs       = 0x1fe0,
274         .sysc_offs      = 0x1fe4,
275         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
276         .idlemodes      = SIDLE_FORCE | SIDLE_NO,
277         .sysc_fields    = &omap_hwmod_sysc_type1,
278 };
279 
280 static struct omap_hwmod_class am33xx_rng_hwmod_class = {
281         .name           = "rng",
282         .sysc           = &am33xx_rng_sysc,
283 };
284 
285 struct omap_hwmod am33xx_rng_hwmod = {
286         .name           = "rng",
287         .class          = &am33xx_rng_hwmod_class,
288         .clkdm_name     = "l4ls_clkdm",
289         .flags          = HWMOD_SWSUP_SIDLE,
290         .main_clk       = "rng_fck",
291         .prcm           = {
292                 .omap4  = {
293                         .modulemode     = MODULEMODE_SWCTRL,
294                 },
295         },
296 };
297 
298 /* ocmcram */
299 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
300         .name = "ocmcram",
301 };
302 
303 struct omap_hwmod am33xx_ocmcram_hwmod = {
304         .name           = "ocmcram",
305         .class          = &am33xx_ocmcram_hwmod_class,
306         .clkdm_name     = "l3_clkdm",
307         .flags          = HWMOD_INIT_NO_IDLE,
308         .main_clk       = "l3_gclk",
309         .prcm           = {
310                 .omap4  = {
311                         .modulemode     = MODULEMODE_SWCTRL,
312                 },
313         },
314 };
315 
316 /* 'smartreflex' class */
317 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
318         .name           = "smartreflex",
319 };
320 
321 /* smartreflex0 */
322 struct omap_hwmod am33xx_smartreflex0_hwmod = {
323         .name           = "smartreflex0",
324         .class          = &am33xx_smartreflex_hwmod_class,
325         .clkdm_name     = "l4_wkup_clkdm",
326         .main_clk       = "smartreflex0_fck",
327         .prcm           = {
328                 .omap4  = {
329                         .modulemode     = MODULEMODE_SWCTRL,
330                 },
331         },
332 };
333 
334 /* smartreflex1 */
335 struct omap_hwmod am33xx_smartreflex1_hwmod = {
336         .name           = "smartreflex1",
337         .class          = &am33xx_smartreflex_hwmod_class,
338         .clkdm_name     = "l4_wkup_clkdm",
339         .main_clk       = "smartreflex1_fck",
340         .prcm           = {
341                 .omap4  = {
342                         .modulemode     = MODULEMODE_SWCTRL,
343                 },
344         },
345 };
346 
347 /*
348  * 'control' module class
349  */
350 struct omap_hwmod_class am33xx_control_hwmod_class = {
351         .name           = "control",
352 };
353 
354 /*
355  * 'cpgmac' class
356  * cpsw/cpgmac sub system
357  */
358 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
359         .rev_offs       = 0x0,
360         .sysc_offs      = 0x8,
361         .syss_offs      = 0x4,
362         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
363                            SYSS_HAS_RESET_STATUS),
364         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
365                            MSTANDBY_NO),
366         .sysc_fields    = &omap_hwmod_sysc_type3,
367 };
368 
369 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
370         .name           = "cpgmac0",
371         .sysc           = &am33xx_cpgmac_sysc,
372 };
373 
374 struct omap_hwmod am33xx_cpgmac0_hwmod = {
375         .name           = "cpgmac0",
376         .class          = &am33xx_cpgmac0_hwmod_class,
377         .clkdm_name     = "cpsw_125mhz_clkdm",
378         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
379         .main_clk       = "cpsw_125mhz_gclk",
380         .mpu_rt_idx     = 1,
381         .prcm           = {
382                 .omap4  = {
383                         .modulemode     = MODULEMODE_SWCTRL,
384                 },
385         },
386 };
387 
388 /*
389  * mdio class
390  */
391 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
392         .name           = "davinci_mdio",
393 };
394 
395 struct omap_hwmod am33xx_mdio_hwmod = {
396         .name           = "davinci_mdio",
397         .class          = &am33xx_mdio_hwmod_class,
398         .clkdm_name     = "cpsw_125mhz_clkdm",
399         .main_clk       = "cpsw_125mhz_gclk",
400 };
401 
402 /*
403  * dcan class
404  */
405 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
406         .name = "d_can",
407 };
408 
409 /* dcan0 */
410 struct omap_hwmod am33xx_dcan0_hwmod = {
411         .name           = "d_can0",
412         .class          = &am33xx_dcan_hwmod_class,
413         .clkdm_name     = "l4ls_clkdm",
414         .main_clk       = "dcan0_fck",
415         .prcm           = {
416                 .omap4  = {
417                         .modulemode     = MODULEMODE_SWCTRL,
418                 },
419         },
420 };
421 
422 /* dcan1 */
423 struct omap_hwmod am33xx_dcan1_hwmod = {
424         .name           = "d_can1",
425         .class          = &am33xx_dcan_hwmod_class,
426         .clkdm_name     = "l4ls_clkdm",
427         .main_clk       = "dcan1_fck",
428         .prcm           = {
429                 .omap4  = {
430                         .modulemode     = MODULEMODE_SWCTRL,
431                 },
432         },
433 };
434 
435 /* elm */
436 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
437         .rev_offs       = 0x0000,
438         .sysc_offs      = 0x0010,
439         .syss_offs      = 0x0014,
440         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
441                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
442                         SYSS_HAS_RESET_STATUS),
443         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
444         .sysc_fields    = &omap_hwmod_sysc_type1,
445 };
446 
447 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
448         .name           = "elm",
449         .sysc           = &am33xx_elm_sysc,
450 };
451 
452 struct omap_hwmod am33xx_elm_hwmod = {
453         .name           = "elm",
454         .class          = &am33xx_elm_hwmod_class,
455         .clkdm_name     = "l4ls_clkdm",
456         .main_clk       = "l4ls_gclk",
457         .prcm           = {
458                 .omap4  = {
459                         .modulemode     = MODULEMODE_SWCTRL,
460                 },
461         },
462 };
463 
464 /* pwmss  */
465 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
466         .rev_offs       = 0x0,
467         .sysc_offs      = 0x4,
468         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
469         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
470                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
471                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
472         .sysc_fields    = &omap_hwmod_sysc_type2,
473 };
474 
475 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
476         .name           = "epwmss",
477         .sysc           = &am33xx_epwmss_sysc,
478 };
479 
480 /* epwmss0 */
481 struct omap_hwmod am33xx_epwmss0_hwmod = {
482         .name           = "epwmss0",
483         .class          = &am33xx_epwmss_hwmod_class,
484         .clkdm_name     = "l4ls_clkdm",
485         .main_clk       = "l4ls_gclk",
486         .prcm           = {
487                 .omap4  = {
488                         .modulemode     = MODULEMODE_SWCTRL,
489                 },
490         },
491 };
492 
493 /* epwmss1 */
494 struct omap_hwmod am33xx_epwmss1_hwmod = {
495         .name           = "epwmss1",
496         .class          = &am33xx_epwmss_hwmod_class,
497         .clkdm_name     = "l4ls_clkdm",
498         .main_clk       = "l4ls_gclk",
499         .prcm           = {
500                 .omap4  = {
501                         .modulemode     = MODULEMODE_SWCTRL,
502                 },
503         },
504 };
505 
506 /* epwmss2 */
507 struct omap_hwmod am33xx_epwmss2_hwmod = {
508         .name           = "epwmss2",
509         .class          = &am33xx_epwmss_hwmod_class,
510         .clkdm_name     = "l4ls_clkdm",
511         .main_clk       = "l4ls_gclk",
512         .prcm           = {
513                 .omap4  = {
514                         .modulemode     = MODULEMODE_SWCTRL,
515                 },
516         },
517 };
518 
519 /*
520  * 'gpio' class: for gpio 0,1,2,3
521  */
522 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
523         .rev_offs       = 0x0000,
524         .sysc_offs      = 0x0010,
525         .syss_offs      = 0x0114,
526         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
527                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
528                           SYSS_HAS_RESET_STATUS),
529         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
530                           SIDLE_SMART_WKUP),
531         .sysc_fields    = &omap_hwmod_sysc_type1,
532 };
533 
534 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
535         .name           = "gpio",
536         .sysc           = &am33xx_gpio_sysc,
537         .rev            = 2,
538 };
539 
540 /* gpio1 */
541 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
542         { .role = "dbclk", .clk = "gpio1_dbclk" },
543 };
544 
545 struct omap_hwmod am33xx_gpio1_hwmod = {
546         .name           = "gpio2",
547         .class          = &am33xx_gpio_hwmod_class,
548         .clkdm_name     = "l4ls_clkdm",
549         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
550         .main_clk       = "l4ls_gclk",
551         .prcm           = {
552                 .omap4  = {
553                         .modulemode     = MODULEMODE_SWCTRL,
554                 },
555         },
556         .opt_clks       = gpio1_opt_clks,
557         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
558 };
559 
560 /* gpio2 */
561 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
562         { .role = "dbclk", .clk = "gpio2_dbclk" },
563 };
564 
565 struct omap_hwmod am33xx_gpio2_hwmod = {
566         .name           = "gpio3",
567         .class          = &am33xx_gpio_hwmod_class,
568         .clkdm_name     = "l4ls_clkdm",
569         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
570         .main_clk       = "l4ls_gclk",
571         .prcm           = {
572                 .omap4  = {
573                         .modulemode     = MODULEMODE_SWCTRL,
574                 },
575         },
576         .opt_clks       = gpio2_opt_clks,
577         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
578 };
579 
580 /* gpio3 */
581 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
582         { .role = "dbclk", .clk = "gpio3_dbclk" },
583 };
584 
585 struct omap_hwmod am33xx_gpio3_hwmod = {
586         .name           = "gpio4",
587         .class          = &am33xx_gpio_hwmod_class,
588         .clkdm_name     = "l4ls_clkdm",
589         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
590         .main_clk       = "l4ls_gclk",
591         .prcm           = {
592                 .omap4  = {
593                         .modulemode     = MODULEMODE_SWCTRL,
594                 },
595         },
596         .opt_clks       = gpio3_opt_clks,
597         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
598 };
599 
600 /* gpmc */
601 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
602         .rev_offs       = 0x0,
603         .sysc_offs      = 0x10,
604         .syss_offs      = 0x14,
605         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
606                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
607         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
608         .sysc_fields    = &omap_hwmod_sysc_type1,
609 };
610 
611 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
612         .name           = "gpmc",
613         .sysc           = &gpmc_sysc,
614 };
615 
616 struct omap_hwmod am33xx_gpmc_hwmod = {
617         .name           = "gpmc",
618         .class          = &am33xx_gpmc_hwmod_class,
619         .clkdm_name     = "l3s_clkdm",
620         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
621         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
622         .main_clk       = "l3s_gclk",
623         .prcm           = {
624                 .omap4  = {
625                         .modulemode     = MODULEMODE_SWCTRL,
626                 },
627         },
628 };
629 
630 /* 'i2c' class */
631 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
632         .rev_offs       = 0,
633         .sysc_offs      = 0x0010,
634         .syss_offs      = 0x0090,
635         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
636                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
637                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
638         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
639                           SIDLE_SMART_WKUP),
640         .sysc_fields    = &omap_hwmod_sysc_type1,
641 };
642 
643 static struct omap_hwmod_class i2c_class = {
644         .name           = "i2c",
645         .sysc           = &am33xx_i2c_sysc,
646         .rev            = OMAP_I2C_IP_VERSION_2,
647         .reset          = &omap_i2c_reset,
648 };
649 
650 /* i2c1 */
651 struct omap_hwmod am33xx_i2c1_hwmod = {
652         .name           = "i2c1",
653         .class          = &i2c_class,
654         .clkdm_name     = "l4_wkup_clkdm",
655         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
656         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
657         .prcm           = {
658                 .omap4  = {
659                         .modulemode     = MODULEMODE_SWCTRL,
660                 },
661         },
662 };
663 
664 /* i2c1 */
665 struct omap_hwmod am33xx_i2c2_hwmod = {
666         .name           = "i2c2",
667         .class          = &i2c_class,
668         .clkdm_name     = "l4ls_clkdm",
669         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
670         .main_clk       = "dpll_per_m2_div4_ck",
671         .prcm           = {
672                 .omap4 = {
673                         .modulemode     = MODULEMODE_SWCTRL,
674                 },
675         },
676 };
677 
678 /* i2c3 */
679 struct omap_hwmod am33xx_i2c3_hwmod = {
680         .name           = "i2c3",
681         .class          = &i2c_class,
682         .clkdm_name     = "l4ls_clkdm",
683         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
684         .main_clk       = "dpll_per_m2_div4_ck",
685         .prcm           = {
686                 .omap4  = {
687                         .modulemode     = MODULEMODE_SWCTRL,
688                 },
689         },
690 };
691 
692 /*
693  * 'mailbox' class
694  * mailbox module allowing communication between the on-chip processors using a
695  * queued mailbox-interrupt mechanism.
696  */
697 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
698         .rev_offs       = 0x0000,
699         .sysc_offs      = 0x0010,
700         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
701                           SYSC_HAS_SOFTRESET),
702         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
703         .sysc_fields    = &omap_hwmod_sysc_type2,
704 };
705 
706 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
707         .name   = "mailbox",
708         .sysc   = &am33xx_mailbox_sysc,
709 };
710 
711 struct omap_hwmod am33xx_mailbox_hwmod = {
712         .name           = "mailbox",
713         .class          = &am33xx_mailbox_hwmod_class,
714         .clkdm_name     = "l4ls_clkdm",
715         .main_clk       = "l4ls_gclk",
716         .prcm = {
717                 .omap4 = {
718                         .modulemode     = MODULEMODE_SWCTRL,
719                 },
720         },
721 };
722 
723 /*
724  * 'mcasp' class
725  */
726 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
727         .rev_offs       = 0x0,
728         .sysc_offs      = 0x4,
729         .sysc_flags     = SYSC_HAS_SIDLEMODE,
730         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
731         .sysc_fields    = &omap_hwmod_sysc_type3,
732 };
733 
734 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
735         .name           = "mcasp",
736         .sysc           = &am33xx_mcasp_sysc,
737 };
738 
739 /* mcasp0 */
740 struct omap_hwmod am33xx_mcasp0_hwmod = {
741         .name           = "mcasp0",
742         .class          = &am33xx_mcasp_hwmod_class,
743         .clkdm_name     = "l3s_clkdm",
744         .main_clk       = "mcasp0_fck",
745         .prcm           = {
746                 .omap4  = {
747                         .modulemode     = MODULEMODE_SWCTRL,
748                 },
749         },
750 };
751 
752 /* mcasp1 */
753 struct omap_hwmod am33xx_mcasp1_hwmod = {
754         .name           = "mcasp1",
755         .class          = &am33xx_mcasp_hwmod_class,
756         .clkdm_name     = "l3s_clkdm",
757         .main_clk       = "mcasp1_fck",
758         .prcm           = {
759                 .omap4  = {
760                         .modulemode     = MODULEMODE_SWCTRL,
761                 },
762         },
763 };
764 
765 /* 'mmc' class */
766 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
767         .rev_offs       = 0x2fc,
768         .sysc_offs      = 0x110,
769         .syss_offs      = 0x114,
770         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
771                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
772                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
773         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
774         .sysc_fields    = &omap_hwmod_sysc_type1,
775 };
776 
777 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
778         .name           = "mmc",
779         .sysc           = &am33xx_mmc_sysc,
780 };
781 
782 /* mmc0 */
783 static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = {
784         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
785 };
786 
787 struct omap_hwmod am33xx_mmc0_hwmod = {
788         .name           = "mmc1",
789         .class          = &am33xx_mmc_hwmod_class,
790         .clkdm_name     = "l4ls_clkdm",
791         .main_clk       = "mmc_clk",
792         .prcm           = {
793                 .omap4  = {
794                         .modulemode     = MODULEMODE_SWCTRL,
795                 },
796         },
797         .dev_attr       = &am33xx_mmc0_dev_attr,
798 };
799 
800 /* mmc1 */
801 static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = {
802         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
803 };
804 
805 struct omap_hwmod am33xx_mmc1_hwmod = {
806         .name           = "mmc2",
807         .class          = &am33xx_mmc_hwmod_class,
808         .clkdm_name     = "l4ls_clkdm",
809         .main_clk       = "mmc_clk",
810         .prcm           = {
811                 .omap4  = {
812                         .modulemode     = MODULEMODE_SWCTRL,
813                 },
814         },
815         .dev_attr       = &am33xx_mmc1_dev_attr,
816 };
817 
818 /* mmc2 */
819 static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = {
820         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
821 };
822 struct omap_hwmod am33xx_mmc2_hwmod = {
823         .name           = "mmc3",
824         .class          = &am33xx_mmc_hwmod_class,
825         .clkdm_name     = "l3s_clkdm",
826         .main_clk       = "mmc_clk",
827         .prcm           = {
828                 .omap4  = {
829                         .modulemode     = MODULEMODE_SWCTRL,
830                 },
831         },
832         .dev_attr       = &am33xx_mmc2_dev_attr,
833 };
834 
835 /*
836  * 'rtc' class
837  * rtc subsystem
838  */
839 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
840         .rev_offs       = 0x0074,
841         .sysc_offs      = 0x0078,
842         .sysc_flags     = SYSC_HAS_SIDLEMODE,
843         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
844                           SIDLE_SMART | SIDLE_SMART_WKUP),
845         .sysc_fields    = &omap_hwmod_sysc_type3,
846 };
847 
848 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
849         .name           = "rtc",
850         .sysc           = &am33xx_rtc_sysc,
851         .unlock         = &omap_hwmod_rtc_unlock,
852         .lock           = &omap_hwmod_rtc_lock,
853 };
854 
855 struct omap_hwmod am33xx_rtc_hwmod = {
856         .name           = "rtc",
857         .class          = &am33xx_rtc_hwmod_class,
858         .clkdm_name     = "l4_rtc_clkdm",
859         .main_clk       = "clk_32768_ck",
860         .prcm           = {
861                 .omap4  = {
862                         .modulemode     = MODULEMODE_SWCTRL,
863                 },
864         },
865 };
866 
867 /* 'spi' class */
868 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
869         .rev_offs       = 0x0000,
870         .sysc_offs      = 0x0110,
871         .syss_offs      = 0x0114,
872         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
873                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
874                           SYSS_HAS_RESET_STATUS),
875         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
876         .sysc_fields    = &omap_hwmod_sysc_type1,
877 };
878 
879 struct omap_hwmod_class am33xx_spi_hwmod_class = {
880         .name           = "mcspi",
881         .sysc           = &am33xx_mcspi_sysc,
882 };
883 
884 /* spi0 */
885 struct omap_hwmod am33xx_spi0_hwmod = {
886         .name           = "spi0",
887         .class          = &am33xx_spi_hwmod_class,
888         .clkdm_name     = "l4ls_clkdm",
889         .main_clk       = "dpll_per_m2_div4_ck",
890         .prcm           = {
891                 .omap4  = {
892                         .modulemode     = MODULEMODE_SWCTRL,
893                 },
894         },
895 };
896 
897 /* spi1 */
898 struct omap_hwmod am33xx_spi1_hwmod = {
899         .name           = "spi1",
900         .class          = &am33xx_spi_hwmod_class,
901         .clkdm_name     = "l4ls_clkdm",
902         .main_clk       = "dpll_per_m2_div4_ck",
903         .prcm           = {
904                 .omap4  = {
905                         .modulemode     = MODULEMODE_SWCTRL,
906                 },
907         },
908 };
909 
910 /*
911  * 'spinlock' class
912  * spinlock provides hardware assistance for synchronizing the
913  * processes running on multiple processors
914  */
915 
916 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
917         .rev_offs       = 0x0000,
918         .sysc_offs      = 0x0010,
919         .syss_offs      = 0x0014,
920         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
921                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
922                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
923         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
924         .sysc_fields    = &omap_hwmod_sysc_type1,
925 };
926 
927 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
928         .name           = "spinlock",
929         .sysc           = &am33xx_spinlock_sysc,
930 };
931 
932 struct omap_hwmod am33xx_spinlock_hwmod = {
933         .name           = "spinlock",
934         .class          = &am33xx_spinlock_hwmod_class,
935         .clkdm_name     = "l4ls_clkdm",
936         .main_clk       = "l4ls_gclk",
937         .prcm           = {
938                 .omap4  = {
939                         .modulemode     = MODULEMODE_SWCTRL,
940                 },
941         },
942 };
943 
944 /* 'timer 2-7' class */
945 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
946         .rev_offs       = 0x0000,
947         .sysc_offs      = 0x0010,
948         .syss_offs      = 0x0014,
949         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
950         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
951                           SIDLE_SMART_WKUP),
952         .sysc_fields    = &omap_hwmod_sysc_type2,
953 };
954 
955 struct omap_hwmod_class am33xx_timer_hwmod_class = {
956         .name           = "timer",
957         .sysc           = &am33xx_timer_sysc,
958 };
959 
960 /* timer1 1ms */
961 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
962         .rev_offs       = 0x0000,
963         .sysc_offs      = 0x0010,
964         .syss_offs      = 0x0014,
965         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
966                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
967                         SYSS_HAS_RESET_STATUS),
968         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
969         .sysc_fields    = &omap_hwmod_sysc_type1,
970 };
971 
972 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
973         .name           = "timer",
974         .sysc           = &am33xx_timer1ms_sysc,
975 };
976 
977 struct omap_hwmod am33xx_timer1_hwmod = {
978         .name           = "timer1",
979         .class          = &am33xx_timer1ms_hwmod_class,
980         .clkdm_name     = "l4_wkup_clkdm",
981         .main_clk       = "timer1_fck",
982         .prcm           = {
983                 .omap4  = {
984                         .modulemode     = MODULEMODE_SWCTRL,
985                 },
986         },
987 };
988 
989 struct omap_hwmod am33xx_timer2_hwmod = {
990         .name           = "timer2",
991         .class          = &am33xx_timer_hwmod_class,
992         .clkdm_name     = "l4ls_clkdm",
993         .main_clk       = "timer2_fck",
994         .prcm           = {
995                 .omap4  = {
996                         .modulemode     = MODULEMODE_SWCTRL,
997                 },
998         },
999 };
1000 
1001 struct omap_hwmod am33xx_timer3_hwmod = {
1002         .name           = "timer3",
1003         .class          = &am33xx_timer_hwmod_class,
1004         .clkdm_name     = "l4ls_clkdm",
1005         .main_clk       = "timer3_fck",
1006         .prcm           = {
1007                 .omap4  = {
1008                         .modulemode     = MODULEMODE_SWCTRL,
1009                 },
1010         },
1011 };
1012 
1013 struct omap_hwmod am33xx_timer4_hwmod = {
1014         .name           = "timer4",
1015         .class          = &am33xx_timer_hwmod_class,
1016         .clkdm_name     = "l4ls_clkdm",
1017         .main_clk       = "timer4_fck",
1018         .prcm           = {
1019                 .omap4  = {
1020                         .modulemode     = MODULEMODE_SWCTRL,
1021                 },
1022         },
1023 };
1024 
1025 struct omap_hwmod am33xx_timer5_hwmod = {
1026         .name           = "timer5",
1027         .class          = &am33xx_timer_hwmod_class,
1028         .clkdm_name     = "l4ls_clkdm",
1029         .main_clk       = "timer5_fck",
1030         .prcm           = {
1031                 .omap4  = {
1032                         .modulemode     = MODULEMODE_SWCTRL,
1033                 },
1034         },
1035 };
1036 
1037 struct omap_hwmod am33xx_timer6_hwmod = {
1038         .name           = "timer6",
1039         .class          = &am33xx_timer_hwmod_class,
1040         .clkdm_name     = "l4ls_clkdm",
1041         .main_clk       = "timer6_fck",
1042         .prcm           = {
1043                 .omap4  = {
1044                         .modulemode     = MODULEMODE_SWCTRL,
1045                 },
1046         },
1047 };
1048 
1049 struct omap_hwmod am33xx_timer7_hwmod = {
1050         .name           = "timer7",
1051         .class          = &am33xx_timer_hwmod_class,
1052         .clkdm_name     = "l4ls_clkdm",
1053         .main_clk       = "timer7_fck",
1054         .prcm           = {
1055                 .omap4  = {
1056                         .modulemode     = MODULEMODE_SWCTRL,
1057                 },
1058         },
1059 };
1060 
1061 /* tpcc */
1062 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1063         .name           = "tpcc",
1064 };
1065 
1066 struct omap_hwmod am33xx_tpcc_hwmod = {
1067         .name           = "tpcc",
1068         .class          = &am33xx_tpcc_hwmod_class,
1069         .clkdm_name     = "l3_clkdm",
1070         .main_clk       = "l3_gclk",
1071         .prcm           = {
1072                 .omap4  = {
1073                         .modulemode     = MODULEMODE_SWCTRL,
1074                 },
1075         },
1076 };
1077 
1078 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1079         .rev_offs       = 0x0,
1080         .sysc_offs      = 0x10,
1081         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1082                           SYSC_HAS_MIDLEMODE),
1083         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1084         .sysc_fields    = &omap_hwmod_sysc_type2,
1085 };
1086 
1087 /* 'tptc' class */
1088 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1089         .name           = "tptc",
1090         .sysc           = &am33xx_tptc_sysc,
1091 };
1092 
1093 /* tptc0 */
1094 struct omap_hwmod am33xx_tptc0_hwmod = {
1095         .name           = "tptc0",
1096         .class          = &am33xx_tptc_hwmod_class,
1097         .clkdm_name     = "l3_clkdm",
1098         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1099         .main_clk       = "l3_gclk",
1100         .prcm           = {
1101                 .omap4  = {
1102                         .modulemode     = MODULEMODE_SWCTRL,
1103                 },
1104         },
1105 };
1106 
1107 /* tptc1 */
1108 struct omap_hwmod am33xx_tptc1_hwmod = {
1109         .name           = "tptc1",
1110         .class          = &am33xx_tptc_hwmod_class,
1111         .clkdm_name     = "l3_clkdm",
1112         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1113         .main_clk       = "l3_gclk",
1114         .prcm           = {
1115                 .omap4  = {
1116                         .modulemode     = MODULEMODE_SWCTRL,
1117                 },
1118         },
1119 };
1120 
1121 /* tptc2 */
1122 struct omap_hwmod am33xx_tptc2_hwmod = {
1123         .name           = "tptc2",
1124         .class          = &am33xx_tptc_hwmod_class,
1125         .clkdm_name     = "l3_clkdm",
1126         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1127         .main_clk       = "l3_gclk",
1128         .prcm           = {
1129                 .omap4  = {
1130                         .modulemode     = MODULEMODE_SWCTRL,
1131                 },
1132         },
1133 };
1134 
1135 /* 'uart' class */
1136 static struct omap_hwmod_class_sysconfig uart_sysc = {
1137         .rev_offs       = 0x50,
1138         .sysc_offs      = 0x54,
1139         .syss_offs      = 0x58,
1140         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1141                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1142         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1143                           SIDLE_SMART_WKUP),
1144         .sysc_fields    = &omap_hwmod_sysc_type1,
1145 };
1146 
1147 static struct omap_hwmod_class uart_class = {
1148         .name           = "uart",
1149         .sysc           = &uart_sysc,
1150 };
1151 
1152 struct omap_hwmod am33xx_uart1_hwmod = {
1153         .name           = "uart1",
1154         .class          = &uart_class,
1155         .clkdm_name     = "l4_wkup_clkdm",
1156         .flags          = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1157         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
1158         .prcm           = {
1159                 .omap4  = {
1160                         .modulemode     = MODULEMODE_SWCTRL,
1161                 },
1162         },
1163 };
1164 
1165 struct omap_hwmod am33xx_uart2_hwmod = {
1166         .name           = "uart2",
1167         .class          = &uart_class,
1168         .clkdm_name     = "l4ls_clkdm",
1169         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1170         .main_clk       = "dpll_per_m2_div4_ck",
1171         .prcm           = {
1172                 .omap4  = {
1173                         .modulemode     = MODULEMODE_SWCTRL,
1174                 },
1175         },
1176 };
1177 
1178 /* uart3 */
1179 struct omap_hwmod am33xx_uart3_hwmod = {
1180         .name           = "uart3",
1181         .class          = &uart_class,
1182         .clkdm_name     = "l4ls_clkdm",
1183         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1184         .main_clk       = "dpll_per_m2_div4_ck",
1185         .prcm           = {
1186                 .omap4  = {
1187                         .modulemode     = MODULEMODE_SWCTRL,
1188                 },
1189         },
1190 };
1191 
1192 struct omap_hwmod am33xx_uart4_hwmod = {
1193         .name           = "uart4",
1194         .class          = &uart_class,
1195         .clkdm_name     = "l4ls_clkdm",
1196         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1197         .main_clk       = "dpll_per_m2_div4_ck",
1198         .prcm           = {
1199                 .omap4  = {
1200                         .modulemode     = MODULEMODE_SWCTRL,
1201                 },
1202         },
1203 };
1204 
1205 struct omap_hwmod am33xx_uart5_hwmod = {
1206         .name           = "uart5",
1207         .class          = &uart_class,
1208         .clkdm_name     = "l4ls_clkdm",
1209         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1210         .main_clk       = "dpll_per_m2_div4_ck",
1211         .prcm           = {
1212                 .omap4  = {
1213                         .modulemode     = MODULEMODE_SWCTRL,
1214                 },
1215         },
1216 };
1217 
1218 struct omap_hwmod am33xx_uart6_hwmod = {
1219         .name           = "uart6",
1220         .class          = &uart_class,
1221         .clkdm_name     = "l4ls_clkdm",
1222         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1223         .main_clk       = "dpll_per_m2_div4_ck",
1224         .prcm           = {
1225                 .omap4  = {
1226                         .modulemode     = MODULEMODE_SWCTRL,
1227                 },
1228         },
1229 };
1230 
1231 /* 'wd_timer' class */
1232 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1233         .rev_offs       = 0x0,
1234         .sysc_offs      = 0x10,
1235         .syss_offs      = 0x14,
1236         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1237                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1238         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1239                         SIDLE_SMART_WKUP),
1240         .sysc_fields    = &omap_hwmod_sysc_type1,
1241 };
1242 
1243 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1244         .name           = "wd_timer",
1245         .sysc           = &wdt_sysc,
1246         .pre_shutdown   = &omap2_wd_timer_disable,
1247 };
1248 
1249 /*
1250  * XXX: device.c file uses hardcoded name for watchdog timer
1251  * driver "wd_timer2, so we are also using same name as of now...
1252  */
1253 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1254         .name           = "wd_timer2",
1255         .class          = &am33xx_wd_timer_hwmod_class,
1256         .clkdm_name     = "l4_wkup_clkdm",
1257         .flags          = HWMOD_SWSUP_SIDLE,
1258         .main_clk       = "wdt1_fck",
1259         .prcm           = {
1260                 .omap4  = {
1261                         .modulemode     = MODULEMODE_SWCTRL,
1262                 },
1263         },
1264 };
1265 
1266 static void omap_hwmod_am33xx_clkctrl(void)
1267 {
1268         CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1269         CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1270         CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1271         CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1272         CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1273         CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1274         CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1275         CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1276         CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1277         CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1278         CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1279         CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1280         CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1281         CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1282         CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1283         CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1284         CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1285         CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1286         CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1287         CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1288         CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1289         CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1290         CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1291         CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1292         CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1293         CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1294         CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1295         CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1296         CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1297         CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1298         CLKCTRL(am33xx_smartreflex0_hwmod,
1299                 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1300         CLKCTRL(am33xx_smartreflex1_hwmod,
1301                 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1302         CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1303         CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1304         CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1305         CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1306         CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1307         PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
1308         CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1309         CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1310         CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1311         CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1312         CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1313         CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1314         CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1315         CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1316         CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1317         CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1318         CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1319         CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1320         CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1321         CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1322         CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1323         CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1324         CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1325         CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
1326 }
1327 
1328 static void omap_hwmod_am33xx_rst(void)
1329 {
1330         RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1331         RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1332         RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1333 }
1334 
1335 void omap_hwmod_am33xx_reg(void)
1336 {
1337         omap_hwmod_am33xx_clkctrl();
1338         omap_hwmod_am33xx_rst();
1339 }
1340 
1341 static void omap_hwmod_am43xx_clkctrl(void)
1342 {
1343         CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1344         CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1345         CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1346         CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1347         CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1348         CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1349         CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1350         CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1351         CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1352         CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1353         CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1354         CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1355         CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1356         CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1357         CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1358         CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1359         CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1360         CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1361         CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1362         CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1363         CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1364         CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1365         CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1366         CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1367         CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1368         CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1369         CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1370         CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1371         CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1372         CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1373         CLKCTRL(am33xx_smartreflex0_hwmod,
1374                 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1375         CLKCTRL(am33xx_smartreflex1_hwmod,
1376                 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1377         CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1378         CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1379         CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1380         CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1381         CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1382         CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1383         CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1384         CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1385         CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1386         CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1387         CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1388         CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1389         CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1390         CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1391         CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1392         CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1393         CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1394         CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1395         CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1396         CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1397         CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1398         CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1399         CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
1400 }
1401 
1402 static void omap_hwmod_am43xx_rst(void)
1403 {
1404         RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1405         RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1406         RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
1407         RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1408 }
1409 
1410 void omap_hwmod_am43xx_reg(void)
1411 {
1412         omap_hwmod_am43xx_clkctrl();
1413         omap_hwmod_am43xx_rst();
1414 }
1415 

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