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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-pxa/zeus.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  *  Support for the Arcom ZEUS.
  4  *
  5  *  Copyright (C) 2006 Arcom Control Systems Ltd.
  6  *
  7  *  Loosely based on Arcom's 2.6.16.28.
  8  *  Maintained by Marc Zyngier <maz@misterjones.org>
  9  */
 10 
 11 #include <linux/cpufreq.h>
 12 #include <linux/interrupt.h>
 13 #include <linux/leds.h>
 14 #include <linux/irq.h>
 15 #include <linux/pm.h>
 16 #include <linux/property.h>
 17 #include <linux/gpio.h>
 18 #include <linux/gpio/machine.h>
 19 #include <linux/serial_8250.h>
 20 #include <linux/dm9000.h>
 21 #include <linux/mmc/host.h>
 22 #include <linux/spi/spi.h>
 23 #include <linux/spi/pxa2xx_spi.h>
 24 #include <linux/mtd/mtd.h>
 25 #include <linux/mtd/partitions.h>
 26 #include <linux/mtd/physmap.h>
 27 #include <linux/i2c.h>
 28 #include <linux/platform_data/i2c-pxa.h>
 29 #include <linux/platform_data/pca953x.h>
 30 #include <linux/apm-emulation.h>
 31 #include <linux/regulator/fixed.h>
 32 #include <linux/regulator/machine.h>
 33 
 34 #include <asm/mach-types.h>
 35 #include <asm/suspend.h>
 36 #include <asm/system_info.h>
 37 #include <asm/mach/arch.h>
 38 #include <asm/mach/map.h>
 39 
 40 #include "pxa27x.h"
 41 #include "devices.h"
 42 #include <mach/regs-uart.h>
 43 #include <linux/platform_data/usb-ohci-pxa27x.h>
 44 #include <linux/platform_data/mmc-pxamci.h>
 45 #include "pxa27x-udc.h"
 46 #include "udc.h"
 47 #include <linux/platform_data/video-pxafb.h>
 48 #include "pm.h"
 49 #include <mach/audio.h>
 50 #include <linux/platform_data/pcmcia-pxa2xx_viper.h>
 51 #include "zeus.h"
 52 #include <mach/smemc.h>
 53 
 54 #include "generic.h"
 55 
 56 /*
 57  * Interrupt handling
 58  */
 59 
 60 static unsigned long zeus_irq_enabled_mask;
 61 static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
 62 static const int zeus_isa_irq_map[] = {
 63         0,              /* ISA irq #0, invalid */
 64         0,              /* ISA irq #1, invalid */
 65         0,              /* ISA irq #2, invalid */
 66         1 << 0,         /* ISA irq #3 */
 67         1 << 1,         /* ISA irq #4 */
 68         1 << 2,         /* ISA irq #5 */
 69         1 << 3,         /* ISA irq #6 */
 70         1 << 4,         /* ISA irq #7 */
 71         0,              /* ISA irq #8, invalid */
 72         0,              /* ISA irq #9, invalid */
 73         1 << 5,         /* ISA irq #10 */
 74         1 << 6,         /* ISA irq #11 */
 75         1 << 7,         /* ISA irq #12 */
 76 };
 77 
 78 static inline int zeus_irq_to_bitmask(unsigned int irq)
 79 {
 80         return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
 81 }
 82 
 83 static inline int zeus_bit_to_irq(int bit)
 84 {
 85         return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
 86 }
 87 
 88 static void zeus_ack_irq(struct irq_data *d)
 89 {
 90         __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
 91 }
 92 
 93 static void zeus_mask_irq(struct irq_data *d)
 94 {
 95         zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
 96 }
 97 
 98 static void zeus_unmask_irq(struct irq_data *d)
 99 {
100         zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
101 }
102 
103 static inline unsigned long zeus_irq_pending(void)
104 {
105         return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
106 }
107 
108 static void zeus_irq_handler(struct irq_desc *desc)
109 {
110         unsigned int irq;
111         unsigned long pending;
112 
113         pending = zeus_irq_pending();
114         do {
115                 /* we're in a chained irq handler,
116                  * so ack the interrupt by hand */
117                 desc->irq_data.chip->irq_ack(&desc->irq_data);
118 
119                 if (likely(pending)) {
120                         irq = zeus_bit_to_irq(__ffs(pending));
121                         generic_handle_irq(irq);
122                 }
123                 pending = zeus_irq_pending();
124         } while (pending);
125 }
126 
127 static struct irq_chip zeus_irq_chip = {
128         .name           = "ISA",
129         .irq_ack        = zeus_ack_irq,
130         .irq_mask       = zeus_mask_irq,
131         .irq_unmask     = zeus_unmask_irq,
132 };
133 
134 static void __init zeus_init_irq(void)
135 {
136         int level;
137         int isa_irq;
138 
139         pxa27x_init_irq();
140 
141         /* Peripheral IRQs. It would be nice to move those inside driver
142            configuration, but it is not supported at the moment. */
143         irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
144         irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
145         irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
146         irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
147                          IRQ_TYPE_EDGE_FALLING);
148         irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
149 
150         /* Setup ISA IRQs */
151         for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
152                 isa_irq = zeus_bit_to_irq(level);
153                 irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
154                                          handle_edge_irq);
155                 irq_clear_status_flags(isa_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
156         }
157 
158         irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
159         irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
160 }
161 
162 
163 /*
164  * Platform devices
165  */
166 
167 /* Flash */
168 static struct resource zeus_mtd_resources[] = {
169         [0] = { /* NOR Flash (up to 64MB) */
170                 .start  = ZEUS_FLASH_PHYS,
171                 .end    = ZEUS_FLASH_PHYS + SZ_64M - 1,
172                 .flags  = IORESOURCE_MEM,
173         },
174         [1] = { /* SRAM */
175                 .start  = ZEUS_SRAM_PHYS,
176                 .end    = ZEUS_SRAM_PHYS + SZ_512K - 1,
177                 .flags  = IORESOURCE_MEM,
178         },
179 };
180 
181 static struct physmap_flash_data zeus_flash_data[] = {
182         [0] = {
183                 .width          = 2,
184                 .parts          = NULL,
185                 .nr_parts       = 0,
186         },
187 };
188 
189 static struct platform_device zeus_mtd_devices[] = {
190         [0] = {
191                 .name           = "physmap-flash",
192                 .id             = 0,
193                 .dev            = {
194                         .platform_data = &zeus_flash_data[0],
195                 },
196                 .resource       = &zeus_mtd_resources[0],
197                 .num_resources  = 1,
198         },
199 };
200 
201 /* Serial */
202 static struct resource zeus_serial_resources[] = {
203         {
204                 .start  = 0x10000000,
205                 .end    = 0x1000000f,
206                 .flags  = IORESOURCE_MEM,
207         },
208         {
209                 .start  = 0x10800000,
210                 .end    = 0x1080000f,
211                 .flags  = IORESOURCE_MEM,
212         },
213         {
214                 .start  = 0x11000000,
215                 .end    = 0x1100000f,
216                 .flags  = IORESOURCE_MEM,
217         },
218         {
219                 .start  = 0x40100000,
220                 .end    = 0x4010001f,
221                 .flags  = IORESOURCE_MEM,
222         },
223         {
224                 .start  = 0x40200000,
225                 .end    = 0x4020001f,
226                 .flags  = IORESOURCE_MEM,
227         },
228         {
229                 .start  = 0x40700000,
230                 .end    = 0x4070001f,
231                 .flags  = IORESOURCE_MEM,
232         },
233 };
234 
235 static struct plat_serial8250_port serial_platform_data[] = {
236         /* External UARTs */
237         /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
238         { /* COM1 */
239                 .mapbase        = 0x10000000,
240                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO),
241                 .irqflags       = IRQF_TRIGGER_RISING,
242                 .uartclk        = 14745600,
243                 .regshift       = 1,
244                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
245                 .iotype         = UPIO_MEM,
246         },
247         { /* COM2 */
248                 .mapbase        = 0x10800000,
249                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO),
250                 .irqflags       = IRQF_TRIGGER_RISING,
251                 .uartclk        = 14745600,
252                 .regshift       = 1,
253                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
254                 .iotype         = UPIO_MEM,
255         },
256         { /* COM3 */
257                 .mapbase        = 0x11000000,
258                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO),
259                 .irqflags       = IRQF_TRIGGER_RISING,
260                 .uartclk        = 14745600,
261                 .regshift       = 1,
262                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
263                 .iotype         = UPIO_MEM,
264         },
265         { /* COM4 */
266                 .mapbase        = 0x11800000,
267                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO),
268                 .irqflags       = IRQF_TRIGGER_RISING,
269                 .uartclk        = 14745600,
270                 .regshift       = 1,
271                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
272                 .iotype         = UPIO_MEM,
273         },
274         /* Internal UARTs */
275         { /* FFUART */
276                 .membase        = (void *)&FFUART,
277                 .mapbase        = __PREG(FFUART),
278                 .irq            = IRQ_FFUART,
279                 .uartclk        = 921600 * 16,
280                 .regshift       = 2,
281                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
282                 .iotype         = UPIO_MEM,
283         },
284         { /* BTUART */
285                 .membase        = (void *)&BTUART,
286                 .mapbase        = __PREG(BTUART),
287                 .irq            = IRQ_BTUART,
288                 .uartclk        = 921600 * 16,
289                 .regshift       = 2,
290                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
291                 .iotype         = UPIO_MEM,
292         },
293         { /* STUART */
294                 .membase        = (void *)&STUART,
295                 .mapbase        = __PREG(STUART),
296                 .irq            = IRQ_STUART,
297                 .uartclk        = 921600 * 16,
298                 .regshift       = 2,
299                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
300                 .iotype         = UPIO_MEM,
301         },
302         { },
303 };
304 
305 static struct platform_device zeus_serial_device = {
306         .name = "serial8250",
307         .id   = PLAT8250_DEV_PLATFORM,
308         .dev  = {
309                 .platform_data = serial_platform_data,
310         },
311         .num_resources  = ARRAY_SIZE(zeus_serial_resources),
312         .resource       = zeus_serial_resources,
313 };
314 
315 /* Ethernet */
316 static struct resource zeus_dm9k0_resource[] = {
317         [0] = {
318                 .start = ZEUS_ETH0_PHYS,
319                 .end   = ZEUS_ETH0_PHYS + 1,
320                 .flags = IORESOURCE_MEM
321         },
322         [1] = {
323                 .start = ZEUS_ETH0_PHYS + 2,
324                 .end   = ZEUS_ETH0_PHYS + 3,
325                 .flags = IORESOURCE_MEM
326         },
327         [2] = {
328                 .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
329                 .end   = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
330                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
331         },
332 };
333 
334 static struct resource zeus_dm9k1_resource[] = {
335         [0] = {
336                 .start = ZEUS_ETH1_PHYS,
337                 .end   = ZEUS_ETH1_PHYS + 1,
338                 .flags = IORESOURCE_MEM
339         },
340         [1] = {
341                 .start = ZEUS_ETH1_PHYS + 2,
342                 .end   = ZEUS_ETH1_PHYS + 3,
343                 .flags = IORESOURCE_MEM,
344         },
345         [2] = {
346                 .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
347                 .end   = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
348                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
349         },
350 };
351 
352 static struct dm9000_plat_data zeus_dm9k_platdata = {
353         .flags          = DM9000_PLATF_16BITONLY,
354 };
355 
356 static struct platform_device zeus_dm9k0_device = {
357         .name           = "dm9000",
358         .id             = 0,
359         .num_resources  = ARRAY_SIZE(zeus_dm9k0_resource),
360         .resource       = zeus_dm9k0_resource,
361         .dev            = {
362                 .platform_data = &zeus_dm9k_platdata,
363         }
364 };
365 
366 static struct platform_device zeus_dm9k1_device = {
367         .name           = "dm9000",
368         .id             = 1,
369         .num_resources  = ARRAY_SIZE(zeus_dm9k1_resource),
370         .resource       = zeus_dm9k1_resource,
371         .dev            = {
372                 .platform_data = &zeus_dm9k_platdata,
373         }
374 };
375 
376 /* External SRAM */
377 static struct resource zeus_sram_resource = {
378         .start          = ZEUS_SRAM_PHYS,
379         .end            = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
380         .flags          = IORESOURCE_MEM,
381 };
382 
383 static struct platform_device zeus_sram_device = {
384         .name           = "pxa2xx-8bit-sram",
385         .id             = 0,
386         .num_resources  = 1,
387         .resource       = &zeus_sram_resource,
388 };
389 
390 /* SPI interface on SSP3 */
391 static struct pxa2xx_spi_controller pxa2xx_spi_ssp3_master_info = {
392         .num_chipselect = 1,
393         .enable_dma     = 1,
394 };
395 
396 /* CAN bus on SPI */
397 static struct regulator_consumer_supply can_regulator_consumer =
398         REGULATOR_SUPPLY("vdd", "spi3.0");
399 
400 static struct regulator_init_data can_regulator_init_data = {
401         .constraints    = {
402                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
403         },
404         .consumer_supplies      = &can_regulator_consumer,
405         .num_consumer_supplies  = 1,
406 };
407 
408 static struct fixed_voltage_config can_regulator_pdata = {
409         .supply_name    = "CAN_SHDN",
410         .microvolts     = 3300000,
411         .init_data      = &can_regulator_init_data,
412 };
413 
414 static struct platform_device can_regulator_device = {
415         .name   = "reg-fixed-voltage",
416         .id     = 0,
417         .dev    = {
418                 .platform_data  = &can_regulator_pdata,
419         },
420 };
421 
422 static struct gpiod_lookup_table can_regulator_gpiod_table = {
423         .dev_id = "reg-fixed-voltage.0",
424         .table = {
425                 GPIO_LOOKUP("gpio-pxa", ZEUS_CAN_SHDN_GPIO,
426                             NULL, GPIO_ACTIVE_LOW),
427                 { },
428         },
429 };
430 
431 static const struct property_entry mcp251x_properties[] = {
432         PROPERTY_ENTRY_U32("clock-frequency", 16000000),
433         {}
434 };
435 
436 static struct spi_board_info zeus_spi_board_info[] = {
437         [0] = {
438                 .modalias       = "mcp2515",
439                 .properties     = mcp251x_properties,
440                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO),
441                 .max_speed_hz   = 1*1000*1000,
442                 .bus_num        = 3,
443                 .mode           = SPI_MODE_0,
444                 .chip_select    = 0,
445         },
446 };
447 
448 /* Leds */
449 static struct gpio_led zeus_leds[] = {
450         [0] = {
451                 .name            = "zeus:yellow:1",
452                 .default_trigger = "heartbeat",
453                 .gpio            = ZEUS_EXT0_GPIO(3),
454                 .active_low      = 1,
455         },
456         [1] = {
457                 .name            = "zeus:yellow:2",
458                 .default_trigger = "default-on",
459                 .gpio            = ZEUS_EXT0_GPIO(4),
460                 .active_low      = 1,
461         },
462         [2] = {
463                 .name            = "zeus:yellow:3",
464                 .default_trigger = "default-on",
465                 .gpio            = ZEUS_EXT0_GPIO(5),
466                 .active_low      = 1,
467         },
468 };
469 
470 static struct gpio_led_platform_data zeus_leds_info = {
471         .leds           = zeus_leds,
472         .num_leds       = ARRAY_SIZE(zeus_leds),
473 };
474 
475 static struct platform_device zeus_leds_device = {
476         .name           = "leds-gpio",
477         .id             = -1,
478         .dev            = {
479                 .platform_data  = &zeus_leds_info,
480         },
481 };
482 
483 static void zeus_cf_reset(int state)
484 {
485         u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
486 
487         if (state)
488                 cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
489         else
490                 cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
491 
492         __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
493 }
494 
495 static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
496         .cd_gpio        = ZEUS_CF_CD_GPIO,
497         .rdy_gpio       = ZEUS_CF_RDY_GPIO,
498         .pwr_gpio       = ZEUS_CF_PWEN_GPIO,
499         .reset          = zeus_cf_reset,
500 };
501 
502 static struct platform_device zeus_pcmcia_device = {
503         .name           = "zeus-pcmcia",
504         .id             = -1,
505         .dev            = {
506                 .platform_data  = &zeus_pcmcia_info,
507         },
508 };
509 
510 static struct resource zeus_max6369_resource = {
511         .start          = ZEUS_CPLD_EXTWDOG_PHYS,
512         .end            = ZEUS_CPLD_EXTWDOG_PHYS,
513         .flags          = IORESOURCE_MEM,
514 };
515 
516 struct platform_device zeus_max6369_device = {
517         .name           = "max6369_wdt",
518         .id             = -1,
519         .resource       = &zeus_max6369_resource,
520         .num_resources  = 1,
521 };
522 
523 /* AC'97 */
524 static pxa2xx_audio_ops_t zeus_ac97_info = {
525         .reset_gpio = 95,
526 };
527 
528 
529 /*
530  * USB host
531  */
532 
533 static struct regulator_consumer_supply zeus_ohci_regulator_supplies[] = {
534         REGULATOR_SUPPLY("vbus2", "pxa27x-ohci"),
535 };
536 
537 static struct regulator_init_data zeus_ohci_regulator_data = {
538         .constraints = {
539                 .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
540         },
541         .num_consumer_supplies  = ARRAY_SIZE(zeus_ohci_regulator_supplies),
542         .consumer_supplies      = zeus_ohci_regulator_supplies,
543 };
544 
545 static struct fixed_voltage_config zeus_ohci_regulator_config = {
546         .supply_name            = "vbus2",
547         .microvolts             = 5000000, /* 5.0V */
548         .startup_delay          = 0,
549         .init_data              = &zeus_ohci_regulator_data,
550 };
551 
552 static struct platform_device zeus_ohci_regulator_device = {
553         .name           = "reg-fixed-voltage",
554         .id             = 1,
555         .dev = {
556                 .platform_data = &zeus_ohci_regulator_config,
557         },
558 };
559 
560 static struct gpiod_lookup_table zeus_ohci_regulator_gpiod_table = {
561         .dev_id = "reg-fixed-voltage.0",
562         .table = {
563                 GPIO_LOOKUP("gpio-pxa", ZEUS_USB2_PWREN_GPIO,
564                             NULL, GPIO_ACTIVE_HIGH),
565                 { },
566         },
567 };
568 
569 static struct pxaohci_platform_data zeus_ohci_platform_data = {
570         .port_mode      = PMM_NPS_MODE,
571         /* Clear Power Control Polarity Low and set Power Sense
572          * Polarity Low. Supply power to USB ports. */
573         .flags          = ENABLE_PORT_ALL | POWER_SENSE_LOW,
574 };
575 
576 static void __init zeus_register_ohci(void)
577 {
578         /* Port 2 is shared between host and client interface. */
579         UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
580 
581         pxa_set_ohci_info(&zeus_ohci_platform_data);
582 }
583 
584 /*
585  * Flat Panel
586  */
587 
588 static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
589 {
590         gpio_set_value(ZEUS_LCD_EN_GPIO, on);
591 }
592 
593 static void zeus_backlight_power(int on)
594 {
595         gpio_set_value(ZEUS_BKLEN_GPIO, on);
596 }
597 
598 static int zeus_setup_fb_gpios(void)
599 {
600         int err;
601 
602         if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
603                 goto out_err;
604 
605         if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
606                 goto out_err_lcd;
607 
608         if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
609                 goto out_err_lcd;
610 
611         if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
612                 goto out_err_bkl;
613 
614         return 0;
615 
616 out_err_bkl:
617         gpio_free(ZEUS_BKLEN_GPIO);
618 out_err_lcd:
619         gpio_free(ZEUS_LCD_EN_GPIO);
620 out_err:
621         return err;
622 }
623 
624 static struct pxafb_mode_info zeus_fb_mode_info[] = {
625         {
626                 .pixclock       = 39722,
627 
628                 .xres           = 640,
629                 .yres           = 480,
630 
631                 .bpp            = 16,
632 
633                 .hsync_len      = 63,
634                 .left_margin    = 16,
635                 .right_margin   = 81,
636 
637                 .vsync_len      = 2,
638                 .upper_margin   = 12,
639                 .lower_margin   = 31,
640 
641                 .sync           = 0,
642         },
643 };
644 
645 static struct pxafb_mach_info zeus_fb_info = {
646         .modes                  = zeus_fb_mode_info,
647         .num_modes              = 1,
648         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
649         .pxafb_lcd_power        = zeus_lcd_power,
650         .pxafb_backlight_power  = zeus_backlight_power,
651 };
652 
653 /*
654  * MMC/SD Device
655  *
656  * The card detect interrupt isn't debounced so we delay it by 250ms
657  * to give the card a chance to fully insert/eject.
658  */
659 
660 static struct pxamci_platform_data zeus_mci_platform_data = {
661         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
662         .detect_delay_ms        = 250,
663         .gpio_card_ro_invert    = 1,
664 };
665 
666 static struct gpiod_lookup_table zeus_mci_gpio_table = {
667         .dev_id = "pxa2xx-mci.0",
668         .table = {
669                 GPIO_LOOKUP("gpio-pxa", ZEUS_MMC_CD_GPIO,
670                             "cd", GPIO_ACTIVE_LOW),
671                 GPIO_LOOKUP("gpio-pxa", ZEUS_MMC_WP_GPIO,
672                             "wp", GPIO_ACTIVE_HIGH),
673                 { },
674         },
675 };
676 
677 /*
678  * USB Device Controller
679  */
680 static void zeus_udc_command(int cmd)
681 {
682         switch (cmd) {
683         case PXA2XX_UDC_CMD_DISCONNECT:
684                 pr_info("zeus: disconnecting USB client\n");
685                 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
686                 break;
687 
688         case PXA2XX_UDC_CMD_CONNECT:
689                 pr_info("zeus: connecting USB client\n");
690                 UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
691                 break;
692         }
693 }
694 
695 static struct pxa2xx_udc_mach_info zeus_udc_info = {
696         .udc_command = zeus_udc_command,
697 };
698 
699 static struct platform_device *zeus_devices[] __initdata = {
700         &zeus_serial_device,
701         &zeus_mtd_devices[0],
702         &zeus_dm9k0_device,
703         &zeus_dm9k1_device,
704         &zeus_sram_device,
705         &zeus_leds_device,
706         &zeus_pcmcia_device,
707         &zeus_max6369_device,
708         &can_regulator_device,
709         &zeus_ohci_regulator_device,
710 };
711 
712 #ifdef CONFIG_PM
713 static void zeus_power_off(void)
714 {
715         local_irq_disable();
716         cpu_suspend(PWRMODE_DEEPSLEEP, pxa27x_finish_suspend);
717 }
718 #else
719 #define zeus_power_off   NULL
720 #endif
721 
722 #ifdef CONFIG_APM_EMULATION
723 static void zeus_get_power_status(struct apm_power_info *info)
724 {
725         /* Power supply is always present */
726         info->ac_line_status    = APM_AC_ONLINE;
727         info->battery_status    = APM_BATTERY_STATUS_NOT_PRESENT;
728         info->battery_flag      = APM_BATTERY_FLAG_NOT_PRESENT;
729 }
730 
731 static inline void zeus_setup_apm(void)
732 {
733         apm_get_power_status = zeus_get_power_status;
734 }
735 #else
736 static inline void zeus_setup_apm(void)
737 {
738 }
739 #endif
740 
741 static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
742                              unsigned ngpio, void *context)
743 {
744         int i;
745         u8 pcb_info = 0;
746 
747         for (i = 0; i < 8; i++) {
748                 int pcb_bit = gpio + i + 8;
749 
750                 if (gpio_request(pcb_bit, "pcb info")) {
751                         dev_err(&client->dev, "Can't request pcb info %d\n", i);
752                         continue;
753                 }
754 
755                 if (gpio_direction_input(pcb_bit)) {
756                         dev_err(&client->dev, "Can't read pcb info %d\n", i);
757                         gpio_free(pcb_bit);
758                         continue;
759                 }
760 
761                 pcb_info |= !!gpio_get_value(pcb_bit) << i;
762 
763                 gpio_free(pcb_bit);
764         }
765 
766         dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
767                  pcb_info >> 4, pcb_info & 0xf);
768 
769         return 0;
770 }
771 
772 static struct pca953x_platform_data zeus_pca953x_pdata[] = {
773         [0] = { .gpio_base      = ZEUS_EXT0_GPIO_BASE, },
774         [1] = {
775                 .gpio_base      = ZEUS_EXT1_GPIO_BASE,
776                 .setup          = zeus_get_pcb_info,
777         },
778         [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
779 };
780 
781 static struct i2c_board_info __initdata zeus_i2c_devices[] = {
782         {
783                 I2C_BOARD_INFO("pca9535",       0x21),
784                 .platform_data  = &zeus_pca953x_pdata[0],
785         },
786         {
787                 I2C_BOARD_INFO("pca9535",       0x22),
788                 .platform_data  = &zeus_pca953x_pdata[1],
789         },
790         {
791                 I2C_BOARD_INFO("pca9535",       0x20),
792                 .platform_data  = &zeus_pca953x_pdata[2],
793                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_EXTGPIO_GPIO),
794         },
795         { I2C_BOARD_INFO("lm75a",       0x48) },
796         { I2C_BOARD_INFO("24c01",       0x50) },
797         { I2C_BOARD_INFO("isl1208",     0x6f) },
798 };
799 
800 static mfp_cfg_t zeus_pin_config[] __initdata = {
801         /* AC97 */
802         GPIO28_AC97_BITCLK,
803         GPIO29_AC97_SDATA_IN_0,
804         GPIO30_AC97_SDATA_OUT,
805         GPIO31_AC97_SYNC,
806 
807         GPIO15_nCS_1,
808         GPIO78_nCS_2,
809         GPIO80_nCS_4,
810         GPIO33_nCS_5,
811 
812         GPIO22_GPIO,
813         GPIO32_MMC_CLK,
814         GPIO92_MMC_DAT_0,
815         GPIO109_MMC_DAT_1,
816         GPIO110_MMC_DAT_2,
817         GPIO111_MMC_DAT_3,
818         GPIO112_MMC_CMD,
819 
820         GPIO88_USBH1_PWR,
821         GPIO89_USBH1_PEN,
822         GPIO119_USBH2_PWR,
823         GPIO120_USBH2_PEN,
824 
825         GPIO86_LCD_LDD_16,
826         GPIO87_LCD_LDD_17,
827 
828         GPIO102_GPIO,
829         GPIO104_CIF_DD_2,
830         GPIO105_CIF_DD_1,
831 
832         GPIO81_SSP3_TXD,
833         GPIO82_SSP3_RXD,
834         GPIO83_SSP3_SFRM,
835         GPIO84_SSP3_SCLK,
836 
837         GPIO48_nPOE,
838         GPIO49_nPWE,
839         GPIO50_nPIOR,
840         GPIO51_nPIOW,
841         GPIO85_nPCE_1,
842         GPIO54_nPCE_2,
843         GPIO79_PSKTSEL,
844         GPIO55_nPREG,
845         GPIO56_nPWAIT,
846         GPIO57_nIOIS16,
847         GPIO36_GPIO,            /* CF CD */
848         GPIO97_GPIO,            /* CF PWREN */
849         GPIO99_GPIO,            /* CF RDY */
850 };
851 
852 /*
853  * DM9k MSCx settings:  SRAM, 16 bits
854  *                      17 cycles delay first access
855  *                       5 cycles delay next access
856  *                      13 cycles recovery time
857  *                      faster device
858  */
859 #define DM9K_MSC_VALUE          0xe4c9
860 
861 static void __init zeus_init(void)
862 {
863         u16 dm9000_msc = DM9K_MSC_VALUE;
864         u32 msc0, msc1;
865 
866         system_rev = __raw_readw(ZEUS_CPLD_VERSION);
867         pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
868 
869         /* Fix timings for dm9000s (CS1/CS2)*/
870         msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
871         msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
872         __raw_writel(msc0, MSC0);
873         __raw_writel(msc1, MSC1);
874 
875         pm_power_off = zeus_power_off;
876         zeus_setup_apm();
877 
878         pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
879 
880         gpiod_add_lookup_table(&can_regulator_gpiod_table);
881         gpiod_add_lookup_table(&zeus_ohci_regulator_gpiod_table);
882         platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
883 
884         zeus_register_ohci();
885 
886         if (zeus_setup_fb_gpios())
887                 pr_err("Failed to setup fb gpios\n");
888         else
889                 pxa_set_fb_info(NULL, &zeus_fb_info);
890 
891         gpiod_add_lookup_table(&zeus_mci_gpio_table);
892         pxa_set_mci_info(&zeus_mci_platform_data);
893         pxa_set_udc_info(&zeus_udc_info);
894         pxa_set_ac97_info(&zeus_ac97_info);
895         pxa_set_i2c_info(NULL);
896         i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
897         pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info);
898         spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info));
899 
900         regulator_has_full_constraints();
901 }
902 
903 static struct map_desc zeus_io_desc[] __initdata = {
904         {
905                 .virtual = (unsigned long)ZEUS_CPLD_VERSION,
906                 .pfn     = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
907                 .length  = 0x1000,
908                 .type    = MT_DEVICE,
909         },
910         {
911                 .virtual = (unsigned long)ZEUS_CPLD_ISA_IRQ,
912                 .pfn     = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
913                 .length  = 0x1000,
914                 .type    = MT_DEVICE,
915         },
916         {
917                 .virtual = (unsigned long)ZEUS_CPLD_CONTROL,
918                 .pfn     = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
919                 .length  = 0x1000,
920                 .type    = MT_DEVICE,
921         },
922         {
923                 .virtual = (unsigned long)ZEUS_PC104IO,
924                 .pfn     = __phys_to_pfn(ZEUS_PC104IO_PHYS),
925                 .length  = 0x00800000,
926                 .type    = MT_DEVICE,
927         },
928 };
929 
930 static void __init zeus_map_io(void)
931 {
932         pxa27x_map_io();
933 
934         iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
935 
936         /* Clear PSPR to ensure a full restart on wake-up. */
937         PMCR = PSPR = 0;
938 
939         /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
940         writel(readl(OSCC) | OSCC_OON, OSCC);
941 
942         /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
943          * float chip selects and PCMCIA */
944         PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
945 }
946 
947 MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
948         /* Maintainer: Marc Zyngier <maz@misterjones.org> */
949         .atag_offset    = 0x100,
950         .map_io         = zeus_map_io,
951         .nr_irqs        = ZEUS_NR_IRQS,
952         .init_irq       = zeus_init_irq,
953         .handle_irq     = pxa27x_handle_irq,
954         .init_time      = pxa_timer_init,
955         .init_machine   = zeus_init,
956         .restart        = pxa_restart,
957 MACHINE_END
958 
959 

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