1 /* 2 * Copyright (c) 2003-2004 Simtec Electronics 3 * Ben Dooks <ben@simtec.co.uk> 4 * 5 * BAST - CPLD control constants 6 * BAST - IRQ Number definitions 7 * BAST - Memory map definitions 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #ifndef __MACH_S3C24XX_BAST_H 15 #define __MACH_S3C24XX_BAST_H __FILE__ 16 17 /* CTRL1 - Audio LR routing */ 18 19 #define BAST_CPLD_CTRL1_LRCOFF (0x00) 20 #define BAST_CPLD_CTRL1_LRCADC (0x01) 21 #define BAST_CPLD_CTRL1_LRCDAC (0x02) 22 #define BAST_CPLD_CTRL1_LRCARM (0x03) 23 #define BAST_CPLD_CTRL1_LRMASK (0x03) 24 25 /* CTRL2 - NAND WP control, IDE Reset assert/check */ 26 27 #define BAST_CPLD_CTRL2_WNAND (0x04) 28 #define BAST_CPLD_CTLR2_IDERST (0x08) 29 30 /* CTRL3 - rom write control, CPLD identity */ 31 32 #define BAST_CPLD_CTRL3_IDMASK (0x0e) 33 #define BAST_CPLD_CTRL3_ROMWEN (0x01) 34 35 /* CTRL4 - 8bit LCD interface control/status */ 36 37 #define BAST_CPLD_CTRL4_LLAT (0x01) 38 #define BAST_CPLD_CTRL4_LCDRW (0x02) 39 #define BAST_CPLD_CTRL4_LCDCMD (0x04) 40 #define BAST_CPLD_CTRL4_LCDE2 (0x01) 41 42 /* CTRL5 - DMA routing */ 43 44 #define BAST_CPLD_DMA0_PRIIDE (0) 45 #define BAST_CPLD_DMA0_SECIDE (1) 46 #define BAST_CPLD_DMA0_ISA15 (2) 47 #define BAST_CPLD_DMA0_ISA36 (3) 48 49 #define BAST_CPLD_DMA1_PRIIDE (0 << 2) 50 #define BAST_CPLD_DMA1_SECIDE (1 << 2) 51 #define BAST_CPLD_DMA1_ISA15 (2 << 2) 52 #define BAST_CPLD_DMA1_ISA36 (3 << 2) 53 54 /* irq numbers to onboard peripherals */ 55 56 #define BAST_IRQ_USBOC IRQ_EINT18 57 #define BAST_IRQ_IDE0 IRQ_EINT16 58 #define BAST_IRQ_IDE1 IRQ_EINT17 59 #define BAST_IRQ_PCSERIAL1 IRQ_EINT15 60 #define BAST_IRQ_PCSERIAL2 IRQ_EINT14 61 #define BAST_IRQ_PCPARALLEL IRQ_EINT13 62 #define BAST_IRQ_ASIX IRQ_EINT11 63 #define BAST_IRQ_DM9000 IRQ_EINT10 64 #define BAST_IRQ_ISA IRQ_EINT9 65 #define BAST_IRQ_SMALERT IRQ_EINT8 66 67 /* map */ 68 69 /* 70 * ok, we've used up to 0x13000000, now we need to find space for the 71 * peripherals that live in the nGCS[x] areas, which are quite numerous 72 * in their space. We also have the board's CPLD to find register space 73 * for. 74 */ 75 76 #define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000)) 77 78 /* we put the CPLD registers next, to get them out of the way */ 79 80 #define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) 81 #define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000) 82 83 #define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) 84 #define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000) 85 86 #define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) 87 #define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000) 88 89 #define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) 90 #define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000) 91 92 /* next, we have the PC104 ISA interrupt registers */ 93 94 #define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) 95 #define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000) 96 97 #define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) 98 #define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000) 99 100 #define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) 101 #define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000) 102 103 #define BAST_PA_LCD_RCMD1 (0x8800000) 104 #define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000) 105 106 #define BAST_PA_LCD_WCMD1 (0x8000000) 107 #define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000) 108 109 #define BAST_PA_LCD_RDATA1 (0x9800000) 110 #define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000) 111 112 #define BAST_PA_LCD_WDATA1 (0x9000000) 113 #define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000) 114 115 #define BAST_PA_LCD_RCMD2 (0xA800000) 116 #define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000) 117 118 #define BAST_PA_LCD_WCMD2 (0xA000000) 119 #define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000) 120 121 #define BAST_PA_LCD_RDATA2 (0xB800000) 122 #define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000) 123 124 #define BAST_PA_LCD_WDATA2 (0xB000000) 125 #define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000) 126 127 128 /* 129 * 0xE0000000 contains the IO space that is split by speed and 130 * whether the access is for 8 or 16bit IO... this ensures that 131 * the correct access is made 132 * 133 * 0x10000000 of space, partitioned as so: 134 * 135 * 0x00000000 to 0x04000000 8bit, slow 136 * 0x04000000 to 0x08000000 16bit, slow 137 * 0x08000000 to 0x0C000000 16bit, net 138 * 0x0C000000 to 0x10000000 16bit, fast 139 * 140 * each of these spaces has the following in: 141 * 142 * 0x00000000 to 0x01000000 16MB ISA IO space 143 * 0x01000000 to 0x02000000 16MB ISA memory space 144 * 0x02000000 to 0x02100000 1MB IDE primary channel 145 * 0x02100000 to 0x02200000 1MB IDE primary channel aux 146 * 0x02200000 to 0x02400000 1MB IDE secondary channel 147 * 0x02300000 to 0x02400000 1MB IDE secondary channel aux 148 * 0x02400000 to 0x02500000 1MB ASIX ethernet controller 149 * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller 150 * 0x02600000 to 0x02700000 1MB PC SuperIO controller 151 * 152 * the phyiscal layout of the zones are: 153 * nGCS2 - 8bit, slow 154 * nGCS3 - 16bit, slow 155 * nGCS4 - 16bit, net 156 * nGCS5 - 16bit, fast 157 */ 158 159 #define BAST_VA_MULTISPACE (0xE0000000) 160 161 #define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000) 162 #define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000) 163 #define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000) 164 #define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000) 165 #define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000) 166 #define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000) 167 #define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000) 168 #define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000) 169 #define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000) 170 171 #define BAST_VAM_CS2 (0x00000000) 172 #define BAST_VAM_CS3 (0x04000000) 173 #define BAST_VAM_CS4 (0x08000000) 174 #define BAST_VAM_CS5 (0x0C000000) 175 176 /* physical offset addresses for the peripherals */ 177 178 #define BAST_PA_ISAIO (0x00000000) 179 #define BAST_PA_ASIXNET (0x01000000) 180 #define BAST_PA_SUPERIO (0x01800000) 181 #define BAST_PA_IDEPRI (0x02000000) 182 #define BAST_PA_IDEPRIAUX (0x02800000) 183 #define BAST_PA_IDESEC (0x03000000) 184 #define BAST_PA_IDESECAUX (0x03800000) 185 #define BAST_PA_ISAMEM (0x04000000) 186 #define BAST_PA_DM9000 (0x05000000) 187 188 /* some configurations for the peripherals */ 189 190 #define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2) 191 192 #define BAST_ASIXNET_CS BAST_VAM_CS5 193 #define BAST_DM9000_CS BAST_VAM_CS4 194 195 #define BAST_IDE_CS S3C2410_CS5 196 197 #endif /* __MACH_S3C24XX_BAST_H */ 198
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