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Linux/arch/arm/mach-s3c24xx/common.c

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  1 /* linux/arch/arm/plat-s3c24xx/cpu.c
  2  *
  3  * Copyright (c) 2004-2005 Simtec Electronics
  4  *      http://www.simtec.co.uk/products/SWLINUX/
  5  *      Ben Dooks <ben@simtec.co.uk>
  6  *
  7  * Common code for S3C24XX machines
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License as published by
 11  * the Free Software Foundation; either version 2 of the License, or
 12  * (at your option) any later version.
 13  *
 14  * This program is distributed in the hope that it will be useful,
 15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17  * GNU General Public License for more details.
 18  *
 19  * You should have received a copy of the GNU General Public License
 20  * along with this program; if not, write to the Free Software
 21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 22 */
 23 
 24 
 25 #include <linux/init.h>
 26 #include <linux/module.h>
 27 #include <linux/interrupt.h>
 28 #include <linux/ioport.h>
 29 #include <linux/serial_core.h>
 30 #include <linux/serial_s3c.h>
 31 #include <clocksource/samsung_pwm.h>
 32 #include <linux/platform_device.h>
 33 #include <linux/delay.h>
 34 #include <linux/io.h>
 35 #include <linux/platform_data/dma-s3c24xx.h>
 36 
 37 #include <mach/hardware.h>
 38 #include <mach/regs-clock.h>
 39 #include <asm/irq.h>
 40 #include <asm/cacheflush.h>
 41 #include <asm/system_info.h>
 42 #include <asm/system_misc.h>
 43 
 44 #include <asm/mach/arch.h>
 45 #include <asm/mach/map.h>
 46 
 47 #include <mach/regs-gpio.h>
 48 #include <mach/dma.h>
 49 
 50 #include <plat/cpu.h>
 51 #include <plat/devs.h>
 52 #include <plat/cpu-freq.h>
 53 #include <plat/pwm-core.h>
 54 
 55 #include "common.h"
 56 
 57 /* table of supported CPUs */
 58 
 59 static const char name_s3c2410[]  = "S3C2410";
 60 static const char name_s3c2412[]  = "S3C2412";
 61 static const char name_s3c2416[]  = "S3C2416/S3C2450";
 62 static const char name_s3c2440[]  = "S3C2440";
 63 static const char name_s3c2442[]  = "S3C2442";
 64 static const char name_s3c2442b[]  = "S3C2442B";
 65 static const char name_s3c2443[]  = "S3C2443";
 66 static const char name_s3c2410a[] = "S3C2410A";
 67 static const char name_s3c2440a[] = "S3C2440A";
 68 
 69 static struct cpu_table cpu_ids[] __initdata = {
 70         {
 71                 .idcode         = 0x32410000,
 72                 .idmask         = 0xffffffff,
 73                 .map_io         = s3c2410_map_io,
 74                 .init_uarts     = s3c2410_init_uarts,
 75                 .init           = s3c2410_init,
 76                 .name           = name_s3c2410
 77         },
 78         {
 79                 .idcode         = 0x32410002,
 80                 .idmask         = 0xffffffff,
 81                 .map_io         = s3c2410_map_io,
 82                 .init_uarts     = s3c2410_init_uarts,
 83                 .init           = s3c2410a_init,
 84                 .name           = name_s3c2410a
 85         },
 86         {
 87                 .idcode         = 0x32440000,
 88                 .idmask         = 0xffffffff,
 89                 .map_io         = s3c2440_map_io,
 90                 .init_uarts     = s3c244x_init_uarts,
 91                 .init           = s3c2440_init,
 92                 .name           = name_s3c2440
 93         },
 94         {
 95                 .idcode         = 0x32440001,
 96                 .idmask         = 0xffffffff,
 97                 .map_io         = s3c2440_map_io,
 98                 .init_uarts     = s3c244x_init_uarts,
 99                 .init           = s3c2440_init,
100                 .name           = name_s3c2440a
101         },
102         {
103                 .idcode         = 0x32440aaa,
104                 .idmask         = 0xffffffff,
105                 .map_io         = s3c2442_map_io,
106                 .init_uarts     = s3c244x_init_uarts,
107                 .init           = s3c2442_init,
108                 .name           = name_s3c2442
109         },
110         {
111                 .idcode         = 0x32440aab,
112                 .idmask         = 0xffffffff,
113                 .map_io         = s3c2442_map_io,
114                 .init_uarts     = s3c244x_init_uarts,
115                 .init           = s3c2442_init,
116                 .name           = name_s3c2442b
117         },
118         {
119                 .idcode         = 0x32412001,
120                 .idmask         = 0xffffffff,
121                 .map_io         = s3c2412_map_io,
122                 .init_uarts     = s3c2412_init_uarts,
123                 .init           = s3c2412_init,
124                 .name           = name_s3c2412,
125         },
126         {                       /* a newer version of the s3c2412 */
127                 .idcode         = 0x32412003,
128                 .idmask         = 0xffffffff,
129                 .map_io         = s3c2412_map_io,
130                 .init_uarts     = s3c2412_init_uarts,
131                 .init           = s3c2412_init,
132                 .name           = name_s3c2412,
133         },
134         {                       /* a strange version of the s3c2416 */
135                 .idcode         = 0x32450003,
136                 .idmask         = 0xffffffff,
137                 .map_io         = s3c2416_map_io,
138                 .init_uarts     = s3c2416_init_uarts,
139                 .init           = s3c2416_init,
140                 .name           = name_s3c2416,
141         },
142         {
143                 .idcode         = 0x32443001,
144                 .idmask         = 0xffffffff,
145                 .map_io         = s3c2443_map_io,
146                 .init_uarts     = s3c2443_init_uarts,
147                 .init           = s3c2443_init,
148                 .name           = name_s3c2443,
149         },
150 };
151 
152 /* minimal IO mapping */
153 
154 static struct map_desc s3c_iodesc[] __initdata = {
155         IODESC_ENT(GPIO),
156         IODESC_ENT(IRQ),
157         IODESC_ENT(MEMCTRL),
158         IODESC_ENT(UART)
159 };
160 
161 /* read cpu identificaiton code */
162 
163 static unsigned long s3c24xx_read_idcode_v5(void)
164 {
165 #if defined(CONFIG_CPU_S3C2416)
166         /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
167 
168         u32 gs = __raw_readl(S3C24XX_GSTATUS1);
169 
170         /* test for s3c2416 or similar device */
171         if ((gs >> 16) == 0x3245)
172                 return gs;
173 #endif
174 
175 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
176         return __raw_readl(S3C2412_GSTATUS1);
177 #else
178         return 1UL;     /* don't look like an 2400 */
179 #endif
180 }
181 
182 static unsigned long s3c24xx_read_idcode_v4(void)
183 {
184         return __raw_readl(S3C2410_GSTATUS1);
185 }
186 
187 static void s3c24xx_default_idle(void)
188 {
189         unsigned long tmp = 0;
190         int i;
191 
192         /* idle the system by using the idle mode which will wait for an
193          * interrupt to happen before restarting the system.
194          */
195 
196         /* Warning: going into idle state upsets jtag scanning */
197 
198         __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
199                      S3C2410_CLKCON);
200 
201         /* the samsung port seems to do a loop and then unset idle.. */
202         for (i = 0; i < 50; i++)
203                 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
204 
205         /* this bit is not cleared on re-start... */
206 
207         __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
208                      S3C2410_CLKCON);
209 }
210 
211 static struct samsung_pwm_variant s3c24xx_pwm_variant = {
212         .bits           = 16,
213         .div_base       = 1,
214         .has_tint_cstat = false,
215         .tclk_mask      = (1 << 4),
216 };
217 
218 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
219 {
220         arm_pm_idle = s3c24xx_default_idle;
221 
222         /* initialise the io descriptors we need for initialisation */
223         iotable_init(mach_desc, size);
224         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
225 
226         if (cpu_architecture() >= CPU_ARCH_ARMv5) {
227                 samsung_cpu_id = s3c24xx_read_idcode_v5();
228         } else {
229                 samsung_cpu_id = s3c24xx_read_idcode_v4();
230         }
231 
232         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
233 
234         samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
235 }
236 
237 void __init samsung_set_timer_source(unsigned int event, unsigned int source)
238 {
239         s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
240         s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
241 }
242 
243 void __init samsung_timer_init(void)
244 {
245         unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
246                 IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
247         };
248 
249         samsung_pwm_clocksource_init(S3C_VA_TIMER,
250                                         timer_irqs, &s3c24xx_pwm_variant);
251 }
252 
253 /* Serial port registrations */
254 
255 #define S3C2410_PA_UART0      (S3C24XX_PA_UART)
256 #define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
257 #define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
258 #define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
259 
260 static struct resource s3c2410_uart0_resource[] = {
261         [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
262         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
263                         IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
264                         NULL, IORESOURCE_IRQ)
265 };
266 
267 static struct resource s3c2410_uart1_resource[] = {
268         [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
269         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
270                         IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
271                         NULL, IORESOURCE_IRQ)
272 };
273 
274 static struct resource s3c2410_uart2_resource[] = {
275         [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
276         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
277                         IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
278                         NULL, IORESOURCE_IRQ)
279 };
280 
281 static struct resource s3c2410_uart3_resource[] = {
282         [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
283         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
284                         IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
285                         NULL, IORESOURCE_IRQ)
286 };
287 
288 struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
289         [0] = {
290                 .resources      = s3c2410_uart0_resource,
291                 .nr_resources   = ARRAY_SIZE(s3c2410_uart0_resource),
292         },
293         [1] = {
294                 .resources      = s3c2410_uart1_resource,
295                 .nr_resources   = ARRAY_SIZE(s3c2410_uart1_resource),
296         },
297         [2] = {
298                 .resources      = s3c2410_uart2_resource,
299                 .nr_resources   = ARRAY_SIZE(s3c2410_uart2_resource),
300         },
301         [3] = {
302                 .resources      = s3c2410_uart3_resource,
303                 .nr_resources   = ARRAY_SIZE(s3c2410_uart3_resource),
304         },
305 };
306 
307 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
308         defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
309 static struct resource s3c2410_dma_resource[] = {
310         [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
311         [1] = DEFINE_RES_IRQ(IRQ_DMA0),
312         [2] = DEFINE_RES_IRQ(IRQ_DMA1),
313         [3] = DEFINE_RES_IRQ(IRQ_DMA2),
314         [4] = DEFINE_RES_IRQ(IRQ_DMA3),
315 };
316 #endif
317 
318 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442)
319 static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = {
320         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
321         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
322         [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
323                                                 S3C24XX_DMA_CHANREQ(2, 2) |
324                                                 S3C24XX_DMA_CHANREQ(1, 3),
325         },
326         [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
327         [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
328         [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
329         [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
330         [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
331         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
332                                                  S3C24XX_DMA_CHANREQ(3, 2) |
333                                                  S3C24XX_DMA_CHANREQ(3, 3),
334         },
335         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
336                                                   S3C24XX_DMA_CHANREQ(1, 2),
337         },
338         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), },
339         [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
340         [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
341         [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
342         [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
343 };
344 
345 static struct s3c24xx_dma_platdata s3c2410_dma_platdata = {
346         .num_phy_channels = 4,
347         .channels = s3c2410_dma_channels,
348         .num_channels = DMACH_MAX,
349 };
350 
351 struct platform_device s3c2410_device_dma = {
352         .name           = "s3c2410-dma",
353         .id             = 0,
354         .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
355         .resource       = s3c2410_dma_resource,
356         .dev    = {
357                 .platform_data  = &s3c2410_dma_platdata,
358         },
359 };
360 #endif
361 
362 #ifdef CONFIG_CPU_S3C2412
363 static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
364         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
365         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
366         [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
367         [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
368         [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
369         [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
370         [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
371         [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
372         [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
373         [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
374         [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
375         [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
376         [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
377         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
378         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
379         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
380         [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 },
381         [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 },
382         [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 },
383         [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 },
384 };
385 
386 static struct s3c24xx_dma_platdata s3c2412_dma_platdata = {
387         .num_phy_channels = 4,
388         .channels = s3c2412_dma_channels,
389         .num_channels = DMACH_MAX,
390 };
391 
392 struct platform_device s3c2412_device_dma = {
393         .name           = "s3c2412-dma",
394         .id             = 0,
395         .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
396         .resource       = s3c2410_dma_resource,
397         .dev    = {
398                 .platform_data  = &s3c2412_dma_platdata,
399         },
400 };
401 #endif
402 
403 #if defined(CONFIG_CPU_S3C2440)
404 static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
405         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
406         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
407         [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
408                                                 S3C24XX_DMA_CHANREQ(6, 1) |
409                                                 S3C24XX_DMA_CHANREQ(2, 2) |
410                                                 S3C24XX_DMA_CHANREQ(1, 3),
411         },
412         [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
413         [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
414         [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
415         [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
416         [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
417         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
418                                                  S3C24XX_DMA_CHANREQ(3, 2) |
419                                                  S3C24XX_DMA_CHANREQ(3, 3),
420         },
421         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
422                                                   S3C24XX_DMA_CHANREQ(1, 2),
423         },
424         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) |
425                                                    S3C24XX_DMA_CHANREQ(0, 2),
426         },
427         [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) |
428                                                   S3C24XX_DMA_CHANREQ(5, 2),
429         },
430         [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) |
431                                                   S3C24XX_DMA_CHANREQ(6, 3),
432         },
433         [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) |
434                                                   S3C24XX_DMA_CHANREQ(5, 3),
435         },
436         [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
437         [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
438         [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
439         [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
440 };
441 
442 static struct s3c24xx_dma_platdata s3c2440_dma_platdata = {
443         .num_phy_channels = 4,
444         .channels = s3c2440_dma_channels,
445         .num_channels = DMACH_MAX,
446 };
447 
448 struct platform_device s3c2440_device_dma = {
449         .name           = "s3c2410-dma",
450         .id             = 0,
451         .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
452         .resource       = s3c2410_dma_resource,
453         .dev    = {
454                 .platform_data  = &s3c2440_dma_platdata,
455         },
456 };
457 #endif
458 
459 #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
460 static struct resource s3c2443_dma_resource[] = {
461         [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
462         [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0),
463         [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1),
464         [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2),
465         [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3),
466         [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4),
467         [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5),
468 };
469 
470 static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = {
471         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
472         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
473         [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
474         [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
475         [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
476         [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
477         [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
478         [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
479         [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
480         [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
481         [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 },
482         [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
483         [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
484         [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
485         [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 },
486         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
487         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
488         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
489         [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 },
490         [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 },
491         [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 },
492 };
493 
494 static struct s3c24xx_dma_platdata s3c2443_dma_platdata = {
495         .num_phy_channels = 6,
496         .channels = s3c2443_dma_channels,
497         .num_channels = DMACH_MAX,
498 };
499 
500 struct platform_device s3c2443_device_dma = {
501         .name           = "s3c2443-dma",
502         .id             = 0,
503         .num_resources  = ARRAY_SIZE(s3c2443_dma_resource),
504         .resource       = s3c2443_dma_resource,
505         .dev    = {
506                 .platform_data  = &s3c2443_dma_platdata,
507         },
508 };
509 #endif
510 
511 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410)
512 void __init s3c2410_init_clocks(int xtal)
513 {
514         s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
515 }
516 #endif
517 
518 #ifdef CONFIG_CPU_S3C2412
519 void __init s3c2412_init_clocks(int xtal)
520 {
521         s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
522 }
523 #endif
524 
525 #ifdef CONFIG_CPU_S3C2416
526 void __init s3c2416_init_clocks(int xtal)
527 {
528         s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
529 }
530 #endif
531 
532 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440)
533 void __init s3c2440_init_clocks(int xtal)
534 {
535         s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
536 }
537 #endif
538 
539 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442)
540 void __init s3c2442_init_clocks(int xtal)
541 {
542         s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
543 }
544 #endif
545 
546 #ifdef CONFIG_CPU_S3C2443
547 void __init s3c2443_init_clocks(int xtal)
548 {
549         s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
550 }
551 #endif
552 
553 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
554         defined(CONFIG_CPU_S3C2442)
555 static struct resource s3c2410_dclk_resource[] = {
556         [0] = DEFINE_RES_MEM(0x56000084, 0x4),
557 };
558 
559 struct platform_device s3c2410_device_dclk = {
560         .name           = "s3c2410-dclk",
561         .id             = 0,
562         .num_resources  = ARRAY_SIZE(s3c2410_dclk_resource),
563         .resource       = s3c2410_dclk_resource,
564 };
565 #endif
566 

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