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Linux/arch/arm/mach-s3c24xx/vr1000.h

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  1 
  2 /* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
  3  *
  4  * Copyright (c) 2003 Simtec Electronics
  5  *      Ben Dooks <ben@simtec.co.uk>
  6  *
  7  * VR1000 - CPLD control constants
  8  * Machine VR1000 - IRQ Number definitions
  9  * Machine VR1000 - Memory map definitions
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License version 2 as
 13  * published by the Free Software Foundation.
 14 */
 15 
 16 #ifndef __MACH_S3C24XX_VR1000_H
 17 #define __MACH_S3C24XX_VR1000_H __FILE__
 18 
 19 #define VR1000_CPLD_CTRL2_RAMWEN        (0x04)  /* SRAM Write Enable */
 20 
 21 /* irq numbers to onboard peripherals */
 22 
 23 #define VR1000_IRQ_USBOC                IRQ_EINT19
 24 #define VR1000_IRQ_IDE0                 IRQ_EINT16
 25 #define VR1000_IRQ_IDE1                 IRQ_EINT17
 26 #define VR1000_IRQ_SERIAL               IRQ_EINT12
 27 #define VR1000_IRQ_DM9000A              IRQ_EINT10
 28 #define VR1000_IRQ_DM9000N              IRQ_EINT9
 29 #define VR1000_IRQ_SMALERT              IRQ_EINT8
 30 
 31 /* map */
 32 
 33 #define VR1000_IOADDR(x)                (S3C2410_ADDR((x) + 0x01300000))
 34 
 35 /* we put the CPLD registers next, to get them out of the way */
 36 
 37 #define VR1000_VA_CTRL1                 VR1000_IOADDR(0x00000000) /* 0x01300000 */
 38 #define VR1000_PA_CTRL1                 (S3C2410_CS5 | 0x7800000)
 39 
 40 #define VR1000_VA_CTRL2                 VR1000_IOADDR(0x00100000) /* 0x01400000 */
 41 #define VR1000_PA_CTRL2                 (S3C2410_CS1 | 0x6000000)
 42 
 43 #define VR1000_VA_CTRL3                 VR1000_IOADDR(0x00200000) /* 0x01500000 */
 44 #define VR1000_PA_CTRL3                 (S3C2410_CS1 | 0x6800000)
 45 
 46 #define VR1000_VA_CTRL4                 VR1000_IOADDR(0x00300000) /* 0x01600000 */
 47 #define VR1000_PA_CTRL4                 (S3C2410_CS1 | 0x7000000)
 48 
 49 /* next, we have the PC104 ISA interrupt registers */
 50 
 51 #define VR1000_PA_PC104_IRQREQ          (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
 52 #define VR1000_VA_PC104_IRQREQ          VR1000_IOADDR(0x00400000)
 53 
 54 #define VR1000_PA_PC104_IRQRAW          (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
 55 #define VR1000_VA_PC104_IRQRAW          VR1000_IOADDR(0x00500000)
 56 
 57 #define VR1000_PA_PC104_IRQMASK         (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
 58 #define VR1000_VA_PC104_IRQMASK         VR1000_IOADDR(0x00600000)
 59 
 60 /*
 61  * 0xE0000000 contains the IO space that is split by speed and
 62  * whether the access is for 8 or 16bit IO... this ensures that
 63  * the correct access is made
 64  *
 65  * 0x10000000 of space, partitioned as so:
 66  *
 67  * 0x00000000 to 0x04000000  8bit,  slow
 68  * 0x04000000 to 0x08000000  16bit, slow
 69  * 0x08000000 to 0x0C000000  16bit, net
 70  * 0x0C000000 to 0x10000000  16bit, fast
 71  *
 72  * each of these spaces has the following in:
 73  *
 74  * 0x02000000 to 0x02100000 1MB  IDE primary channel
 75  * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
 76  * 0x02200000 to 0x02400000 1MB  IDE secondary channel
 77  * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
 78  * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controllers
 79  * 0x02600000 to 0x02700000 1MB
 80  *
 81  * the phyiscal layout of the zones are:
 82  *  nGCS2 - 8bit, slow
 83  *  nGCS3 - 16bit, slow
 84  *  nGCS4 - 16bit, net
 85  *  nGCS5 - 16bit, fast
 86  */
 87 
 88 #define VR1000_VA_MULTISPACE    (0xE0000000)
 89 
 90 #define VR1000_VA_ISAIO         (VR1000_VA_MULTISPACE + 0x00000000)
 91 #define VR1000_VA_ISAMEM        (VR1000_VA_MULTISPACE + 0x01000000)
 92 #define VR1000_VA_IDEPRI        (VR1000_VA_MULTISPACE + 0x02000000)
 93 #define VR1000_VA_IDEPRIAUX     (VR1000_VA_MULTISPACE + 0x02100000)
 94 #define VR1000_VA_IDESEC        (VR1000_VA_MULTISPACE + 0x02200000)
 95 #define VR1000_VA_IDESECAUX     (VR1000_VA_MULTISPACE + 0x02300000)
 96 #define VR1000_VA_ASIXNET       (VR1000_VA_MULTISPACE + 0x02400000)
 97 #define VR1000_VA_DM9000        (VR1000_VA_MULTISPACE + 0x02500000)
 98 #define VR1000_VA_SUPERIO       (VR1000_VA_MULTISPACE + 0x02600000)
 99 
100 /* physical offset addresses for the peripherals */
101 
102 #define VR1000_PA_IDEPRI        (0x02000000)
103 #define VR1000_PA_IDEPRIAUX     (0x02800000)
104 #define VR1000_PA_IDESEC        (0x03000000)
105 #define VR1000_PA_IDESECAUX     (0x03800000)
106 #define VR1000_PA_DM9000        (0x05000000)
107 
108 #define VR1000_PA_SERIAL        (0x11800000)
109 #define VR1000_VA_SERIAL        (VR1000_IOADDR(0x00700000))
110 
111 /* VR1000 ram is in CS1, with A26..A24 = 2_101 */
112 #define VR1000_PA_SRAM          (S3C2410_CS1 | 0x05000000)
113 
114 /* some configurations for the peripherals */
115 
116 #define VR1000_DM9000_CS        VR1000_VAM_CS4
117 
118 #endif /* __MACH_S3C24XX_VR1000_H */
119 

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