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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-shmobile/intc-sh73a0.c

Version: ~ [ linux-5.5-rc7 ] ~ [ linux-5.4.13 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.97 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.166 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.210 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.210 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.81 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * sh73a0 processor support - INTC hardware block
  3  *
  4  * Copyright (C) 2010  Magnus Damm
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; version 2 of the License.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  *
 15  * You should have received a copy of the GNU General Public License
 16  * along with this program; if not, write to the Free Software
 17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 18  */
 19 #include <linux/kernel.h>
 20 #include <linux/init.h>
 21 #include <linux/interrupt.h>
 22 #include <linux/module.h>
 23 #include <linux/irq.h>
 24 #include <linux/io.h>
 25 #include <linux/sh_intc.h>
 26 #include <linux/irqchip.h>
 27 #include <linux/irqchip/arm-gic.h>
 28 #include <mach/intc.h>
 29 #include <mach/irqs.h>
 30 #include <mach/sh73a0.h>
 31 #include <asm/mach-types.h>
 32 #include <asm/mach/arch.h>
 33 
 34 enum {
 35         UNUSED = 0,
 36 
 37         /* interrupt sources INTCS */
 38         PINTCS_PINT1, PINTCS_PINT2,
 39         RTDMAC_0_DEI0, RTDMAC_0_DEI1, RTDMAC_0_DEI2, RTDMAC_0_DEI3,
 40         CEU, MFI, BBIF2, VPU, TSIF1, _3DG_SGX543, _2DDMAC_2DDM0,
 41         RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR,
 42         KEYSC_KEY, VINT, MSIOF,
 43         TMU0_TUNI00, TMU0_TUNI01, TMU0_TUNI02,
 44         CMT0, TSIF0, CMT2, LMB, MSUG, MSU_MSU, MSU_MSU2,
 45         CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC,
 46         RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
 47         RTDMAC_3_DEI10, RTDMAC_3_DEI11,
 48         FRC, GCU, LCDC1, CSIRX,
 49         DSITX0_DSITX00, DSITX0_DSITX01,
 50         SPU2_SPU0, SPU2_SPU1, FSI,
 51         TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
 52         TSIF2, CMT4, MFIS2, CPORTS2R, TSG, DMASCH1, SCUW,
 53         VIO60, VIO61, CEU21, CSI21, DSITX1_DSITX10, DSITX1_DSITX11,
 54         DISP, DSRV, EMUX2_EMUX20I, EMUX2_EMUX21I,
 55         MSTIF0_MST00I, MSTIF0_MST01I, MSTIF1_MST10I, MSTIF1_MST11I,
 56         SPUV,
 57 
 58         /* interrupt groups INTCS */
 59         RTDMAC_0, RTDMAC_1, RTDMAC_2, RTDMAC_3,
 60         DSITX0, SPU2, TMU1, MSU,
 61 };
 62 
 63 static struct intc_vect intcs_vectors[] = {
 64         INTCS_VECT(PINTCS_PINT1, 0x0600), INTCS_VECT(PINTCS_PINT2, 0x0620),
 65         INTCS_VECT(RTDMAC_0_DEI0, 0x0800), INTCS_VECT(RTDMAC_0_DEI1, 0x0820),
 66         INTCS_VECT(RTDMAC_0_DEI2, 0x0840), INTCS_VECT(RTDMAC_0_DEI3, 0x0860),
 67         INTCS_VECT(CEU, 0x0880), INTCS_VECT(MFI, 0x0900),
 68         INTCS_VECT(BBIF2, 0x0960), INTCS_VECT(VPU, 0x0980),
 69         INTCS_VECT(TSIF1, 0x09a0), INTCS_VECT(_3DG_SGX543, 0x09e0),
 70         INTCS_VECT(_2DDMAC_2DDM0, 0x0a00),
 71         INTCS_VECT(RTDMAC_1_DEI4, 0x0b80), INTCS_VECT(RTDMAC_1_DEI5, 0x0ba0),
 72         INTCS_VECT(RTDMAC_1_DADERR, 0x0bc0),
 73         INTCS_VECT(KEYSC_KEY, 0x0be0), INTCS_VECT(VINT, 0x0c80),
 74         INTCS_VECT(MSIOF, 0x0d20),
 75         INTCS_VECT(TMU0_TUNI00, 0x0e80), INTCS_VECT(TMU0_TUNI01, 0x0ea0),
 76         INTCS_VECT(TMU0_TUNI02, 0x0ec0),
 77         INTCS_VECT(CMT0, 0x0f00), INTCS_VECT(TSIF0, 0x0f20),
 78         INTCS_VECT(CMT2, 0x0f40), INTCS_VECT(LMB, 0x0f60),
 79         INTCS_VECT(MSUG, 0x0f80),
 80         INTCS_VECT(MSU_MSU, 0x0fa0), INTCS_VECT(MSU_MSU2, 0x0fc0),
 81         INTCS_VECT(CTI, 0x0400), INTCS_VECT(RWDT0, 0x0440),
 82         INTCS_VECT(ICB, 0x0480), INTCS_VECT(PEP, 0x04a0),
 83         INTCS_VECT(ASA, 0x04c0), INTCS_VECT(JPU_JPEG, 0x0560),
 84         INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0),
 85         INTCS_VECT(RTDMAC_2_DEI6, 0x1300), INTCS_VECT(RTDMAC_2_DEI7, 0x1320),
 86         INTCS_VECT(RTDMAC_2_DEI8, 0x1340), INTCS_VECT(RTDMAC_2_DEI9, 0x1360),
 87         INTCS_VECT(RTDMAC_3_DEI10, 0x1380), INTCS_VECT(RTDMAC_3_DEI11, 0x13a0),
 88         INTCS_VECT(FRC, 0x1700), INTCS_VECT(GCU, 0x1760),
 89         INTCS_VECT(LCDC1, 0x1780), INTCS_VECT(CSIRX, 0x17a0),
 90         INTCS_VECT(DSITX0_DSITX00, 0x17c0), INTCS_VECT(DSITX0_DSITX01, 0x17e0),
 91         INTCS_VECT(SPU2_SPU0, 0x1800), INTCS_VECT(SPU2_SPU1, 0x1820),
 92         INTCS_VECT(FSI, 0x1840),
 93         INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
 94         INTCS_VECT(TMU1_TUNI12, 0x1940),
 95         INTCS_VECT(TSIF2, 0x1960), INTCS_VECT(CMT4, 0x1980),
 96         INTCS_VECT(MFIS2, 0x1a00), INTCS_VECT(CPORTS2R, 0x1a20),
 97         INTCS_VECT(TSG, 0x1ae0), INTCS_VECT(DMASCH1, 0x1b00),
 98         INTCS_VECT(SCUW, 0x1b40),
 99         INTCS_VECT(VIO60, 0x1b60), INTCS_VECT(VIO61, 0x1b80),
100         INTCS_VECT(CEU21, 0x1ba0), INTCS_VECT(CSI21, 0x1be0),
101         INTCS_VECT(DSITX1_DSITX10, 0x1c00), INTCS_VECT(DSITX1_DSITX11, 0x1c20),
102         INTCS_VECT(DISP, 0x1c40), INTCS_VECT(DSRV, 0x1c60),
103         INTCS_VECT(EMUX2_EMUX20I, 0x1c80), INTCS_VECT(EMUX2_EMUX21I, 0x1ca0),
104         INTCS_VECT(MSTIF0_MST00I, 0x1cc0), INTCS_VECT(MSTIF0_MST01I, 0x1ce0),
105         INTCS_VECT(MSTIF1_MST10I, 0x1d00), INTCS_VECT(MSTIF1_MST11I, 0x1d20),
106         INTCS_VECT(SPUV, 0x2300),
107 };
108 
109 static struct intc_group intcs_groups[] __initdata = {
110         INTC_GROUP(RTDMAC_0, RTDMAC_0_DEI0, RTDMAC_0_DEI1,
111                    RTDMAC_0_DEI2, RTDMAC_0_DEI3),
112         INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR),
113         INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI6, RTDMAC_2_DEI7,
114                    RTDMAC_2_DEI8, RTDMAC_2_DEI9),
115         INTC_GROUP(RTDMAC_3, RTDMAC_3_DEI10, RTDMAC_3_DEI11),
116         INTC_GROUP(TMU1, TMU1_TUNI12, TMU1_TUNI11, TMU1_TUNI10),
117         INTC_GROUP(DSITX0, DSITX0_DSITX00, DSITX0_DSITX01),
118         INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
119         INTC_GROUP(MSU, MSU_MSU, MSU_MSU2),
120 };
121 
122 static struct intc_mask_reg intcs_mask_registers[] = {
123         { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
124           { 0, 0, 0, CEU,
125             0, 0, 0, 0 } },
126         { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
127           { 0, 0, 0, VPU,
128             BBIF2, 0, 0, MFI } },
129         { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
130           { 0, 0, 0, _2DDMAC_2DDM0,
131             0, ASA, PEP, ICB } },
132         { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
133           { 0, 0, 0, CTI,
134             JPU_JPEG, 0, LCRC, LCDC } },
135         { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
136           { KEYSC_KEY, RTDMAC_1_DADERR, RTDMAC_1_DEI5, RTDMAC_1_DEI4,
137             RTDMAC_0_DEI3, RTDMAC_0_DEI2, RTDMAC_0_DEI1, RTDMAC_0_DEI0 } },
138         { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
139           { 0, 0, MSIOF, 0,
140             _3DG_SGX543, 0, 0, 0 } },
141         { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
142           { 0, TMU0_TUNI02, TMU0_TUNI01, TMU0_TUNI00,
143             0, 0, 0, 0 } },
144         { 0xffd201a0, 0xffd201e0, 8, /* IMR8SA / IMCR8SA */
145           { 0, 0, 0, 0,
146             0, MSU_MSU, MSU_MSU2, MSUG } },
147         { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
148           { 0, RWDT0, CMT2, CMT0,
149             0, 0, 0, 0 } },
150         { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
151           { 0, 0, 0, 0,
152             0, TSIF1, LMB, TSIF0 } },
153         { 0xffd201b0, 0xffd201f0, 8, /* IMR12SA / IMCR12SA */
154           { 0, 0, 0, 0,
155             0, 0, PINTCS_PINT2, PINTCS_PINT1 } },
156         { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
157           { RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
158             RTDMAC_3_DEI10, RTDMAC_3_DEI11, 0, 0 } },
159         { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
160           { FRC, 0, 0, GCU,
161             LCDC1, CSIRX, DSITX0_DSITX00, DSITX0_DSITX01 } },
162         { 0xffd50194, 0xffd501d4, 8, /* IMR5SA3 / IMCR5SA3 */
163           { SPU2_SPU0, SPU2_SPU1, FSI, 0,
164             0, 0, 0, 0 } },
165         { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
166           { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 0,
167             TSIF2, CMT4, 0, 0 } },
168         { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
169           { MFIS2, CPORTS2R, 0, 0,
170             0, 0, 0, TSG } },
171         { 0xffd501a0, 0xffd501e0, 8, /* IMR8SA3 / IMCR8SA3 */
172           { DMASCH1, 0, SCUW, VIO60,
173             VIO61, CEU21, 0, CSI21 } },
174         { 0xffd501a4, 0xffd501e4, 8, /* IMR9SA3 / IMCR9SA3 */
175           { DSITX1_DSITX10, DSITX1_DSITX11, DISP, DSRV,
176             EMUX2_EMUX20I, EMUX2_EMUX21I, MSTIF0_MST00I, MSTIF0_MST01I } },
177         { 0xffd501a8, 0xffd501e8, 8, /* IMR10SA3 / IMCR10SA3 */
178           { MSTIF0_MST00I, MSTIF0_MST01I, 0, 0,
179             0, 0, 0, 0  } },
180         { 0xffd60180, 0xffd601c0, 8, /* IMR0SA4 / IMCR0SA4 */
181           { SPUV, 0, 0, 0,
182             0, 0, 0, 0  } },
183 };
184 
185 /* Priority is needed for INTCA to receive the INTCS interrupt */
186 static struct intc_prio_reg intcs_prio_registers[] = {
187         { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC_2DDM0, ICB } },
188         { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
189         { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
190         { 0xffd2000c, 0, 16, 4, /* IPRDS */ { PINTCS_PINT1, PINTCS_PINT2,
191                                               0, 0 } },
192         { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_0, CEU, MFI, VPU } },
193         { 0xffd20014, 0, 16, 4, /* IPRFS */ { KEYSC_KEY, RTDMAC_1,
194                                               CMT2, CMT0 } },
195         { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_TUNI00, TMU0_TUNI01,
196                                               TMU0_TUNI02, TSIF1 } },
197         { 0xffd2001c, 0, 16, 4, /* IPRHS */ { VINT, 0, 0, 0 } },
198         { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, 0 } },
199         { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX543, MSUG, MSU } },
200         { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, ASA, LMB, PEP } },
201         { 0xffd20030, 0, 16, 4, /* IPRMS */ { 0, 0, 0, RWDT0 } },
202         { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC_2, 0, 0, 0 } },
203         { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC_3, 0, 0, 0 } },
204         { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { FRC, 0, 0, 0 } },
205         { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX0, 0 } },
206         { 0xffd50028, 0, 16, 4, /* IPRKS3 */ { SPU2, 0, FSI, 0 } },
207         { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, TSIF2 } },
208         { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, 0, 0, 0 } },
209         { 0xffd50038, 0, 16, 4, /* IPROS3 */ { MFIS2, CPORTS2R, 0, 0 } },
210         { 0xffd50040, 0, 16, 4, /* IPRQS3 */ { DMASCH1, 0, SCUW, VIO60 } },
211         { 0xffd50044, 0, 16, 4, /* IPRRS3 */ { VIO61, CEU21, 0, CSI21 } },
212         { 0xffd50048, 0, 16, 4, /* IPRSS3 */ { DSITX1_DSITX10, DSITX1_DSITX11,
213                                                DISP, DSRV } },
214         { 0xffd5004c, 0, 16, 4, /* IPRTS3 */ { EMUX2_EMUX20I, EMUX2_EMUX21I,
215                                                MSTIF0_MST00I, MSTIF0_MST01I } },
216         { 0xffd50050, 0, 16, 4, /* IPRUS3 */ { MSTIF1_MST10I, MSTIF1_MST11I,
217                                                0, 0 } },
218         { 0xffd60000, 0, 16, 4, /* IPRAS4 */ { SPUV, 0, 0, 0 } },
219 };
220 
221 static struct resource intcs_resources[] __initdata = {
222         [0] = {
223                 .start  = 0xffd20000,
224                 .end    = 0xffd201ff,
225                 .flags  = IORESOURCE_MEM,
226         },
227         [1] = {
228                 .start  = 0xffd50000,
229                 .end    = 0xffd501ff,
230                 .flags  = IORESOURCE_MEM,
231         },
232         [2] = {
233                 .start  = 0xffd60000,
234                 .end    = 0xffd601ff,
235                 .flags  = IORESOURCE_MEM,
236         }
237 };
238 
239 static struct intc_desc intcs_desc __initdata = {
240         .name = "sh73a0-intcs",
241         .resource = intcs_resources,
242         .num_resources = ARRAY_SIZE(intcs_resources),
243         .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
244                            intcs_prio_registers, NULL, NULL),
245 };
246 
247 static struct irqaction sh73a0_intcs_cascade;
248 
249 static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id)
250 {
251         unsigned int evtcodeas = ioread32((void __iomem *)dev_id);
252 
253         generic_handle_irq(intcs_evt2irq(evtcodeas));
254 
255         return IRQ_HANDLED;
256 }
257 
258 static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
259 {
260         return 0; /* always allow wakeup */
261 }
262 
263 #define PINTER0_PHYS 0xe69000a0
264 #define PINTER1_PHYS 0xe69000a4
265 #define PINTER0_VIRT IOMEM(0xe69000a0)
266 #define PINTER1_VIRT IOMEM(0xe69000a4)
267 #define PINTRR0 IOMEM(0xe69000d0)
268 #define PINTRR1 IOMEM(0xe69000d4)
269 
270 #define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq))
271 #define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8))
272 #define PINT0C_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 16))
273 #define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24))
274 #define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq))
275 
276 INTC_PINT(intc_pint0, PINTER0_PHYS, 0xe69000b0, "sh73a0-pint0",         \
277   INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D),       \
278   INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ),               \
279   INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ),               \
280   INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D),       \
281   INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D));
282 
283 INTC_PINT(intc_pint1, PINTER1_PHYS, 0xe69000c0, "sh73a0-pint1",         \
284   INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \
285   INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE,                         \
286   INTC_PINT_V_NONE, INTC_PINT_V_NONE,                                   \
287   INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E(E), \
288   INTC_PINT_E(E), INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE);
289 
290 static struct irqaction sh73a0_pint0_cascade;
291 static struct irqaction sh73a0_pint1_cascade;
292 
293 static void pint_demux(void __iomem *rr, void __iomem *er, int base_irq)
294 {
295         unsigned long value =  ioread32(rr) & ioread32(er);
296         int k;
297 
298         for (k = 0; k < 32; k++) {
299                 if (value & (1 << (31 - k))) {
300                         generic_handle_irq(base_irq + k);
301                         iowrite32(~(1 << (31 - k)), rr);
302                 }
303         }
304 }
305 
306 static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id)
307 {
308         pint_demux(PINTRR0, PINTER0_VIRT, SH73A0_PINT0_IRQ(0));
309         return IRQ_HANDLED;
310 }
311 
312 static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id)
313 {
314         pint_demux(PINTRR1, PINTER1_VIRT, SH73A0_PINT1_IRQ(0));
315         return IRQ_HANDLED;
316 }
317 
318 void __init sh73a0_init_irq(void)
319 {
320         void __iomem *gic_dist_base = IOMEM(0xf0001000);
321         void __iomem *gic_cpu_base = IOMEM(0xf0000100);
322         void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
323 
324         gic_init(0, 29, gic_dist_base, gic_cpu_base);
325         gic_arch_extn.irq_set_wake = sh73a0_set_wake;
326 
327         register_intc_controller(&intcs_desc);
328         register_intc_controller(&intc_pint0_desc);
329         register_intc_controller(&intc_pint1_desc);
330 
331         /* demux using INTEVTSA */
332         sh73a0_intcs_cascade.name = "INTCS cascade";
333         sh73a0_intcs_cascade.handler = sh73a0_intcs_demux;
334         sh73a0_intcs_cascade.dev_id = intevtsa;
335         setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
336 
337         /* PINT pins are sanely tied to the GIC as SPI */
338         sh73a0_pint0_cascade.name = "PINT0 cascade";
339         sh73a0_pint0_cascade.handler = sh73a0_pint0_demux;
340         setup_irq(gic_spi(33), &sh73a0_pint0_cascade);
341 
342         sh73a0_pint1_cascade.name = "PINT1 cascade";
343         sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
344         setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
345 }
346 

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