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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-tegra/gpio.c

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  1 /*
  2  * arch/arm/mach-tegra/gpio.c
  3  *
  4  * Copyright (c) 2010 Google, Inc
  5  *
  6  * Author:
  7  *      Erik Gilling <konkers@google.com>
  8  *
  9  * This software is licensed under the terms of the GNU General Public
 10  * License version 2, as published by the Free Software Foundation, and
 11  * may be copied, distributed, and modified under those terms.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  */
 19 
 20 #include <linux/init.h>
 21 #include <linux/irq.h>
 22 #include <linux/interrupt.h>
 23 
 24 #include <linux/io.h>
 25 #include <linux/gpio.h>
 26 
 27 #include <mach/iomap.h>
 28 #include <mach/suspend.h>
 29 
 30 #define GPIO_BANK(x)            ((x) >> 5)
 31 #define GPIO_PORT(x)            (((x) >> 3) & 0x3)
 32 #define GPIO_BIT(x)             ((x) & 0x7)
 33 
 34 #define GPIO_REG(x)             (IO_TO_VIRT(TEGRA_GPIO_BASE) +  \
 35                                  GPIO_BANK(x) * 0x80 +          \
 36                                  GPIO_PORT(x) * 4)
 37 
 38 #define GPIO_CNF(x)             (GPIO_REG(x) + 0x00)
 39 #define GPIO_OE(x)              (GPIO_REG(x) + 0x10)
 40 #define GPIO_OUT(x)             (GPIO_REG(x) + 0X20)
 41 #define GPIO_IN(x)              (GPIO_REG(x) + 0x30)
 42 #define GPIO_INT_STA(x)         (GPIO_REG(x) + 0x40)
 43 #define GPIO_INT_ENB(x)         (GPIO_REG(x) + 0x50)
 44 #define GPIO_INT_LVL(x)         (GPIO_REG(x) + 0x60)
 45 #define GPIO_INT_CLR(x)         (GPIO_REG(x) + 0x70)
 46 
 47 #define GPIO_MSK_CNF(x)         (GPIO_REG(x) + 0x800)
 48 #define GPIO_MSK_OE(x)          (GPIO_REG(x) + 0x810)
 49 #define GPIO_MSK_OUT(x)         (GPIO_REG(x) + 0X820)
 50 #define GPIO_MSK_INT_STA(x)     (GPIO_REG(x) + 0x840)
 51 #define GPIO_MSK_INT_ENB(x)     (GPIO_REG(x) + 0x850)
 52 #define GPIO_MSK_INT_LVL(x)     (GPIO_REG(x) + 0x860)
 53 
 54 #define GPIO_INT_LVL_MASK               0x010101
 55 #define GPIO_INT_LVL_EDGE_RISING        0x000101
 56 #define GPIO_INT_LVL_EDGE_FALLING       0x000100
 57 #define GPIO_INT_LVL_EDGE_BOTH          0x010100
 58 #define GPIO_INT_LVL_LEVEL_HIGH         0x000001
 59 #define GPIO_INT_LVL_LEVEL_LOW          0x000000
 60 
 61 struct tegra_gpio_bank {
 62         int bank;
 63         int irq;
 64         spinlock_t lvl_lock[4];
 65 #ifdef CONFIG_PM
 66         u32 cnf[4];
 67         u32 out[4];
 68         u32 oe[4];
 69         u32 int_enb[4];
 70         u32 int_lvl[4];
 71 #endif
 72 };
 73 
 74 
 75 static struct tegra_gpio_bank tegra_gpio_banks[] = {
 76         {.bank = 0, .irq = INT_GPIO1},
 77         {.bank = 1, .irq = INT_GPIO2},
 78         {.bank = 2, .irq = INT_GPIO3},
 79         {.bank = 3, .irq = INT_GPIO4},
 80         {.bank = 4, .irq = INT_GPIO5},
 81         {.bank = 5, .irq = INT_GPIO6},
 82         {.bank = 6, .irq = INT_GPIO7},
 83 };
 84 
 85 static int tegra_gpio_compose(int bank, int port, int bit)
 86 {
 87         return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
 88 }
 89 
 90 static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
 91 {
 92         u32 val;
 93 
 94         val = 0x100 << GPIO_BIT(gpio);
 95         if (value)
 96                 val |= 1 << GPIO_BIT(gpio);
 97         __raw_writel(val, reg);
 98 }
 99 
100 void tegra_gpio_enable(int gpio)
101 {
102         tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
103 }
104 
105 void tegra_gpio_disable(int gpio)
106 {
107         tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
108 }
109 
110 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
111 {
112         tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
113 }
114 
115 static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
116 {
117         return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
118 }
119 
120 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
121 {
122         tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
123         return 0;
124 }
125 
126 static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
127                                         int value)
128 {
129         tegra_gpio_set(chip, offset, value);
130         tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
131         return 0;
132 }
133 
134 
135 
136 static struct gpio_chip tegra_gpio_chip = {
137         .label                  = "tegra-gpio",
138         .direction_input        = tegra_gpio_direction_input,
139         .get                    = tegra_gpio_get,
140         .direction_output       = tegra_gpio_direction_output,
141         .set                    = tegra_gpio_set,
142         .base                   = 0,
143         .ngpio                  = TEGRA_NR_GPIOS,
144 };
145 
146 static void tegra_gpio_irq_ack(struct irq_data *d)
147 {
148         int gpio = d->irq - INT_GPIO_BASE;
149 
150         __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
151 }
152 
153 static void tegra_gpio_irq_mask(struct irq_data *d)
154 {
155         int gpio = d->irq - INT_GPIO_BASE;
156 
157         tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
158 }
159 
160 static void tegra_gpio_irq_unmask(struct irq_data *d)
161 {
162         int gpio = d->irq - INT_GPIO_BASE;
163 
164         tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
165 }
166 
167 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
168 {
169         int gpio = d->irq - INT_GPIO_BASE;
170         struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
171         int port = GPIO_PORT(gpio);
172         int lvl_type;
173         int val;
174         unsigned long flags;
175 
176         switch (type & IRQ_TYPE_SENSE_MASK) {
177         case IRQ_TYPE_EDGE_RISING:
178                 lvl_type = GPIO_INT_LVL_EDGE_RISING;
179                 break;
180 
181         case IRQ_TYPE_EDGE_FALLING:
182                 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
183                 break;
184 
185         case IRQ_TYPE_EDGE_BOTH:
186                 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
187                 break;
188 
189         case IRQ_TYPE_LEVEL_HIGH:
190                 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
191                 break;
192 
193         case IRQ_TYPE_LEVEL_LOW:
194                 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
195                 break;
196 
197         default:
198                 return -EINVAL;
199         }
200 
201         spin_lock_irqsave(&bank->lvl_lock[port], flags);
202 
203         val = __raw_readl(GPIO_INT_LVL(gpio));
204         val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
205         val |= lvl_type << GPIO_BIT(gpio);
206         __raw_writel(val, GPIO_INT_LVL(gpio));
207 
208         spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
209 
210         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
211                 __irq_set_handler_locked(d->irq, handle_level_irq);
212         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
213                 __irq_set_handler_locked(d->irq, handle_edge_irq);
214 
215         return 0;
216 }
217 
218 static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
219 {
220         struct tegra_gpio_bank *bank;
221         int port;
222         int pin;
223         int unmasked = 0;
224 
225         desc->irq_data.chip->irq_ack(&desc->irq_data);
226 
227         bank = irq_get_handler_data(irq);
228 
229         for (port = 0; port < 4; port++) {
230                 int gpio = tegra_gpio_compose(bank->bank, port, 0);
231                 unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
232                         __raw_readl(GPIO_INT_ENB(gpio));
233                 u32 lvl = __raw_readl(GPIO_INT_LVL(gpio));
234 
235                 for_each_set_bit(pin, &sta, 8) {
236                         __raw_writel(1 << pin, GPIO_INT_CLR(gpio));
237 
238                         /* if gpio is edge triggered, clear condition
239                          * before executing the hander so that we don't
240                          * miss edges
241                          */
242                         if (lvl & (0x100 << pin)) {
243                                 unmasked = 1;
244                                 desc->irq_data.chip->irq_unmask(&desc->irq_data);
245                         }
246 
247                         generic_handle_irq(gpio_to_irq(gpio + pin));
248                 }
249         }
250 
251         if (!unmasked)
252                 desc->irq_data.chip->irq_unmask(&desc->irq_data);
253 
254 }
255 
256 #ifdef CONFIG_PM
257 void tegra_gpio_resume(void)
258 {
259         unsigned long flags;
260         int b;
261         int p;
262 
263         local_irq_save(flags);
264 
265         for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
266                 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
267 
268                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
269                         unsigned int gpio = (b<<5) | (p<<3);
270                         __raw_writel(bank->cnf[p], GPIO_CNF(gpio));
271                         __raw_writel(bank->out[p], GPIO_OUT(gpio));
272                         __raw_writel(bank->oe[p], GPIO_OE(gpio));
273                         __raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
274                         __raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
275                 }
276         }
277 
278         local_irq_restore(flags);
279 }
280 
281 void tegra_gpio_suspend(void)
282 {
283         unsigned long flags;
284         int b;
285         int p;
286 
287         local_irq_save(flags);
288         for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
289                 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
290 
291                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
292                         unsigned int gpio = (b<<5) | (p<<3);
293                         bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
294                         bank->out[p] = __raw_readl(GPIO_OUT(gpio));
295                         bank->oe[p] = __raw_readl(GPIO_OE(gpio));
296                         bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
297                         bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
298                 }
299         }
300         local_irq_restore(flags);
301 }
302 
303 static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
304 {
305         struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
306         return irq_set_irq_wake(bank->irq, enable);
307 }
308 #endif
309 
310 static struct irq_chip tegra_gpio_irq_chip = {
311         .name           = "GPIO",
312         .irq_ack        = tegra_gpio_irq_ack,
313         .irq_mask       = tegra_gpio_irq_mask,
314         .irq_unmask     = tegra_gpio_irq_unmask,
315         .irq_set_type   = tegra_gpio_irq_set_type,
316 #ifdef CONFIG_PM
317         .irq_set_wake   = tegra_gpio_wake_enable,
318 #endif
319 };
320 
321 
322 /* This lock class tells lockdep that GPIO irqs are in a different
323  * category than their parents, so it won't report false recursion.
324  */
325 static struct lock_class_key gpio_lock_class;
326 
327 static int __init tegra_gpio_init(void)
328 {
329         struct tegra_gpio_bank *bank;
330         int i;
331         int j;
332 
333         for (i = 0; i < 7; i++) {
334                 for (j = 0; j < 4; j++) {
335                         int gpio = tegra_gpio_compose(i, j, 0);
336                         __raw_writel(0x00, GPIO_INT_ENB(gpio));
337                 }
338         }
339 
340         gpiochip_add(&tegra_gpio_chip);
341 
342         for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
343                 bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))];
344 
345                 irq_set_lockdep_class(i, &gpio_lock_class);
346                 irq_set_chip_data(i, bank);
347                 irq_set_chip_and_handler(i, &tegra_gpio_irq_chip,
348                                          handle_simple_irq);
349                 set_irq_flags(i, IRQF_VALID);
350         }
351 
352         for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
353                 bank = &tegra_gpio_banks[i];
354 
355                 irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
356                 irq_set_handler_data(bank->irq, bank);
357 
358                 for (j = 0; j < 4; j++)
359                         spin_lock_init(&bank->lvl_lock[j]);
360         }
361 
362         return 0;
363 }
364 
365 postcore_initcall(tegra_gpio_init);
366 
367 void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
368 {
369         int i;
370 
371         for (i = 0; i < num; i++) {
372                 int gpio = table[i].gpio;
373 
374                 if (table[i].enable)
375                         tegra_gpio_enable(gpio);
376                 else
377                         tegra_gpio_disable(gpio);
378         }
379 }
380 
381 #ifdef  CONFIG_DEBUG_FS
382 
383 #include <linux/debugfs.h>
384 #include <linux/seq_file.h>
385 
386 static int dbg_gpio_show(struct seq_file *s, void *unused)
387 {
388         int i;
389         int j;
390 
391         for (i = 0; i < 7; i++) {
392                 for (j = 0; j < 4; j++) {
393                         int gpio = tegra_gpio_compose(i, j, 0);
394                         seq_printf(s,
395                                 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
396                                 i, j,
397                                 __raw_readl(GPIO_CNF(gpio)),
398                                 __raw_readl(GPIO_OE(gpio)),
399                                 __raw_readl(GPIO_OUT(gpio)),
400                                 __raw_readl(GPIO_IN(gpio)),
401                                 __raw_readl(GPIO_INT_STA(gpio)),
402                                 __raw_readl(GPIO_INT_ENB(gpio)),
403                                 __raw_readl(GPIO_INT_LVL(gpio)));
404                 }
405         }
406         return 0;
407 }
408 
409 static int dbg_gpio_open(struct inode *inode, struct file *file)
410 {
411         return single_open(file, dbg_gpio_show, &inode->i_private);
412 }
413 
414 static const struct file_operations debug_fops = {
415         .open           = dbg_gpio_open,
416         .read           = seq_read,
417         .llseek         = seq_lseek,
418         .release        = single_release,
419 };
420 
421 static int __init tegra_gpio_debuginit(void)
422 {
423         (void) debugfs_create_file("tegra_gpio", S_IRUGO,
424                                         NULL, NULL, &debug_fops);
425         return 0;
426 }
427 late_initcall(tegra_gpio_debuginit);
428 #endif
429 

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