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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-u300/clock.c

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  1 /*
  2  *
  3  * arch/arm/mach-u300/clock.c
  4  *
  5  *
  6  * Copyright (C) 2007-2009 ST-Ericsson AB
  7  * License terms: GNU General Public License (GPL) version 2
  8  * Define clocks in the app platform.
  9  * Author: Linus Walleij <linus.walleij@stericsson.com>
 10  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
 11  *
 12  */
 13 #include <linux/module.h>
 14 #include <linux/kernel.h>
 15 #include <linux/list.h>
 16 #include <linux/errno.h>
 17 #include <linux/err.h>
 18 #include <linux/string.h>
 19 #include <linux/clk.h>
 20 #include <linux/mutex.h>
 21 #include <linux/spinlock.h>
 22 #include <linux/debugfs.h>
 23 #include <linux/device.h>
 24 #include <linux/init.h>
 25 #include <linux/timer.h>
 26 #include <linux/io.h>
 27 #include <linux/seq_file.h>
 28 #include <linux/clkdev.h>
 29 
 30 #include <mach/hardware.h>
 31 #include <mach/syscon.h>
 32 
 33 #include "clock.h"
 34 
 35 /*
 36  * TODO:
 37  * - move all handling of the CCR register into this file and create
 38  *   a spinlock for the CCR register
 39  * - switch to the clkdevice lookup mechanism that maps clocks to
 40  *   device ID:s instead when it becomes available in kernel 2.6.29.
 41  * - implement rate get/set for all clocks that need it.
 42  */
 43 
 44 /*
 45  * Syscon clock I/O registers lock so clock requests don't collide
 46  * NOTE: this is a local lock only used to lock access to clock and
 47  * reset registers in syscon.
 48  */
 49 static DEFINE_SPINLOCK(syscon_clkreg_lock);
 50 static DEFINE_SPINLOCK(syscon_resetreg_lock);
 51 
 52 /*
 53  * The clocking hierarchy currently looks like this.
 54  * NOTE: the idea is NOT to show how the clocks are routed on the chip!
 55  * The ideas is to show dependencies, so a clock higher up in the
 56  * hierarchy has to be on in order for another clock to be on. Now,
 57  * both CPU and DMA can actually be on top of the hierarchy, and that
 58  * is not modeled currently. Instead we have the backbone AMBA bus on
 59  * top. This bus cannot be programmed in any way but conceptually it
 60  * needs to be active for the bridges and devices to transport data.
 61  *
 62  * Please be aware that a few clocks are hw controlled, which mean that
 63  * the hw itself can turn on/off or change the rate of the clock when
 64  * needed!
 65  *
 66  *  AMBA bus
 67  *  |
 68  *  +- CPU
 69  *  +- FSMC NANDIF NAND Flash interface
 70  *  +- SEMI Shared Memory interface
 71  *  +- ISP Image Signal Processor (U335 only)
 72  *  +- CDS (U335 only)
 73  *  +- DMA Direct Memory Access Controller
 74  *  +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
 75  *  +- APEX
 76  *  +- VIDEO_ENC AVE2/3 Video Encoder
 77  *  +- XGAM Graphics Accelerator Controller
 78  *  +- AHB
 79  *  |
 80  *  +- ahb:0 AHB Bridge
 81  *  |  |
 82  *  |  +- ahb:1 INTCON Interrupt controller
 83  *  |  +- ahb:3 MSPRO  Memory Stick Pro controller
 84  *  |  +- ahb:4 EMIF   External Memory interface
 85  *  |
 86  *  +- fast:0 FAST bridge
 87  *  |  |
 88  *  |  +- fast:1 MMCSD MMC/SD card reader controller
 89  *  |  +- fast:2 I2S0  PCM I2S channel 0 controller
 90  *  |  +- fast:3 I2S1  PCM I2S channel 1 controller
 91  *  |  +- fast:4 I2C0  I2C channel 0 controller
 92  *  |  +- fast:5 I2C1  I2C channel 1 controller
 93  *  |  +- fast:6 SPI   SPI controller
 94  *  |  +- fast:7 UART1 Secondary UART (U335 only)
 95  *  |
 96  *  +- slow:0 SLOW bridge
 97  *     |
 98  *     +- slow:1 SYSCON (not possible to control)
 99  *     +- slow:2 WDOG Watchdog
100  *     +- slow:3 UART0 primary UART
101  *     +- slow:4 TIMER_APP Application timer - used in Linux
102  *     +- slow:5 KEYPAD controller
103  *     +- slow:6 GPIO controller
104  *     +- slow:7 RTC controller
105  *     +- slow:8 BT Bus Tracer (not used currently)
106  *     +- slow:9 EH Event Handler (not used currently)
107  *     +- slow:a TIMER_ACC Access style timer (not used currently)
108  *     +- slow:b PPM (U335 only, what is that?)
109  */
110 
111 /*
112  * Reset control functions. We remember if a block has been
113  * taken out of reset and don't remove the reset assertion again
114  * and vice versa. Currently we only remove resets so the
115  * enablement function is defined out.
116  */
117 static void syscon_block_reset_enable(struct clk *clk)
118 {
119         u16 val;
120         unsigned long iflags;
121 
122         /* Not all blocks support resetting */
123         if (!clk->res_reg || !clk->res_mask)
124                 return;
125         spin_lock_irqsave(&syscon_resetreg_lock, iflags);
126         val = readw(clk->res_reg);
127         val |= clk->res_mask;
128         writew(val, clk->res_reg);
129         spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
130         clk->reset = true;
131 }
132 
133 static void syscon_block_reset_disable(struct clk *clk)
134 {
135         u16 val;
136         unsigned long iflags;
137 
138         /* Not all blocks support resetting */
139         if (!clk->res_reg || !clk->res_mask)
140                 return;
141         spin_lock_irqsave(&syscon_resetreg_lock, iflags);
142         val = readw(clk->res_reg);
143         val &= ~clk->res_mask;
144         writew(val, clk->res_reg);
145         spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
146         clk->reset = false;
147 }
148 
149 int __clk_get(struct clk *clk)
150 {
151         u16 val;
152 
153         /* The MMC and MSPRO clocks need some special set-up */
154         if (!strcmp(clk->name, "MCLK")) {
155                 /* Set default MMC clock divisor to 18.9 MHz */
156                 writew(0x0054U, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
157                 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
158                 /* Disable the MMC feedback clock */
159                 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
160                 /* Disable MSPRO frequency */
161                 val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
162                 writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
163         }
164         if (!strcmp(clk->name, "MSPRO")) {
165                 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
166                 /* Disable the MMC feedback clock */
167                 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
168                 /* Enable MSPRO frequency */
169                 val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
170                 writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
171         }
172         return 1;
173 }
174 EXPORT_SYMBOL(__clk_get);
175 
176 void __clk_put(struct clk *clk)
177 {
178 }
179 EXPORT_SYMBOL(__clk_put);
180 
181 static void syscon_clk_disable(struct clk *clk)
182 {
183         unsigned long iflags;
184 
185         /* Don't touch the hardware controlled clocks */
186         if (clk->hw_ctrld)
187                 return;
188 
189         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
190         writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCDR);
191         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
192 }
193 
194 static void syscon_clk_enable(struct clk *clk)
195 {
196         unsigned long iflags;
197 
198         /* Don't touch the hardware controlled clocks */
199         if (clk->hw_ctrld)
200                 return;
201 
202         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
203         writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCER);
204         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
205 }
206 
207 static u16 syscon_clk_get_rate(void)
208 {
209         u16 val;
210         unsigned long iflags;
211 
212         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
213         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
214         val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
215         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
216         return val;
217 }
218 
219 #ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
220 static void enable_i2s0_vcxo(void)
221 {
222         u16 val;
223         unsigned long iflags;
224 
225         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
226         /* Set I2S0 to use the VCXO 26 MHz clock */
227         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
228         val |= U300_SYSCON_CCR_TURN_VCXO_ON;
229         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
230         val |= U300_SYSCON_CCR_I2S0_USE_VCXO;
231         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
232         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
233         val |= U300_SYSCON_CEFR_I2S0_CLK_EN;
234         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
235         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
236 }
237 
238 static void enable_i2s1_vcxo(void)
239 {
240         u16 val;
241         unsigned long iflags;
242 
243         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
244         /* Set I2S1 to use the VCXO 26 MHz clock */
245         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
246         val |= U300_SYSCON_CCR_TURN_VCXO_ON;
247         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
248         val |= U300_SYSCON_CCR_I2S1_USE_VCXO;
249         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
250         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
251         val |= U300_SYSCON_CEFR_I2S1_CLK_EN;
252         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
253         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
254 }
255 
256 static void disable_i2s0_vcxo(void)
257 {
258         u16 val;
259         unsigned long iflags;
260 
261         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
262         /* Disable I2S0 use of the VCXO 26 MHz clock */
263         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
264         val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO;
265         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
266         /* Deactivate VCXO if no one else is using VCXO */
267         if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO))
268                 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
269         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
270         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
271         val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
272         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
273         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
274 }
275 
276 static void disable_i2s1_vcxo(void)
277 {
278         u16 val;
279         unsigned long iflags;
280 
281         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
282         /* Disable I2S1 use of the VCXO 26 MHz clock */
283         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
284         val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO;
285         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
286         /* Deactivate VCXO if no one else is using VCXO */
287         if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO))
288                 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
289         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
290         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
291         val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
292         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
293         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
294 }
295 #endif /* CONFIG_MACH_U300_USE_I2S_AS_MASTER */
296 
297 
298 static void syscon_clk_rate_set_mclk(unsigned long rate)
299 {
300         u16 val;
301         u32 reg;
302         unsigned long iflags;
303 
304         switch (rate) {
305         case 18900000:
306                 val = 0x0054;
307                 break;
308         case 20800000:
309                 val = 0x0044;
310                 break;
311         case 23100000:
312                 val = 0x0043;
313                 break;
314         case 26000000:
315                 val = 0x0033;
316                 break;
317         case 29700000:
318                 val = 0x0032;
319                 break;
320         case 34700000:
321                 val = 0x0022;
322                 break;
323         case 41600000:
324                 val = 0x0021;
325                 break;
326         case 52000000:
327                 val = 0x0011;
328                 break;
329         case 104000000:
330                 val = 0x0000;
331                 break;
332         default:
333                 printk(KERN_ERR "Trying to set MCLK to unknown speed! %ld\n",
334                        rate);
335                 return;
336         }
337 
338         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
339         reg = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
340                 ~U300_SYSCON_MMF0R_MASK;
341         writew(reg | val, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
342         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
343 }
344 
345 void syscon_clk_rate_set_cpuclk(unsigned long rate)
346 {
347         u16 val;
348         unsigned long iflags;
349 
350         switch (rate) {
351         case 13000000:
352                 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
353                 break;
354         case 52000000:
355                 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
356                 break;
357         case 104000000:
358                 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
359                 break;
360         case 208000000:
361                 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
362                 break;
363         default:
364                 return;
365         }
366         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
367         val |= readw(U300_SYSCON_VBASE + U300_SYSCON_CCR) &
368                 ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
369         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
370         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
371 }
372 EXPORT_SYMBOL(syscon_clk_rate_set_cpuclk);
373 
374 void clk_disable(struct clk *clk)
375 {
376         unsigned long iflags;
377 
378         spin_lock_irqsave(&clk->lock, iflags);
379         if (clk->usecount > 0 && !(--clk->usecount)) {
380                 /* some blocks lack clocking registers and cannot be disabled */
381                 if (clk->disable)
382                         clk->disable(clk);
383                 if (likely((u32)clk->parent))
384                         clk_disable(clk->parent);
385         }
386 #ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
387         if (unlikely(!strcmp(clk->name, "I2S0")))
388                 disable_i2s0_vcxo();
389         if (unlikely(!strcmp(clk->name, "I2S1")))
390                 disable_i2s1_vcxo();
391 #endif
392         spin_unlock_irqrestore(&clk->lock, iflags);
393 }
394 EXPORT_SYMBOL(clk_disable);
395 
396 int clk_enable(struct clk *clk)
397 {
398         int ret = 0;
399         unsigned long iflags;
400 
401         spin_lock_irqsave(&clk->lock, iflags);
402         if (clk->usecount++ == 0) {
403                 if (likely((u32)clk->parent))
404                         ret = clk_enable(clk->parent);
405 
406                 if (unlikely(ret != 0))
407                         clk->usecount--;
408                 else {
409                         /* remove reset line (we never enable reset again) */
410                         syscon_block_reset_disable(clk);
411                         /* clocks without enable function are always on */
412                         if (clk->enable)
413                                 clk->enable(clk);
414 #ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
415                         if (unlikely(!strcmp(clk->name, "I2S0")))
416                                 enable_i2s0_vcxo();
417                         if (unlikely(!strcmp(clk->name, "I2S1")))
418                                 enable_i2s1_vcxo();
419 #endif
420                 }
421         }
422         spin_unlock_irqrestore(&clk->lock, iflags);
423         return ret;
424 
425 }
426 EXPORT_SYMBOL(clk_enable);
427 
428 /* Returns the clock rate in Hz */
429 static unsigned long clk_get_rate_cpuclk(struct clk *clk)
430 {
431         u16 val;
432 
433         val = syscon_clk_get_rate();
434 
435         switch (val) {
436         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
437         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
438                 return 13000000;
439         case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
440                 return 52000000;
441         case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
442                 return 104000000;
443         case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
444                 return 208000000;
445         default:
446                 break;
447         }
448         return clk->rate;
449 }
450 
451 static unsigned long clk_get_rate_ahb_clk(struct clk *clk)
452 {
453         u16 val;
454 
455         val = syscon_clk_get_rate();
456 
457         switch (val) {
458         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
459         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
460                 return 6500000;
461         case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
462                 return 26000000;
463         case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
464         case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
465                 return 52000000;
466         default:
467                 break;
468         }
469         return clk->rate;
470 
471 }
472 
473 static unsigned long clk_get_rate_emif_clk(struct clk *clk)
474 {
475         u16 val;
476 
477         val = syscon_clk_get_rate();
478 
479         switch (val) {
480         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
481         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
482                 return 13000000;
483         case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
484                 return 52000000;
485         case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
486         case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
487                 return 104000000;
488         default:
489                 break;
490         }
491         return clk->rate;
492 
493 }
494 
495 static unsigned long clk_get_rate_xgamclk(struct clk *clk)
496 {
497         u16 val;
498 
499         val = syscon_clk_get_rate();
500 
501         switch (val) {
502         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
503         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
504                 return 6500000;
505         case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
506                 return 26000000;
507         case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
508         case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
509                 return 52000000;
510         default:
511                 break;
512         }
513 
514         return clk->rate;
515 }
516 
517 static unsigned long clk_get_rate_mclk(struct clk *clk)
518 {
519         u16 val;
520 
521         val = syscon_clk_get_rate();
522 
523         switch (val) {
524         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
525                 /*
526                  * Here, the 208 MHz PLL gets shut down and the always
527                  * on 13 MHz PLL used for RTC etc kicks into use
528                  * instead.
529                  */
530                 return 13000000;
531         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
532         case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
533         case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
534         case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
535         {
536                 /*
537                  * This clock is under program control. The register is
538                  * divided in two nybbles, bit 7-4 gives cycles-1 to count
539                  * high, bit 3-0 gives cycles-1 to count low. Distribute
540                  * these with no more than 1 cycle difference between
541                  * low and high and add low and high to get the actual
542                  * divisor. The base PLL is 208 MHz. Writing 0x00 will
543                  * divide by 1 and 1 so the highest frequency possible
544                  * is 104 MHz.
545                  *
546                  * e.g. 0x54 =>
547                  * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
548                  */
549                 u16 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
550                         U300_SYSCON_MMF0R_MASK;
551                 switch (val) {
552                 case 0x0054:
553                         return 18900000;
554                 case 0x0044:
555                         return 20800000;
556                 case 0x0043:
557                         return 23100000;
558                 case 0x0033:
559                         return 26000000;
560                 case 0x0032:
561                         return 29700000;
562                 case 0x0022:
563                         return 34700000;
564                 case 0x0021:
565                         return 41600000;
566                 case 0x0011:
567                         return 52000000;
568                 case 0x0000:
569                         return 104000000;
570                 default:
571                         break;
572                 }
573         }
574         default:
575                 break;
576         }
577 
578         return clk->rate;
579 }
580 
581 static unsigned long clk_get_rate_i2s_i2c_spi(struct clk *clk)
582 {
583         u16 val;
584 
585         val = syscon_clk_get_rate();
586 
587         switch (val) {
588         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
589         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
590                 return 13000000;
591         case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
592         case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
593         case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
594                 return 26000000;
595         default:
596                 break;
597         }
598 
599         return clk->rate;
600 }
601 
602 unsigned long clk_get_rate(struct clk *clk)
603 {
604         if (clk->get_rate)
605                 return clk->get_rate(clk);
606         else
607                 return clk->rate;
608 }
609 EXPORT_SYMBOL(clk_get_rate);
610 
611 static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate)
612 {
613         if (rate <= 18900000)
614                 return 18900000;
615         if (rate <= 20800000)
616                 return 20800000;
617         if (rate <= 23100000)
618                 return 23100000;
619         if (rate <= 26000000)
620                 return 26000000;
621         if (rate <= 29700000)
622                 return 29700000;
623         if (rate <= 34700000)
624                 return 34700000;
625         if (rate <= 41600000)
626                 return 41600000;
627         if (rate <= 52000000)
628                 return 52000000;
629         return -EINVAL;
630 }
631 
632 static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
633 {
634         if (rate <= 13000000)
635                 return 13000000;
636         if (rate <= 52000000)
637                 return 52000000;
638         if (rate <= 104000000)
639                 return 104000000;
640         if (rate <= 208000000)
641                 return 208000000;
642         return -EINVAL;
643 }
644 
645 /*
646  * This adjusts a requested rate to the closest exact rate
647  * a certain clock can provide. For a fixed clock it's
648  * mostly clk->rate.
649  */
650 long clk_round_rate(struct clk *clk, unsigned long rate)
651 {
652         /* TODO: get appropriate switches for EMIFCLK, AHBCLK and MCLK */
653         /* Else default to fixed value */
654 
655         if (clk->round_rate) {
656                 return (long) clk->round_rate(clk, rate);
657         } else {
658                 printk(KERN_ERR "clock: Failed to round rate of %s\n",
659                        clk->name);
660         }
661         return (long) clk->rate;
662 }
663 EXPORT_SYMBOL(clk_round_rate);
664 
665 static int clk_set_rate_mclk(struct clk *clk, unsigned long rate)
666 {
667         syscon_clk_rate_set_mclk(clk_round_rate(clk, rate));
668         return 0;
669 }
670 
671 static int clk_set_rate_cpuclk(struct clk *clk, unsigned long rate)
672 {
673         syscon_clk_rate_set_cpuclk(clk_round_rate(clk, rate));
674         return 0;
675 }
676 
677 int clk_set_rate(struct clk *clk, unsigned long rate)
678 {
679         /* TODO: set for EMIFCLK and AHBCLK */
680         /* Else assume the clock is fixed and fail */
681         if (clk->set_rate) {
682                 return clk->set_rate(clk, rate);
683         } else {
684                 printk(KERN_ERR "clock: Failed to set %s to %ld hz\n",
685                        clk->name, rate);
686                 return -EINVAL;
687         }
688 }
689 EXPORT_SYMBOL(clk_set_rate);
690 
691 /*
692  * Clock definitions. The clock parents are set to respective
693  * bridge and the clock framework makes sure that the clocks have
694  * parents activated and are brought out of reset when in use.
695  *
696  * Clocks that have hw_ctrld = true are hw controlled, and the hw
697  * can by itself turn these clocks on and off.
698  * So in other words, we don't really have to care about them.
699  */
700 
701 static struct clk amba_clk = {
702         .name       = "AMBA",
703         .rate       = 52000000, /* this varies! */
704         .hw_ctrld   = true,
705         .reset      = false,
706         .lock       = __SPIN_LOCK_UNLOCKED(amba_clk.lock),
707 };
708 
709 /*
710  * These blocks are connected directly to the AMBA bus
711  * with no bridge.
712  */
713 
714 static struct clk cpu_clk = {
715         .name       = "CPU",
716         .parent     = &amba_clk,
717         .rate       = 208000000, /* this varies! */
718         .hw_ctrld   = true,
719         .reset      = true,
720         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
721         .res_mask   = U300_SYSCON_RRR_CPU_RESET_EN,
722         .set_rate   = clk_set_rate_cpuclk,
723         .get_rate   = clk_get_rate_cpuclk,
724         .round_rate = clk_round_rate_cpuclk,
725         .lock       = __SPIN_LOCK_UNLOCKED(cpu_clk.lock),
726 };
727 
728 static struct clk nandif_clk = {
729         .name       = "FSMC",
730         .parent     = &amba_clk,
731         .hw_ctrld   = false,
732         .reset      = true,
733         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
734         .res_mask   = U300_SYSCON_RRR_NANDIF_RESET_EN,
735         .clk_val    = U300_SYSCON_SBCER_NANDIF_CLK_EN,
736         .enable     = syscon_clk_enable,
737         .disable    = syscon_clk_disable,
738         .lock       = __SPIN_LOCK_UNLOCKED(nandif_clk.lock),
739 };
740 
741 static struct clk semi_clk = {
742         .name       = "SEMI",
743         .parent     = &amba_clk,
744         .rate       = 0, /* FIXME */
745         /* It is not possible to reset SEMI */
746         .hw_ctrld   = false,
747         .reset      = false,
748         .clk_val    = U300_SYSCON_SBCER_SEMI_CLK_EN,
749         .enable     = syscon_clk_enable,
750         .disable    = syscon_clk_disable,
751         .lock       = __SPIN_LOCK_UNLOCKED(semi_clk.lock),
752 };
753 
754 #ifdef CONFIG_MACH_U300_BS335
755 static struct clk isp_clk = {
756         .name       = "ISP",
757         .parent     = &amba_clk,
758         .rate       = 0, /* FIXME */
759         .hw_ctrld   = false,
760         .reset      = true,
761         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
762         .res_mask   = U300_SYSCON_RRR_ISP_RESET_EN,
763         .clk_val    = U300_SYSCON_SBCER_ISP_CLK_EN,
764         .enable     = syscon_clk_enable,
765         .disable    = syscon_clk_disable,
766         .lock       = __SPIN_LOCK_UNLOCKED(isp_clk.lock),
767 };
768 
769 static struct clk cds_clk = {
770         .name       = "CDS",
771         .parent     = &amba_clk,
772         .rate       = 0, /* FIXME */
773         .hw_ctrld   = false,
774         .reset      = true,
775         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
776         .res_mask   = U300_SYSCON_RRR_CDS_RESET_EN,
777         .clk_val    = U300_SYSCON_SBCER_CDS_CLK_EN,
778         .enable     = syscon_clk_enable,
779         .disable    = syscon_clk_disable,
780         .lock       = __SPIN_LOCK_UNLOCKED(cds_clk.lock),
781 };
782 #endif
783 
784 static struct clk dma_clk = {
785         .name       = "DMA",
786         .parent     = &amba_clk,
787         .rate       = 52000000, /* this varies! */
788         .hw_ctrld   = true,
789         .reset      = true,
790         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
791         .res_mask   = U300_SYSCON_RRR_DMAC_RESET_EN,
792         .clk_val    = U300_SYSCON_SBCER_DMAC_CLK_EN,
793         .enable     = syscon_clk_enable,
794         .disable    = syscon_clk_disable,
795         .lock       = __SPIN_LOCK_UNLOCKED(dma_clk.lock),
796 };
797 
798 static struct clk aaif_clk = {
799         .name       = "AAIF",
800         .parent     = &amba_clk,
801         .rate       = 52000000, /* this varies! */
802         .hw_ctrld   = true,
803         .reset      = true,
804         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
805         .res_mask   = U300_SYSCON_RRR_AAIF_RESET_EN,
806         .clk_val    = U300_SYSCON_SBCER_AAIF_CLK_EN,
807         .enable     = syscon_clk_enable,
808         .disable    = syscon_clk_disable,
809         .lock       = __SPIN_LOCK_UNLOCKED(aaif_clk.lock),
810 };
811 
812 static struct clk apex_clk = {
813         .name       = "APEX",
814         .parent     = &amba_clk,
815         .rate       = 0, /* FIXME */
816         .hw_ctrld   = true,
817         .reset      = true,
818         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
819         .res_mask   = U300_SYSCON_RRR_APEX_RESET_EN,
820         .clk_val    = U300_SYSCON_SBCER_APEX_CLK_EN,
821         .enable     = syscon_clk_enable,
822         .disable    = syscon_clk_disable,
823         .lock       = __SPIN_LOCK_UNLOCKED(apex_clk.lock),
824 };
825 
826 static struct clk video_enc_clk = {
827         .name       = "VIDEO_ENC",
828         .parent     = &amba_clk,
829         .rate       = 208000000, /* this varies! */
830         .hw_ctrld   = false,
831         .reset      = false,
832         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
833         /* This has XGAM in the name but refers to the video encoder */
834         .res_mask   = U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN,
835         .clk_val    = U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN,
836         .enable     = syscon_clk_enable,
837         .disable    = syscon_clk_disable,
838         .lock       = __SPIN_LOCK_UNLOCKED(video_enc_clk.lock),
839 };
840 
841 static struct clk xgam_clk = {
842         .name       = "XGAMCLK",
843         .parent     = &amba_clk,
844         .rate       = 52000000, /* this varies! */
845         .hw_ctrld   = false,
846         .reset      = true,
847         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
848         .res_mask   = U300_SYSCON_RRR_XGAM_RESET_EN,
849         .clk_val    = U300_SYSCON_SBCER_XGAM_CLK_EN,
850         .get_rate   = clk_get_rate_xgamclk,
851         .enable     = syscon_clk_enable,
852         .disable    = syscon_clk_disable,
853         .lock       = __SPIN_LOCK_UNLOCKED(xgam_clk.lock),
854 };
855 
856 /* This clock is used to activate the video encoder */
857 static struct clk ahb_clk = {
858         .name       = "AHB",
859         .parent     = &amba_clk,
860         .rate       = 52000000, /* this varies! */
861         .hw_ctrld   = false, /* This one is set to false due to HW bug */
862         .reset      = true,
863         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
864         .res_mask   = U300_SYSCON_RRR_AHB_RESET_EN,
865         .clk_val    = U300_SYSCON_SBCER_AHB_CLK_EN,
866         .enable     = syscon_clk_enable,
867         .disable    = syscon_clk_disable,
868         .get_rate   = clk_get_rate_ahb_clk,
869         .lock       = __SPIN_LOCK_UNLOCKED(ahb_clk.lock),
870 };
871 
872 
873 /*
874  * Clocks on the AHB bridge
875  */
876 
877 static struct clk ahb_subsys_clk = {
878         .name       = "AHB_SUBSYS",
879         .parent     = &amba_clk,
880         .rate       = 52000000, /* this varies! */
881         .hw_ctrld   = true,
882         .reset      = false,
883         .clk_val    = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
884         .enable     = syscon_clk_enable,
885         .disable    = syscon_clk_disable,
886         .get_rate   = clk_get_rate_ahb_clk,
887         .lock       = __SPIN_LOCK_UNLOCKED(ahb_subsys_clk.lock),
888 };
889 
890 static struct clk intcon_clk = {
891         .name       = "INTCON",
892         .parent     = &ahb_subsys_clk,
893         .rate       = 52000000, /* this varies! */
894         .hw_ctrld   = false,
895         .reset      = true,
896         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
897         .res_mask   = U300_SYSCON_RRR_INTCON_RESET_EN,
898         /* INTCON can be reset but not clock-gated */
899         .lock       = __SPIN_LOCK_UNLOCKED(intcon_clk.lock),
900 
901 };
902 
903 static struct clk mspro_clk = {
904         .name       = "MSPRO",
905         .parent     = &ahb_subsys_clk,
906         .rate       = 0, /* FIXME */
907         .hw_ctrld   = false,
908         .reset      = true,
909         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
910         .res_mask   = U300_SYSCON_RRR_MSPRO_RESET_EN,
911         .clk_val    = U300_SYSCON_SBCER_MSPRO_CLK_EN,
912         .enable     = syscon_clk_enable,
913         .disable    = syscon_clk_disable,
914         .lock       = __SPIN_LOCK_UNLOCKED(mspro_clk.lock),
915 };
916 
917 static struct clk emif_clk = {
918         .name       = "EMIF",
919         .parent     = &ahb_subsys_clk,
920         .rate       = 104000000, /* this varies! */
921         .hw_ctrld   = false,
922         .reset      = true,
923         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
924         .res_mask   = U300_SYSCON_RRR_EMIF_RESET_EN,
925         .clk_val    = U300_SYSCON_SBCER_EMIF_CLK_EN,
926         .enable     = syscon_clk_enable,
927         .disable    = syscon_clk_disable,
928         .get_rate   = clk_get_rate_emif_clk,
929         .lock       = __SPIN_LOCK_UNLOCKED(emif_clk.lock),
930 };
931 
932 
933 /*
934  * Clocks on the FAST bridge
935  */
936 static struct clk fast_clk = {
937         .name       = "FAST_BRIDGE",
938         .parent     = &amba_clk,
939         .rate       = 13000000, /* this varies! */
940         .hw_ctrld   = true,
941         .reset      = true,
942         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
943         .res_mask   = U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE,
944         .clk_val    = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
945         .enable     = syscon_clk_enable,
946         .disable    = syscon_clk_disable,
947         .lock       = __SPIN_LOCK_UNLOCKED(fast_clk.lock),
948 };
949 
950 /*
951  * The MMCI apb_pclk is hardwired to the same terminal as the
952  * external MCI clock. Thus this will be referenced twice.
953  */
954 static struct clk mmcsd_clk = {
955         .name       = "MCLK",
956         .parent     = &fast_clk,
957         .rate       = 18900000, /* this varies! */
958         .hw_ctrld   = false,
959         .reset      = true,
960         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
961         .res_mask   = U300_SYSCON_RFR_MMC_RESET_ENABLE,
962         .clk_val    = U300_SYSCON_SBCER_MMC_CLK_EN,
963         .get_rate   = clk_get_rate_mclk,
964         .set_rate   = clk_set_rate_mclk,
965         .round_rate = clk_round_rate_mclk,
966         .disable    = syscon_clk_disable,
967         .enable     = syscon_clk_enable,
968         .lock       = __SPIN_LOCK_UNLOCKED(mmcsd_clk.lock),
969 };
970 
971 static struct clk i2s0_clk = {
972         .name       = "i2s0",
973         .parent     = &fast_clk,
974         .rate       = 26000000, /* this varies! */
975         .hw_ctrld   = true,
976         .reset      = true,
977         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
978         .res_mask   = U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE,
979         .clk_val    = U300_SYSCON_SBCER_I2S0_CORE_CLK_EN,
980         .enable     = syscon_clk_enable,
981         .disable    = syscon_clk_disable,
982         .get_rate   = clk_get_rate_i2s_i2c_spi,
983         .lock       = __SPIN_LOCK_UNLOCKED(i2s0_clk.lock),
984 };
985 
986 static struct clk i2s1_clk = {
987         .name       = "i2s1",
988         .parent     = &fast_clk,
989         .rate       = 26000000, /* this varies! */
990         .hw_ctrld   = true,
991         .reset      = true,
992         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
993         .res_mask   = U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE,
994         .clk_val    = U300_SYSCON_SBCER_I2S1_CORE_CLK_EN,
995         .enable     = syscon_clk_enable,
996         .disable    = syscon_clk_disable,
997         .get_rate   = clk_get_rate_i2s_i2c_spi,
998         .lock       = __SPIN_LOCK_UNLOCKED(i2s1_clk.lock),
999 };
1000 
1001 static struct clk i2c0_clk = {
1002         .name       = "I2C0",
1003         .parent     = &fast_clk,
1004         .rate       = 26000000, /* this varies! */
1005         .hw_ctrld   = false,
1006         .reset      = true,
1007         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1008         .res_mask   = U300_SYSCON_RFR_I2C0_RESET_ENABLE,
1009         .clk_val    = U300_SYSCON_SBCER_I2C0_CLK_EN,
1010         .enable     = syscon_clk_enable,
1011         .disable    = syscon_clk_disable,
1012         .get_rate   = clk_get_rate_i2s_i2c_spi,
1013         .lock       = __SPIN_LOCK_UNLOCKED(i2c0_clk.lock),
1014 };
1015 
1016 static struct clk i2c1_clk = {
1017         .name       = "I2C1",
1018         .parent     = &fast_clk,
1019         .rate       = 26000000, /* this varies! */
1020         .hw_ctrld   = false,
1021         .reset      = true,
1022         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1023         .res_mask   = U300_SYSCON_RFR_I2C1_RESET_ENABLE,
1024         .clk_val    = U300_SYSCON_SBCER_I2C1_CLK_EN,
1025         .enable     = syscon_clk_enable,
1026         .disable    = syscon_clk_disable,
1027         .get_rate   = clk_get_rate_i2s_i2c_spi,
1028         .lock       = __SPIN_LOCK_UNLOCKED(i2c1_clk.lock),
1029 };
1030 
1031 /*
1032  * The SPI apb_pclk is hardwired to the same terminal as the
1033  * external SPI clock. Thus this will be referenced twice.
1034  */
1035 static struct clk spi_clk = {
1036         .name       = "SPI",
1037         .parent     = &fast_clk,
1038         .rate       = 26000000, /* this varies! */
1039         .hw_ctrld   = false,
1040         .reset      = true,
1041         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1042         .res_mask   = U300_SYSCON_RFR_SPI_RESET_ENABLE,
1043         .clk_val    = U300_SYSCON_SBCER_SPI_CLK_EN,
1044         .enable     = syscon_clk_enable,
1045         .disable    = syscon_clk_disable,
1046         .get_rate   = clk_get_rate_i2s_i2c_spi,
1047         .lock       = __SPIN_LOCK_UNLOCKED(spi_clk.lock),
1048 };
1049 
1050 #ifdef CONFIG_MACH_U300_BS335
1051 static struct clk uart1_pclk = {
1052         .name       = "UART1_PCLK",
1053         .parent     = &fast_clk,
1054         .hw_ctrld   = false,
1055         .reset      = true,
1056         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1057         .res_mask   = U300_SYSCON_RFR_UART1_RESET_ENABLE,
1058         .clk_val    = U300_SYSCON_SBCER_UART1_CLK_EN,
1059         .enable     = syscon_clk_enable,
1060         .disable    = syscon_clk_disable,
1061         .lock       = __SPIN_LOCK_UNLOCKED(uart1_pclk.lock),
1062 };
1063 
1064 /* This one is hardwired to PLL13 */
1065 static struct clk uart1_clk = {
1066         .name       = "UART1_CLK",
1067         .rate       = 13000000,
1068         .hw_ctrld   = true,
1069         .lock       = __SPIN_LOCK_UNLOCKED(uart1_clk.lock),
1070 };
1071 #endif
1072 
1073 
1074 /*
1075  * Clocks on the SLOW bridge
1076  */
1077 static struct clk slow_clk = {
1078         .name       = "SLOW_BRIDGE",
1079         .parent     = &amba_clk,
1080         .rate       = 13000000,
1081         .hw_ctrld   = true,
1082         .reset      = true,
1083         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1084         .res_mask   = U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN,
1085         .clk_val    = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
1086         .enable     = syscon_clk_enable,
1087         .disable    = syscon_clk_disable,
1088         .lock       = __SPIN_LOCK_UNLOCKED(slow_clk.lock),
1089 };
1090 
1091 /* TODO: implement SYSCON clock? */
1092 
1093 static struct clk wdog_clk = {
1094         .name       = "WDOG",
1095         .parent     = &slow_clk,
1096         .hw_ctrld   = false,
1097         .rate       = 32768,
1098         .reset      = false,
1099         /* This is always on, cannot be enabled/disabled or reset */
1100         .lock       = __SPIN_LOCK_UNLOCKED(wdog_clk.lock),
1101 };
1102 
1103 static struct clk uart0_pclk = {
1104         .name       = "UART0_PCLK",
1105         .parent     = &slow_clk,
1106         .hw_ctrld   = false,
1107         .reset      = true,
1108         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1109         .res_mask   = U300_SYSCON_RSR_UART_RESET_EN,
1110         .clk_val    = U300_SYSCON_SBCER_UART_CLK_EN,
1111         .enable     = syscon_clk_enable,
1112         .disable    = syscon_clk_disable,
1113         .lock       = __SPIN_LOCK_UNLOCKED(uart0_pclk.lock),
1114 };
1115 
1116 /* This one is hardwired to PLL13 */
1117 static struct clk uart0_clk = {
1118         .name       = "UART0_CLK",
1119         .parent     = &slow_clk,
1120         .rate       = 13000000,
1121         .hw_ctrld   = true,
1122         .lock       = __SPIN_LOCK_UNLOCKED(uart0_clk.lock),
1123 };
1124 
1125 static struct clk keypad_clk = {
1126         .name       = "KEYPAD",
1127         .parent     = &slow_clk,
1128         .rate       = 32768,
1129         .hw_ctrld   = false,
1130         .reset      = true,
1131         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1132         .res_mask   = U300_SYSCON_RSR_KEYPAD_RESET_EN,
1133         .clk_val    = U300_SYSCON_SBCER_KEYPAD_CLK_EN,
1134         .enable     = syscon_clk_enable,
1135         .disable    = syscon_clk_disable,
1136         .lock       = __SPIN_LOCK_UNLOCKED(keypad_clk.lock),
1137 };
1138 
1139 static struct clk gpio_clk = {
1140         .name       = "GPIO",
1141         .parent     = &slow_clk,
1142         .rate       = 13000000,
1143         .hw_ctrld   = true,
1144         .reset      = true,
1145         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1146         .res_mask   = U300_SYSCON_RSR_GPIO_RESET_EN,
1147         .clk_val    = U300_SYSCON_SBCER_GPIO_CLK_EN,
1148         .enable     = syscon_clk_enable,
1149         .disable    = syscon_clk_disable,
1150         .lock       = __SPIN_LOCK_UNLOCKED(gpio_clk.lock),
1151 };
1152 
1153 static struct clk rtc_clk = {
1154         .name       = "RTC",
1155         .parent     = &slow_clk,
1156         .rate       = 32768,
1157         .hw_ctrld   = true,
1158         .reset      = true,
1159         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1160         .res_mask   = U300_SYSCON_RSR_RTC_RESET_EN,
1161         /* This clock is always on, cannot be enabled/disabled */
1162         .lock       = __SPIN_LOCK_UNLOCKED(rtc_clk.lock),
1163 };
1164 
1165 static struct clk bustr_clk = {
1166         .name       = "BUSTR",
1167         .parent     = &slow_clk,
1168         .rate       = 13000000,
1169         .hw_ctrld   = true,
1170         .reset      = true,
1171         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1172         .res_mask   = U300_SYSCON_RSR_BTR_RESET_EN,
1173         .clk_val    = U300_SYSCON_SBCER_BTR_CLK_EN,
1174         .enable     = syscon_clk_enable,
1175         .disable    = syscon_clk_disable,
1176         .lock       = __SPIN_LOCK_UNLOCKED(bustr_clk.lock),
1177 };
1178 
1179 static struct clk evhist_clk = {
1180         .name       = "EVHIST",
1181         .parent     = &slow_clk,
1182         .rate       = 13000000,
1183         .hw_ctrld   = true,
1184         .reset      = true,
1185         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1186         .res_mask   = U300_SYSCON_RSR_EH_RESET_EN,
1187         .clk_val    = U300_SYSCON_SBCER_EH_CLK_EN,
1188         .enable     = syscon_clk_enable,
1189         .disable    = syscon_clk_disable,
1190         .lock       = __SPIN_LOCK_UNLOCKED(evhist_clk.lock),
1191 };
1192 
1193 static struct clk timer_clk = {
1194         .name       = "TIMER",
1195         .parent     = &slow_clk,
1196         .rate       = 13000000,
1197         .hw_ctrld   = true,
1198         .reset      = true,
1199         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1200         .res_mask   = U300_SYSCON_RSR_ACC_TMR_RESET_EN,
1201         .clk_val    = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
1202         .enable     = syscon_clk_enable,
1203         .disable    = syscon_clk_disable,
1204         .lock       = __SPIN_LOCK_UNLOCKED(timer_clk.lock),
1205 };
1206 
1207 /*
1208  * There is a binary divider in the hardware that divides
1209  * the 13MHz PLL by 13 down to 1 MHz.
1210  */
1211 static struct clk app_timer_clk = {
1212         .name       = "TIMER_APP",
1213         .parent     = &slow_clk,
1214         .rate       = 1000000,
1215         .hw_ctrld   = true,
1216         .reset      = true,
1217         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1218         .res_mask   = U300_SYSCON_RSR_APP_TMR_RESET_EN,
1219         .clk_val    = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
1220         .enable     = syscon_clk_enable,
1221         .disable    = syscon_clk_disable,
1222         .lock       = __SPIN_LOCK_UNLOCKED(app_timer_clk.lock),
1223 };
1224 
1225 #ifdef CONFIG_MACH_U300_BS335
1226 static struct clk ppm_clk = {
1227         .name       = "PPM",
1228         .parent     = &slow_clk,
1229         .rate       = 0, /* FIXME */
1230         .hw_ctrld   = true, /* TODO: Look up if it is hw ctrld or not */
1231         .reset      = true,
1232         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1233         .res_mask   = U300_SYSCON_RSR_PPM_RESET_EN,
1234         .clk_val    = U300_SYSCON_SBCER_PPM_CLK_EN,
1235         .enable     = syscon_clk_enable,
1236         .disable    = syscon_clk_disable,
1237         .lock       = __SPIN_LOCK_UNLOCKED(ppm_clk.lock),
1238 };
1239 #endif
1240 
1241 #define DEF_LOOKUP(devid, clkref)               \
1242         {                                       \
1243         .dev_id = devid,                        \
1244         .clk = clkref,                          \
1245         }
1246 
1247 #define DEF_LOOKUP_CON(devid, conid, clkref)    \
1248         {                                       \
1249         .dev_id = devid,                        \
1250         .con_id = conid,                        \
1251         .clk = clkref,                          \
1252         }
1253 
1254 /*
1255  * Here we only define clocks that are meaningful to
1256  * look up through clockdevice.
1257  */
1258 static struct clk_lookup lookups[] = {
1259         /* Connected directly to the AMBA bus */
1260         DEF_LOOKUP("amba",      &amba_clk),
1261         DEF_LOOKUP("cpu",       &cpu_clk),
1262         DEF_LOOKUP("fsmc-nand", &nandif_clk),
1263         DEF_LOOKUP("semi",      &semi_clk),
1264 #ifdef CONFIG_MACH_U300_BS335
1265         DEF_LOOKUP("isp",       &isp_clk),
1266         DEF_LOOKUP("cds",       &cds_clk),
1267 #endif
1268         DEF_LOOKUP("dma",       &dma_clk),
1269         DEF_LOOKUP("msl",       &aaif_clk),
1270         DEF_LOOKUP("apex",      &apex_clk),
1271         DEF_LOOKUP("video_enc", &video_enc_clk),
1272         DEF_LOOKUP("xgam",      &xgam_clk),
1273         DEF_LOOKUP("ahb",       &ahb_clk),
1274         /* AHB bridge clocks */
1275         DEF_LOOKUP("ahb_subsys", &ahb_subsys_clk),
1276         DEF_LOOKUP("intcon",    &intcon_clk),
1277         DEF_LOOKUP_CON("intcon", "apb_pclk", &intcon_clk),
1278         DEF_LOOKUP("mspro",     &mspro_clk),
1279         DEF_LOOKUP("pl172",     &emif_clk),
1280         DEF_LOOKUP_CON("pl172", "apb_pclk", &emif_clk),
1281         /* FAST bridge clocks */
1282         DEF_LOOKUP("fast",      &fast_clk),
1283         DEF_LOOKUP("mmci",      &mmcsd_clk),
1284         DEF_LOOKUP_CON("mmci", "apb_pclk", &mmcsd_clk),
1285         /*
1286          * The .0 and .1 identifiers on these comes from the platform device
1287          * .id field and are assigned when the platform devices are registered.
1288          */
1289         DEF_LOOKUP("i2s.0",     &i2s0_clk),
1290         DEF_LOOKUP("i2s.1",     &i2s1_clk),
1291         DEF_LOOKUP("stu300.0",  &i2c0_clk),
1292         DEF_LOOKUP("stu300.1",  &i2c1_clk),
1293         DEF_LOOKUP("pl022",     &spi_clk),
1294         DEF_LOOKUP_CON("pl022", "apb_pclk", &spi_clk),
1295 #ifdef CONFIG_MACH_U300_BS335
1296         DEF_LOOKUP("uart1",     &uart1_clk),
1297         DEF_LOOKUP_CON("uart1", "apb_pclk", &uart1_pclk),
1298 #endif
1299         /* SLOW bridge clocks */
1300         DEF_LOOKUP("slow",      &slow_clk),
1301         DEF_LOOKUP("coh901327_wdog",      &wdog_clk),
1302         DEF_LOOKUP("uart0",     &uart0_clk),
1303         DEF_LOOKUP_CON("uart0", "apb_pclk", &uart0_pclk),
1304         DEF_LOOKUP("apptimer",  &app_timer_clk),
1305         DEF_LOOKUP("coh901461-keypad",    &keypad_clk),
1306         DEF_LOOKUP("u300-gpio", &gpio_clk),
1307         DEF_LOOKUP("rtc-coh901331",      &rtc_clk),
1308         DEF_LOOKUP("bustr",     &bustr_clk),
1309         DEF_LOOKUP("evhist",    &evhist_clk),
1310         DEF_LOOKUP("timer",     &timer_clk),
1311 #ifdef CONFIG_MACH_U300_BS335
1312         DEF_LOOKUP("ppm",       &ppm_clk),
1313 #endif
1314 };
1315 
1316 static void __init clk_register(void)
1317 {
1318         /* Register the lookups */
1319         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
1320 }
1321 
1322 #if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
1323 /*
1324  * The following makes it possible to view the status (especially
1325  * reference count and reset status) for the clocks in the platform
1326  * by looking into the special file <debugfs>/u300_clocks
1327  */
1328 
1329 /* A list of all clocks in the platform */
1330 static struct clk *clks[] = {
1331         /* Top node clock for the AMBA bus */
1332         &amba_clk,
1333         /* Connected directly to the AMBA bus */
1334         &cpu_clk,
1335         &nandif_clk,
1336         &semi_clk,
1337 #ifdef CONFIG_MACH_U300_BS335
1338         &isp_clk,
1339         &cds_clk,
1340 #endif
1341         &dma_clk,
1342         &aaif_clk,
1343         &apex_clk,
1344         &video_enc_clk,
1345         &xgam_clk,
1346         &ahb_clk,
1347 
1348         /* AHB bridge clocks */
1349         &ahb_subsys_clk,
1350         &intcon_clk,
1351         &mspro_clk,
1352         &emif_clk,
1353         /* FAST bridge clocks */
1354         &fast_clk,
1355         &mmcsd_clk,
1356         &i2s0_clk,
1357         &i2s1_clk,
1358         &i2c0_clk,
1359         &i2c1_clk,
1360         &spi_clk,
1361 #ifdef CONFIG_MACH_U300_BS335
1362         &uart1_clk,
1363         &uart1_pclk,
1364 #endif
1365         /* SLOW bridge clocks */
1366         &slow_clk,
1367         &wdog_clk,
1368         &uart0_clk,
1369         &uart0_pclk,
1370         &app_timer_clk,
1371         &keypad_clk,
1372         &gpio_clk,
1373         &rtc_clk,
1374         &bustr_clk,
1375         &evhist_clk,
1376         &timer_clk,
1377 #ifdef CONFIG_MACH_U300_BS335
1378         &ppm_clk,
1379 #endif
1380 };
1381 
1382 static int u300_clocks_show(struct seq_file *s, void *data)
1383 {
1384         struct clk *clk;
1385         int i;
1386 
1387         seq_printf(s, "CLOCK           DEVICE          RESET STATE\t" \
1388                    "ACTIVE\tUSERS\tHW CTRL FREQ\n");
1389         seq_printf(s, "---------------------------------------------" \
1390                    "-----------------------------------------\n");
1391         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1392                 clk = clks[i];
1393                 if (clk != ERR_PTR(-ENOENT)) {
1394                         /* Format clock and device name nicely */
1395                         char cdp[33];
1396                         int chars;
1397 
1398                         chars = snprintf(&cdp[0], 17, "%s", clk->name);
1399                         while (chars < 16) {
1400                                 cdp[chars] = ' ';
1401                                 chars++;
1402                         }
1403                         chars = snprintf(&cdp[16], 17, "%s", clk->dev ?
1404                                          dev_name(clk->dev) : "N/A");
1405                         while (chars < 16) {
1406                                 cdp[chars+16] = ' ';
1407                                 chars++;
1408                         }
1409                         cdp[32] = '\0';
1410                         if (clk->get_rate || clk->rate != 0)
1411                                 seq_printf(s,
1412                                            "%s%s\t%s\t%d\t%s\t%lu Hz\n",
1413                                            &cdp[0],
1414                                            clk->reset ?
1415                                            "ASSERTED" : "RELEASED",
1416                                            clk->usecount ? "ON" : "OFF",
1417                                            clk->usecount,
1418                                            clk->hw_ctrld  ? "YES" : "NO ",
1419                                            clk_get_rate(clk));
1420                         else
1421                                 seq_printf(s,
1422                                            "%s%s\t%s\t%d\t%s\t" \
1423                                            "(unknown rate)\n",
1424                                            &cdp[0],
1425                                            clk->reset ?
1426                                            "ASSERTED" : "RELEASED",
1427                                            clk->usecount ? "ON" : "OFF",
1428                                            clk->usecount,
1429                                            clk->hw_ctrld  ? "YES" : "NO ");
1430                 }
1431         }
1432         return 0;
1433 }
1434 
1435 static int u300_clocks_open(struct inode *inode, struct file *file)
1436 {
1437         return single_open(file, u300_clocks_show, NULL);
1438 }
1439 
1440 static const struct file_operations u300_clocks_operations = {
1441         .open           = u300_clocks_open,
1442         .read           = seq_read,
1443         .llseek         = seq_lseek,
1444         .release        = single_release,
1445 };
1446 
1447 static int __init init_clk_read_debugfs(void)
1448 {
1449         /* Expose a simple debugfs interface to view all clocks */
1450         (void) debugfs_create_file("u300_clocks", S_IFREG | S_IRUGO,
1451                                    NULL, NULL,
1452                                    &u300_clocks_operations);
1453         return 0;
1454 }
1455 /*
1456  * This needs to come in after the core_initcall() for the
1457  * overall clocks, because debugfs is not available until
1458  * the subsystems come up.
1459  */
1460 module_init(init_clk_read_debugfs);
1461 #endif
1462 
1463 int __init u300_clock_init(void)
1464 {
1465         u16 val;
1466 
1467         /*
1468          * FIXME: shall all this powermanagement stuff really live here???
1469          */
1470 
1471         /* Set system to run at PLL208, max performance, a known state. */
1472         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1473         val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1474         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1475         /* Wait for the PLL208 to lock if not locked in yet */
1476         while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1477                  U300_SYSCON_CSR_PLL208_LOCK_IND));
1478 
1479         /* Power management enable */
1480         val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
1481         val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
1482         writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
1483 
1484         clk_register();
1485 
1486         /*
1487          * Some of these may be on when we boot the system so make sure they
1488          * are turned OFF.
1489          */
1490         syscon_block_reset_enable(&timer_clk);
1491         timer_clk.disable(&timer_clk);
1492 
1493         /*
1494          * These shall be turned on by default when we boot the system
1495          * so make sure they are ON. (Adding CPU here is a bit too much.)
1496          * These clocks will be claimed by drivers later.
1497          */
1498         syscon_block_reset_disable(&semi_clk);
1499         syscon_block_reset_disable(&emif_clk);
1500         clk_enable(&semi_clk);
1501         clk_enable(&emif_clk);
1502 
1503         return 0;
1504 }
1505 

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