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Linux/arch/arm/mach-ux500/platsmp.c

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  1 /*
  2  * Copyright (C) 2002 ARM Ltd.
  3  * Copyright (C) 2008 STMicroelctronics.
  4  * Copyright (C) 2009 ST-Ericsson.
  5  * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
  6  *
  7  * This file is based on arm realview platform
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 #include <linux/init.h>
 14 #include <linux/errno.h>
 15 #include <linux/delay.h>
 16 #include <linux/device.h>
 17 #include <linux/smp.h>
 18 #include <linux/io.h>
 19 
 20 #include <asm/cacheflush.h>
 21 #include <asm/smp_plat.h>
 22 #include <asm/smp_scu.h>
 23 
 24 #include "setup.h"
 25 
 26 #include "db8500-regs.h"
 27 #include "id.h"
 28 
 29 /* This is called from headsmp.S to wakeup the secondary core */
 30 extern void u8500_secondary_startup(void);
 31 
 32 /*
 33  * Write pen_release in a way that is guaranteed to be visible to all
 34  * observers, irrespective of whether they're taking part in coherency
 35  * or not.  This is necessary for the hotplug code to work reliably.
 36  */
 37 static void write_pen_release(int val)
 38 {
 39         pen_release = val;
 40         smp_wmb();
 41         __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
 42         outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
 43 }
 44 
 45 static void __iomem *scu_base_addr(void)
 46 {
 47         if (cpu_is_u8500_family() || cpu_is_ux540_family())
 48                 return __io_address(U8500_SCU_BASE);
 49         else
 50                 ux500_unknown_soc();
 51 
 52         return NULL;
 53 }
 54 
 55 static DEFINE_SPINLOCK(boot_lock);
 56 
 57 static void ux500_secondary_init(unsigned int cpu)
 58 {
 59         /*
 60          * let the primary processor know we're out of the
 61          * pen, then head off into the C entry point
 62          */
 63         write_pen_release(-1);
 64 
 65         /*
 66          * Synchronise with the boot thread.
 67          */
 68         spin_lock(&boot_lock);
 69         spin_unlock(&boot_lock);
 70 }
 71 
 72 static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
 73 {
 74         unsigned long timeout;
 75 
 76         /*
 77          * set synchronisation state between this boot processor
 78          * and the secondary one
 79          */
 80         spin_lock(&boot_lock);
 81 
 82         /*
 83          * The secondary processor is waiting to be released from
 84          * the holding pen - release it, then wait for it to flag
 85          * that it has been released by resetting pen_release.
 86          */
 87         write_pen_release(cpu_logical_map(cpu));
 88 
 89         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 90 
 91         timeout = jiffies + (1 * HZ);
 92         while (time_before(jiffies, timeout)) {
 93                 if (pen_release == -1)
 94                         break;
 95         }
 96 
 97         /*
 98          * now the secondary core is starting up let it run its
 99          * calibrations, then wait for it to finish
100          */
101         spin_unlock(&boot_lock);
102 
103         return pen_release != -1 ? -ENOSYS : 0;
104 }
105 
106 static void __init wakeup_secondary(void)
107 {
108         void __iomem *backupram;
109 
110         if (cpu_is_u8500_family() || cpu_is_ux540_family())
111                 backupram = __io_address(U8500_BACKUPRAM0_BASE);
112         else
113                 ux500_unknown_soc();
114 
115         /*
116          * write the address of secondary startup into the backup ram register
117          * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
118          * backup ram register at offset 0x1FF0, which is what boot rom code
119          * is waiting for. This would wake up the secondary core from WFE
120          */
121 #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
122         __raw_writel(virt_to_phys(u8500_secondary_startup),
123                      backupram + UX500_CPU1_JUMPADDR_OFFSET);
124 
125 #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
126         __raw_writel(0xA1FEED01,
127                      backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
128 
129         /* make sure write buffer is drained */
130         mb();
131 }
132 
133 /*
134  * Initialise the CPU possible map early - this describes the CPUs
135  * which may be present or become present in the system.
136  */
137 static void __init ux500_smp_init_cpus(void)
138 {
139         void __iomem *scu_base = scu_base_addr();
140         unsigned int i, ncores;
141 
142         ncores = scu_base ? scu_get_core_count(scu_base) : 1;
143 
144         /* sanity check */
145         if (ncores > nr_cpu_ids) {
146                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
147                         ncores, nr_cpu_ids);
148                 ncores = nr_cpu_ids;
149         }
150 
151         for (i = 0; i < ncores; i++)
152                 set_cpu_possible(i, true);
153 }
154 
155 static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
156 {
157 
158         scu_enable(scu_base_addr());
159         wakeup_secondary();
160 }
161 
162 struct smp_operations ux500_smp_ops __initdata = {
163         .smp_init_cpus          = ux500_smp_init_cpus,
164         .smp_prepare_cpus       = ux500_smp_prepare_cpus,
165         .smp_secondary_init     = ux500_secondary_init,
166         .smp_boot_secondary     = ux500_boot_secondary,
167 #ifdef CONFIG_HOTPLUG_CPU
168         .cpu_die                = ux500_cpu_die,
169 #endif
170 };
171 

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