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Linux/arch/arm/mach-ux500/platsmp.c

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  1 /*
  2  * Copyright (C) 2002 ARM Ltd.
  3  * Copyright (C) 2008 STMicroelctronics.
  4  * Copyright (C) 2009 ST-Ericsson.
  5  * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
  6  *
  7  * This file is based on arm realview platform
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 #include <linux/init.h>
 14 #include <linux/errno.h>
 15 #include <linux/delay.h>
 16 #include <linux/device.h>
 17 #include <linux/smp.h>
 18 #include <linux/io.h>
 19 #include <linux/irqchip/arm-gic.h>
 20 
 21 #include <asm/cacheflush.h>
 22 #include <asm/smp_plat.h>
 23 #include <asm/smp_scu.h>
 24 
 25 #include <mach/hardware.h>
 26 #include <mach/setup.h>
 27 
 28 #include "id.h"
 29 
 30 /* This is called from headsmp.S to wakeup the secondary core */
 31 extern void u8500_secondary_startup(void);
 32 
 33 /*
 34  * Write pen_release in a way that is guaranteed to be visible to all
 35  * observers, irrespective of whether they're taking part in coherency
 36  * or not.  This is necessary for the hotplug code to work reliably.
 37  */
 38 static void write_pen_release(int val)
 39 {
 40         pen_release = val;
 41         smp_wmb();
 42         __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
 43         outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
 44 }
 45 
 46 static void __iomem *scu_base_addr(void)
 47 {
 48         if (cpu_is_u8500_family() || cpu_is_ux540_family())
 49                 return __io_address(U8500_SCU_BASE);
 50         else
 51                 ux500_unknown_soc();
 52 
 53         return NULL;
 54 }
 55 
 56 static DEFINE_SPINLOCK(boot_lock);
 57 
 58 static void __cpuinit ux500_secondary_init(unsigned int cpu)
 59 {
 60         /*
 61          * if any interrupts are already enabled for the primary
 62          * core (e.g. timer irq), then they will not have been enabled
 63          * for us: do so
 64          */
 65         gic_secondary_init(0);
 66 
 67         /*
 68          * let the primary processor know we're out of the
 69          * pen, then head off into the C entry point
 70          */
 71         write_pen_release(-1);
 72 
 73         /*
 74          * Synchronise with the boot thread.
 75          */
 76         spin_lock(&boot_lock);
 77         spin_unlock(&boot_lock);
 78 }
 79 
 80 static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
 81 {
 82         unsigned long timeout;
 83 
 84         /*
 85          * set synchronisation state between this boot processor
 86          * and the secondary one
 87          */
 88         spin_lock(&boot_lock);
 89 
 90         /*
 91          * The secondary processor is waiting to be released from
 92          * the holding pen - release it, then wait for it to flag
 93          * that it has been released by resetting pen_release.
 94          */
 95         write_pen_release(cpu_logical_map(cpu));
 96 
 97         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 98 
 99         timeout = jiffies + (1 * HZ);
100         while (time_before(jiffies, timeout)) {
101                 if (pen_release == -1)
102                         break;
103         }
104 
105         /*
106          * now the secondary core is starting up let it run its
107          * calibrations, then wait for it to finish
108          */
109         spin_unlock(&boot_lock);
110 
111         return pen_release != -1 ? -ENOSYS : 0;
112 }
113 
114 static void __init wakeup_secondary(void)
115 {
116         void __iomem *backupram;
117 
118         if (cpu_is_u8500_family() || cpu_is_ux540_family())
119                 backupram = __io_address(U8500_BACKUPRAM0_BASE);
120         else
121                 ux500_unknown_soc();
122 
123         /*
124          * write the address of secondary startup into the backup ram register
125          * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
126          * backup ram register at offset 0x1FF0, which is what boot rom code
127          * is waiting for. This would wake up the secondary core from WFE
128          */
129 #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
130         __raw_writel(virt_to_phys(u8500_secondary_startup),
131                      backupram + UX500_CPU1_JUMPADDR_OFFSET);
132 
133 #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
134         __raw_writel(0xA1FEED01,
135                      backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
136 
137         /* make sure write buffer is drained */
138         mb();
139 }
140 
141 /*
142  * Initialise the CPU possible map early - this describes the CPUs
143  * which may be present or become present in the system.
144  */
145 static void __init ux500_smp_init_cpus(void)
146 {
147         void __iomem *scu_base = scu_base_addr();
148         unsigned int i, ncores;
149 
150         ncores = scu_base ? scu_get_core_count(scu_base) : 1;
151 
152         /* sanity check */
153         if (ncores > nr_cpu_ids) {
154                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
155                         ncores, nr_cpu_ids);
156                 ncores = nr_cpu_ids;
157         }
158 
159         for (i = 0; i < ncores; i++)
160                 set_cpu_possible(i, true);
161 }
162 
163 static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
164 {
165 
166         scu_enable(scu_base_addr());
167         wakeup_secondary();
168 }
169 
170 struct smp_operations ux500_smp_ops __initdata = {
171         .smp_init_cpus          = ux500_smp_init_cpus,
172         .smp_prepare_cpus       = ux500_smp_prepare_cpus,
173         .smp_secondary_init     = ux500_secondary_init,
174         .smp_boot_secondary     = ux500_boot_secondary,
175 #ifdef CONFIG_HOTPLUG_CPU
176         .cpu_die                = ux500_cpu_die,
177 #endif
178 };
179 

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