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Linux/arch/arm/mach-zynq/common.c

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  1 /*
  2  * This file contains common code that is intended to be used across
  3  * boards so that it's not replicated.
  4  *
  5  *  Copyright (C) 2011 Xilinx
  6  *
  7  * This software is licensed under the terms of the GNU General Public
  8  * License version 2, as published by the Free Software Foundation, and
  9  * may be copied, distributed, and modified under those terms.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  */
 16 
 17 #include <linux/init.h>
 18 #include <linux/kernel.h>
 19 #include <linux/cpumask.h>
 20 #include <linux/platform_device.h>
 21 #include <linux/clk.h>
 22 #include <linux/clk-provider.h>
 23 #include <linux/clk/zynq.h>
 24 #include <linux/clocksource.h>
 25 #include <linux/of_address.h>
 26 #include <linux/of_irq.h>
 27 #include <linux/of_platform.h>
 28 #include <linux/of.h>
 29 #include <linux/memblock.h>
 30 #include <linux/irqchip.h>
 31 #include <linux/irqchip/arm-gic.h>
 32 #include <linux/slab.h>
 33 #include <linux/sys_soc.h>
 34 
 35 #include <asm/mach/arch.h>
 36 #include <asm/mach/map.h>
 37 #include <asm/mach/time.h>
 38 #include <asm/mach-types.h>
 39 #include <asm/page.h>
 40 #include <asm/pgtable.h>
 41 #include <asm/smp_scu.h>
 42 #include <asm/system_info.h>
 43 #include <asm/hardware/cache-l2x0.h>
 44 
 45 #include "common.h"
 46 
 47 #define ZYNQ_DEVCFG_MCTRL               0x80
 48 #define ZYNQ_DEVCFG_PS_VERSION_SHIFT    28
 49 #define ZYNQ_DEVCFG_PS_VERSION_MASK     0xF
 50 
 51 void __iomem *zynq_scu_base;
 52 
 53 /**
 54  * zynq_memory_init - Initialize special memory
 55  *
 56  * We need to stop things allocating the low memory as DMA can't work in
 57  * the 1st 512K of memory.
 58  */
 59 static void __init zynq_memory_init(void)
 60 {
 61         if (!__pa(PAGE_OFFSET))
 62                 memblock_reserve(__pa(PAGE_OFFSET), __pa(swapper_pg_dir));
 63 }
 64 
 65 static struct platform_device zynq_cpuidle_device = {
 66         .name = "cpuidle-zynq",
 67 };
 68 
 69 /**
 70  * zynq_get_revision - Get Zynq silicon revision
 71  *
 72  * Return: Silicon version or -1 otherwise
 73  */
 74 static int __init zynq_get_revision(void)
 75 {
 76         struct device_node *np;
 77         void __iomem *zynq_devcfg_base;
 78         u32 revision;
 79 
 80         np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-devcfg-1.0");
 81         if (!np) {
 82                 pr_err("%s: no devcfg node found\n", __func__);
 83                 return -1;
 84         }
 85 
 86         zynq_devcfg_base = of_iomap(np, 0);
 87         if (!zynq_devcfg_base) {
 88                 pr_err("%s: Unable to map I/O memory\n", __func__);
 89                 return -1;
 90         }
 91 
 92         revision = readl(zynq_devcfg_base + ZYNQ_DEVCFG_MCTRL);
 93         revision >>= ZYNQ_DEVCFG_PS_VERSION_SHIFT;
 94         revision &= ZYNQ_DEVCFG_PS_VERSION_MASK;
 95 
 96         iounmap(zynq_devcfg_base);
 97 
 98         return revision;
 99 }
100 
101 static void __init zynq_init_late(void)
102 {
103         zynq_core_pm_init();
104         zynq_pm_late_init();
105 }
106 
107 /**
108  * zynq_init_machine - System specific initialization, intended to be
109  *                     called from board specific initialization.
110  */
111 static void __init zynq_init_machine(void)
112 {
113         struct platform_device_info devinfo = { .name = "cpufreq-dt", };
114         struct soc_device_attribute *soc_dev_attr;
115         struct soc_device *soc_dev;
116         struct device *parent = NULL;
117 
118         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
119         if (!soc_dev_attr)
120                 goto out;
121 
122         system_rev = zynq_get_revision();
123 
124         soc_dev_attr->family = kasprintf(GFP_KERNEL, "Xilinx Zynq");
125         soc_dev_attr->revision = kasprintf(GFP_KERNEL, "0x%x", system_rev);
126         soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "0x%x",
127                                          zynq_slcr_get_device_id());
128 
129         soc_dev = soc_device_register(soc_dev_attr);
130         if (IS_ERR(soc_dev)) {
131                 kfree(soc_dev_attr->family);
132                 kfree(soc_dev_attr->revision);
133                 kfree(soc_dev_attr->soc_id);
134                 kfree(soc_dev_attr);
135                 goto out;
136         }
137 
138         parent = soc_device_to_device(soc_dev);
139 
140 out:
141         /*
142          * Finished with the static registrations now; fill in the missing
143          * devices
144          */
145         of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
146 
147         platform_device_register(&zynq_cpuidle_device);
148         platform_device_register_full(&devinfo);
149 }
150 
151 static void __init zynq_timer_init(void)
152 {
153         zynq_early_slcr_init();
154 
155         zynq_clock_init();
156         of_clk_init(NULL);
157         clocksource_of_init();
158 }
159 
160 static struct map_desc zynq_cortex_a9_scu_map __initdata = {
161         .length = SZ_256,
162         .type   = MT_DEVICE,
163 };
164 
165 static void __init zynq_scu_map_io(void)
166 {
167         unsigned long base;
168 
169         base = scu_a9_get_base();
170         zynq_cortex_a9_scu_map.pfn = __phys_to_pfn(base);
171         /* Expected address is in vmalloc area that's why simple assign here */
172         zynq_cortex_a9_scu_map.virtual = base;
173         iotable_init(&zynq_cortex_a9_scu_map, 1);
174         zynq_scu_base = (void __iomem *)base;
175         BUG_ON(!zynq_scu_base);
176 }
177 
178 /**
179  * zynq_map_io - Create memory mappings needed for early I/O.
180  */
181 static void __init zynq_map_io(void)
182 {
183         debug_ll_io_init();
184         zynq_scu_map_io();
185 }
186 
187 static void __init zynq_irq_init(void)
188 {
189         irqchip_init();
190 }
191 
192 static const char * const zynq_dt_match[] = {
193         "xlnx,zynq-7000",
194         NULL
195 };
196 
197 DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
198         /* 64KB way size, 8-way associativity, parity disabled */
199         .l2c_aux_val    = 0x00400000,
200         .l2c_aux_mask   = 0xffbfffff,
201         .smp            = smp_ops(zynq_smp_ops),
202         .map_io         = zynq_map_io,
203         .init_irq       = zynq_irq_init,
204         .init_machine   = zynq_init_machine,
205         .init_late      = zynq_init_late,
206         .init_time      = zynq_timer_init,
207         .dt_compat      = zynq_dt_match,
208         .reserve        = zynq_memory_init,
209 MACHINE_END
210 

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