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Linux/arch/arm/mach-zynq/slcr.c

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  1 /*
  2  * Xilinx SLCR driver
  3  *
  4  * Copyright (c) 2011-2013 Xilinx Inc.
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License
  8  * as published by the Free Software Foundation; either version
  9  * 2 of the License, or (at your option) any later version.
 10  *
 11  * You should have received a copy of the GNU General Public
 12  * License along with this program; if not, write to the Free
 13  * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
 14  * 02139, USA.
 15  */
 16 
 17 #include <linux/export.h>
 18 #include <linux/io.h>
 19 #include <linux/fs.h>
 20 #include <linux/interrupt.h>
 21 #include <linux/init.h>
 22 #include <linux/kernel.h>
 23 #include <linux/module.h>
 24 #include <linux/of_address.h>
 25 #include <linux/uaccess.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/slab.h>
 28 #include <linux/string.h>
 29 #include <linux/clk/zynq.h>
 30 #include "common.h"
 31 
 32 #define SLCR_UNLOCK_MAGIC               0xDF0D
 33 #define SLCR_UNLOCK                     0x8   /* SCLR unlock register */
 34 
 35 #define SLCR_PS_RST_CTRL_OFFSET         0x200 /* PS Software Reset Control */
 36 
 37 #define SLCR_A9_CPU_CLKSTOP             0x10
 38 #define SLCR_A9_CPU_RST                 0x1
 39 
 40 #define SLCR_A9_CPU_RST_CTRL            0x244 /* CPU Software Reset Control */
 41 #define SLCR_REBOOT_STATUS              0x258 /* PS Reboot Status */
 42 
 43 void __iomem *zynq_slcr_base;
 44 
 45 /**
 46  * zynq_slcr_system_reset - Reset the entire system.
 47  */
 48 void zynq_slcr_system_reset(void)
 49 {
 50         u32 reboot;
 51 
 52         /*
 53          * Unlock the SLCR then reset the system.
 54          * Note that this seems to require raw i/o
 55          * functions or there's a lockup?
 56          */
 57         writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK);
 58 
 59         /*
 60          * Clear 0x0F000000 bits of reboot status register to workaround
 61          * the FSBL not loading the bitstream after soft-reboot
 62          * This is a temporary solution until we know more.
 63          */
 64         reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS);
 65         writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS);
 66         writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);
 67 }
 68 
 69 /**
 70  * zynq_slcr_cpu_start - Start cpu
 71  * @cpu:        cpu number
 72  */
 73 void zynq_slcr_cpu_start(int cpu)
 74 {
 75         /* enable CPUn */
 76         writel(SLCR_A9_CPU_CLKSTOP << cpu,
 77                zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);
 78         /* enable CLK for CPUn */
 79         writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);
 80 }
 81 
 82 /**
 83  * zynq_slcr_cpu_stop - Stop cpu
 84  * @cpu:        cpu number
 85  */
 86 void zynq_slcr_cpu_stop(int cpu)
 87 {
 88         /* stop CLK and reset CPUn */
 89         writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu,
 90                zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);
 91 }
 92 
 93 /**
 94  * zynq_slcr_init
 95  * Returns 0 on success, negative errno otherwise.
 96  *
 97  * Called early during boot from platform code to remap SLCR area.
 98  */
 99 int __init zynq_slcr_init(void)
100 {
101         struct device_node *np;
102 
103         np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
104         if (!np) {
105                 pr_err("%s: no slcr node found\n", __func__);
106                 BUG();
107         }
108 
109         zynq_slcr_base = of_iomap(np, 0);
110         if (!zynq_slcr_base) {
111                 pr_err("%s: Unable to map I/O memory\n", __func__);
112                 BUG();
113         }
114 
115         /* unlock the SLCR so that registers can be changed */
116         writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK);
117 
118         pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
119 
120         xilinx_zynq_clocks_init(zynq_slcr_base);
121 
122         of_node_put(np);
123 
124         return 0;
125 }
126 

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